URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- This comparison shows the changes necessary to convert path
/
- from Rev 215 to Rev 216
- ↔ Reverse comparison
Rev 215 → Rev 216
/trunk/rtl/vhdl/system/syn_ram-lpm-a.vhd
3,7 → 3,7
-- A synchronous parametrizable RAM instantiating a standard RAM from |
-- the Altera LPM. |
-- |
-- $Id: syn_ram-lpm-a.vhd,v 1.3 2005-09-07 17:39:34 arniml Exp $ |
-- $Id: syn_ram-lpm-a.vhd,v 1.4 2005-11-14 21:12:57 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
94,7 → 94,7
address => ram_addr_i, |
we => ram_we_i, |
inclock => clk_i, |
outclock => zero_s, -- unused |
outclock => clk_i, |
q => ram_data_o |
); |
|
105,6 → 105,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2005/09/07 17:39:34 arniml |
-- fix missing assignment to outclock |
-- |
-- Revision 1.2 2004/04/07 22:09:08 arniml |
-- remove unused signals |
-- |
/trunk/rtl/vhdl/system/syn_rom-lpm-a.vhd
3,7 → 3,7
-- A synchronous parametrizable ROM instantiating a standard ROM from |
-- the Altera LPM. |
-- |
-- $Id: syn_rom-lpm-a.vhd,v 1.2 2005-09-07 17:39:34 arniml Exp $ |
-- $Id: syn_rom-lpm-a.vhd,v 1.3 2005-11-14 21:13:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
91,7 → 91,7
port map ( |
address => rom_addr_i, |
inclock => clk_i, |
outclock => zero_s, -- unused |
outclock => clk_i, |
memenab => one_s, |
q => rom_data_o |
); |
103,6 → 103,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/09/07 17:39:34 arniml |
-- fix missing assignment to outclock |
-- |
-- Revision 1.1 2004/03/24 21:32:27 arniml |
-- initial check-in |
-- |