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/trunk/bench/verilog/test_bench_top.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.6 2001-11-29 02:17:36 rudi Exp $
// $Id: test_bench_top.v,v 1.7 2002-01-21 13:10:37 rudi Exp $
//
// $Date: 2001-11-29 02:17:36 $
// $Revision: 1.6 $
// $Date: 2002-01-21 13:10:37 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2001/11/29 02:17:36 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.5 2001/11/13 00:45:15 rudi
//
// Just minor test bench update, syncing all the files.
156,6 → 166,7
integer read, write;
integer done;
integer adr;
integer do_quick;
 
/////////////////////////////////////////////////////////////////////
//
215,6 → 226,7
$shm_probe("AS",test,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
do_quick = 0;
poc_mode = 1;
#1;
poc_mode = 0;
260,6 → 272,7
sdram_rd4(0);
sdram_wr4(0);
sdram_wp(0);
sdram_bo;
sdram_rmw1(0);
sdram_rmw2(0);
rmw_cross1(0);
290,7 → 303,9
$display(" : :");
$display(" : Short Regression Run ... :");
$display(" :....................................................:");
do_quick = 1;
verbose = 0;
LVL = 1;
 
`ifdef FLASH
boot(LVL);
310,6 → 325,7
sdram_wr4(LVL);
 
sdram_wp(LVL);
sdram_bo;
sdram_rmw1(LVL);
sdram_rmw2(LVL);
rmw_cross1(LVL);
335,14 → 351,14
 
mc_reset;
end
//else
if(0) // Suspend resume testing
if(do_quick) // Suspend resume testing
begin
$display(" ......................................................");
$display(" : :");
$display(" : Suspend Resume Testing ... :");
$display(" :....................................................:");
verbose = 0;
//verbose = 0;
//LVL = 1;
done = 0;
fork
begin
374,12 → 390,16
while(susp_req | suspended) @(posedge clk);
sdram_wp(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_bo;
while(susp_req | suspended) @(posedge clk);
sdram_rmw1(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rmw2(LVL);
 
while(susp_req | suspended) @(posedge clk);
rmw_cross1(LVL);
 
 
`ifdef MULTI_SDRAM
while(susp_req | suspended) @(posedge clk);
sdram_rd5(LVL);
387,7 → 407,6
sdram_wr5(LVL);
`endif
 
 
`ifdef FLASH
while(susp_req | suspended) @(posedge clk);
asc_rdwr1(LVL);
428,8 → 447,7
 
mc_reset;
end
//else
if(0) // Bus Request testing
if(do_quick) // Bus Request testing
begin
$display(" ......................................................");
$display(" : :");
454,6 → 472,7
sdram_rd4(LVL);
sdram_wr4(LVL);
sdram_wp(LVL);
sdram_bo;
sdram_rmw1(LVL);
sdram_rmw2(LVL);
 
490,54 → 509,15
join
end
else
if(1) // Debug Tests
if(0) // Debug Tests
begin
$display(" ......................................................");
$display(" : :");
$display(" : Test Debug Testing ... :");
$display(" :....................................................:");
//verbose = 0;
verbose = 0;
//boot(2);
 
/*
`define CSR 8'h00
`define POC 8'h04
`define BA_MASK 8'h08
 
`define CSR_MASK 32'hff00_07fe
`define BAM_MASK 32'h0000_07ff
`define CSC_MASK 32'hffff_ffff
`define TMS_MASK 32'hffff_ffff
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_ffff);
 
m0.wb_rd1(`REG_BASE + `CSR, 4'hf, data);
m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC0, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS0, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC1, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS1, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC2, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS2, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC3, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS3, 4'hf, data);
 
 
*/
 
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
//sdram_rd1(2);
//sdram_wr1(2);
566,10 → 546,7
 
 
 
//sdram_rd1(2);
//sdram_wr1(2);
 
 
//sdram_rd4(2);
//sdram_wr4(2);
//sdram_rd5(2);
599,15 → 576,20
sdram_wr3(2);
sdram_rd4(2);
sdram_wr4(2);
 
 
sdram_rd5(2);
sdram_wr5(2);
 
sdram_wp(2);
 
sdram_rmw1(2);
sdram_rmw2(2);
rmw_cross1(2);
 
 
 
 
repeat(100) @(posedge clk);
$finish;
end
717,6 → 699,25
// IO Buffers
//
 
reg rst_r1, rst_r2, rst_r3, rst_r4;
 
always @(posedge clk or posedge rst)
if(rst) rst_r1 <= #1 1'b1;
else rst_r1 <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if(rst) rst_r2 <= #1 1'b1;
else rst_r2 <= #1 rst_r1;
 
always @(posedge clk or posedge rst)
if(rst) rst_r3 <= #1 1'b1;
else rst_r3 <= #1 rst_r2;
 
always @(posedge clk or posedge rst)
if(rst) rst_r4 <= #1 1'b1;
else rst_r4 <= #1 rst_r3;
 
 
wire [31:0] mc_dq;
wire [3:0] mc_dqp;
wire [23:0] _mc_addr;
743,30 → 744,7
default: rst_dq_val = 32'hzzzz_zzzz;
endcase
 
/*
assign #1 mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
assign #1 mc_data_i = mc_dq;
 
assign #1 mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
assign #1 mc_dp_i = mc_dqp;
 
assign #1 mc_addr = mc_c_oe ? _mc_addr : 24'bz;
assign #1 mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
assign #1 mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
assign #1 mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
assign #1 mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
assign #1 mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
assign #1 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign #1 mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
assign #1 mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
assign #1 mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
assign #1 mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
assign #1 mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign #1 mc_zz = mc_c_oe ? _mc_zz : 1'bz;
*/
 
 
assign mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
assign mc_dq = mc_data_oe ? mc_data_o : (rst_r4 ? rst_dq_val : 32'hzzzz_zzzz);
assign mc_data_i = mc_dq;
 
assign mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
786,9 → 764,6
assign mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
 
 
 
pullup p0(mc_cas_);
pullup p1(mc_ras_);
pullup p2(mc_oe_);
893,6 → 868,8
// Memory Models
//
 
wire [27:0] dq_tmp;
 
`ifdef SDRAM0
// Model: MT48LC2M32B2 (2Meg x 32 x 4 Banks)
mt48lc2m32b2 sdram0(
908,7 → 885,6
.Dqm( mc_dqm )
);
 
wire [27:0] dq_tmp;
mt48lc2m32b2 sdram0p(
.Dq( {dq_tmp, mc_dqp}),
.Addr( mc_addr[10:0] ),
922,35 → 898,8
.Dqm( mc_dqm )
);
 
task fill_mem;
input size;
 
integer size, n;
reg [31:0] data;
 
begin
sdram0.mem_fill(size);
 
for(n=0;n<size;n=n+1)
begin
data = sdram0.Bank0[n];
sdram0p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank1[n];
sdram0p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank2[n];
sdram0p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank3[n];
sdram0p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
end
 
 
end
endtask
 
 
`endif
 
 
`ifdef MULTI_SDRAM
// Model: MT48LC2M32B2 (2Meg x 32 x 4 Banks)
 
967,6 → 916,20
.Dqm( mc_dqm )
);
 
mt48lc2m32b2 sdram1p(
.Dq( {dq_tmp, mc_dqp} ),
.Addr( mc_addr[10:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[1] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm )
);
 
 
// Model: MT48LC2M32B2 (2Meg x 32 x 4 Banks)
mt48lc2m32b2 sdram2(
.Dq( mc_dq ),
981,6 → 944,18
.Dqm( mc_dqm )
);
 
mt48lc2m32b2 sdram2p(
.Dq( {dq_tmp, mc_dqp}),
.Addr( mc_addr[10:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[2] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm )
);
 
mt48lc16m16a2 sdram1a(
.Dq( mc_dq[15:0] ),
1008,60 → 983,6
.Dqm( mc_dqm[3:2] )
);
 
/*
mt48lc8m8a2 sdram2a(
.Dq( mc_dq[07:00] ),
.Addr( mc_addr[11:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[2] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm[0] )
);
 
mt48lc8m8a2 sdram2b(
.Dq( mc_dq[15:08] ),
.Addr( mc_addr[11:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[2] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm[1] )
);
 
mt48lc8m8a2 sdram2c(
.Dq( mc_dq[23:16] ),
.Addr( mc_addr[11:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[2] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm[2] )
);
 
mt48lc8m8a2 sdram2d(
.Dq( mc_dq[31:24] ),
.Addr( mc_addr[11:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[2] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
.Dqm( mc_dqm[3] )
);
*/
 
`endif
 
`ifdef FLASH
/trunk/bench/verilog/sram_models/MicronSRAM/mt58l1my18d.v
100,14 → 100,16
input x;
 
integer a, n, x;
 
reg [15:0] data;
begin
 
a=0;
for(n=0;n<x;n=n+1)
begin
bank0[n] = a;
bank1[n] = a+1;
data = a;
bank0[n] = { ^data[15:8], data[15:8], ^data[7:0], data[7:0]};
data = a+1;
bank1[n] = { ^data[15:8], data[15:8], ^data[7:0], data[7:0]};
a=a+2;
end
 
/trunk/bench/verilog/tests.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: tests.v,v 1.6 2001-11-29 02:17:36 rudi Exp $
// $Id: tests.v,v 1.7 2002-01-21 13:10:37 rudi Exp $
//
// $Date: 2001-11-29 02:17:36 $
// $Revision: 1.6 $
// $Date: 2002-01-21 13:10:37 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2001/11/29 02:17:36 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.5 2001/11/13 00:45:19 rudi
//
// Just minor test bench update, syncing all the files.
123,10 → 133,12
for(kro=0;kro<2;kro=kro+1)
for(bas=0;bas<2;bas=bas+1)
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021 | (bas<<9) | (kro<<10));
 
sdram0.mem_fill(1024);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas<<9) | (kro<<10));
 
fill_mem(1024);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
178,164 → 190,6
endtask
 
 
 
 
task sdram_rd1b;
input quick;
 
integer quick;
integer n;
integer del, size;
reg [7:0] mode;
reg [2:0] bs;
integer sz_inc;
integer sz_max, del_max;
integer write;
reg [31:0] memd;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** SDRAM Size, Delay & Mode Read test 1B ... ***");
$display("*****************************************************\n");
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd3 // Burst Length
});
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
m0.wb_wr1(`REG_BASE + `CSC5, 4'hf, 32'h0000_0091);
 
case(quick)
0: sz_max = 64;
1: sz_max = 32;
2: sz_max = 16;
endcase
 
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
endcase
 
size = 4;
del = 1;
mode = 2;
write = 0;
//force sdram0.Debug = 1;
 
for(mode=0;mode<10;mode=mode+1)
begin
sdram1a.mem_fill(1024);
sdram1b.mem_fill(1024);
//sdram0p.mem_fill(1024);
 
case(mode[3:1])
0: bs = 0;
1: bs = 1;
2: bs = 2;
3: bs = 3;
4: bs = 7;
endcase
case(mode[3:1])
0: sz_inc = 1;
1: sz_inc = 2;
2: sz_inc = 4;
3: sz_inc = 8;
4: sz_inc = 1;
endcase
 
 
/*
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
*/
 
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
4'd3, // Trp [23:20]
3'd3, // Trcd [19:17]
2'd2, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
 
if(!verbose) $display("Mode: %b", mode);
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
m0.mem_fill;
 
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
 
if(write) m0.wb_wr_mult(`MEM_BASE + 0, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + 0, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*1*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*1*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*2*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*2*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
 
for(n=0;n<(size*4);n=n+1)
begin
memd = {sdram1b.Bank0[n], sdram1a.Bank0[n]};
 
if((memd !== m0.rd_mem[n]) |
(|memd === 1'bx) |
(|m0.rd_mem[n] === 1'bx) )
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, memd, m0.rd_mem[n], $time);
error_cnt = error_cnt + 1;
end
end
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
endtask
 
 
task sdram_rd1;
input quick;
 
372,8 → 226,8
3'd3 // Burst Length
});
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
 
case(quick)
0: sz_max = 64;
390,13 → 244,13
size = 4;
del = 0;
mode = 2;
write = 0;
write = 1; // enable writes for parity !
 
//force sdram0.Debug = 1;
 
for(mode=0;mode<10;mode=mode+1)
begin
sdram0.mem_fill(1024);
//sdram0p.mem_fill(1024);
 
case(mode[3:1])
0: bs = 0;
414,25 → 268,8
4: sz_inc = 1;
endcase
 
 
/*
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
*/
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
4'd3, // Trp [23:20]
3'd3, // Trcd [19:17]
524,6 → 361,7
3'd3 // Burst Length
});
 
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
 
case(quick)
683,6 → 521,7
bas = 0;
for(bas=0;bas<2;bas=bas+1)
begin
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas[0]<<9));
 
size = 33;
791,8 → 630,6
endtask
 
 
 
 
task sdram_wr2;
input quick;
 
838,8 → 675,8
for(bas=0;bas<2;bas=bas+1)
begin
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021 | (bas[0]<<9));
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas[0]<<9));
 
case(quick)
0: sz_max = 32;
856,7 → 693,6
size = 3;
del = 0;
mode = 10;
read = 1;
//force sdram0.Debug = 1;
 
for(mode=0;mode<20;mode=mode+1)
913,24 → 749,16
bas, mode, size, del);
 
m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);
m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);
 
m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);
m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);
 
m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);
m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);
 
m0.wb_wr_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);
m0.wb_wr_mult(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size);
 
repeat(10) @(posedge clk);
 
948,16 → 776,6
3: data = sdram0.Bank3[n+3*size*2];
endcase
 
 
if(read & 0)
if((data !== m0.rd_mem[(m*size*2)+n]) | (|data === 1'bx) |
(|m0.rd_mem[(m*size*2)+n] === 1'bx) )
begin
$display("ERROR: RD Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*size*2)+n, data, m0.rd_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
end
 
if((data !== m0.wr_mem[(m*size*2)+n]) | (|data === 1'bx) |
(|m0.wr_mem[(m*size*2)+n] === 1'bx) )
begin
1018,7 → 836,8
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21);
 
case(quick)
0: sz_max = 65;
1092,7 → 911,6
 
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
 
//bw_clear;
if(write) m0.wb_wr_mult(`MEM_BASE + 0, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + 0, 4'hf, del, size);
 
1105,8 → 923,6
if(write) m0.wb_wr_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
 
//bw_report;
 
for(n=0;n<(size*4);n=n+1)
begin
if((sdram0.Bank0[n] !== m0.rd_mem[n]) |
1168,7 → 984,8
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21);
 
case(quick)
0: sz_max = 64;
1185,7 → 1002,7
size = 8;
del = 0;
mode = 16;
read = 0;
read = 1;
//force sdram0.Debug = 1;
 
for(mode=0;mode<20;mode=mode+1)
1341,8 → 1158,11
bas = 0;
for(bas=0;bas<2;bas=bas+1)
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
fill_mem(1024);
 
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21 | (bas[0]<<9));
 
size = 2;
del = 3;
mode = 0;
1509,7 → 1329,8
for(bas=0;bas<2;bas=bas+1)
begin
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21 | (bas[0]<<9));
 
case(quick)
0: sz_max = 32;
1531,7 → 1352,8
for(mode=0;mode<20;mode=mode+1)
begin
 
sdram0.mem_fill(1024);
//sdram0.mem_fill(1024);
fill_mem(1024);
 
case(mode[4:2])
0: bs = 0;
1722,13 → 1544,15
bas = 0;
for(bas=0;bas<2;bas=bas+1)
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0021 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0421 | (bas[0]<<9));
 
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0c21 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0c21 | (bas[0]<<9));
 
size = 2;
del = 0;
mode = 4;
del = 3;
mode = 0;
write = 1;
if(0)
begin
1737,13 → 1561,17
force sdram2.Debug = 1;
end
 
//for(mode=0;mode<10;mode=mode+1)
for(mode=0;mode<10;mode=mode+1)
for(mode=0;mode<10;mode=mode+1)
begin
sdram0.mem_fill(1024);
sdram1.mem_fill(1024);
sdram2.mem_fill(1024);
//sdram0.mem_fill(1024);
//sdram1.mem_fill(1024);
//sdram2.mem_fill(1024);
 
fill_mem(1024);
fill_mem1(1024);
fill_mem2(1024);
 
case(mode[3:1])
0: bs = 0;
1: bs = 1;
1807,7 → 1635,6
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
//for(size=sz_inc;size<8;size=size+sz_inc)
begin
m0.mem_fill;
if(verbose) $display("BAS: %0d, Mode: %b, Size: %0d, Delay: %0d",
2025,9 → 1852,10
for(bas=0;bas<2;bas=bas+1)
begin
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0421 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0421 | (bas[0]<<9));
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0c21 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0c21 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0c21 | (bas[0]<<9));
 
case(quick)
0: sz_max = 32;
2056,10 → 1884,14
for(mode=0;mode<20;mode=mode+1)
begin
 
sdram0.mem_fill(1024);
sdram1.mem_fill(1024);
sdram2.mem_fill(1024);
//sdram0.mem_fill(1024);
//sdram1.mem_fill(1024);
//sdram2.mem_fill(1024);
 
fill_mem(1024);
fill_mem1(1024);
fill_mem2(1024);
 
case(mode[4:2])
0: bs = 0;
1: bs = 1;
2289,6 → 2121,7
3'd3 // Burst Length
});
 
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
 
case(quick)
2358,7 → 2191,7
endcase
 
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
if(!verbose) $display("Mode: %b, Bus Width: %0d, Cycle Delay: %0d", mode, a_mode, cycle);
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
2401,7 → 2234,6
m0.wb_rmw2(`MEM_BASE3 + size*7*4,
`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size, size);
 
 
repeat(10) @(posedge clk);
 
x = 0;
2460,69 → 2292,6
error_cnt = error_cnt + 1;
end
end
 
 
 
 
/*
m0.mem_fill;
for(n=0;n<1024;n=n+1)
m0.wr_mem[n] = 32'hffff_ffff;
if(verbose) $display("Mode: %0d, Size: %0d, Delay: %0d", mode, size, del);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
 
repeat(10) @(posedge clk);
 
x = 0;
for(n=0;n<(size*4);n=n+1)
begin
 
case(mode)
0: data = {16'hxxxx, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
data[23:16] = x[7:0]+2;
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
end
endcase
 
case(mode)
0: x = x + 1;
1: x = x + 4;
2: x = x + 2;
endcase
 
exp = m0.rd_mem[n];
if(mode==0) exp[31:16] = data[31:16];
 
if(data !== exp)
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, exp, $time);
error_cnt = error_cnt + 1;
end
 
end
*/
 
end
 
end
2579,7 → 2348,6
read = 1;
write = 1;
 
 
sz_max = 6;
for(mode=0;mode<3;mode=mode+1)
begin
2666,142 → 2434,6
end
endtask
 
 
task asc_rdwr1_x;
input quick;
 
integer quick;
integer x,s,n,m,adr;
integer del, size;
reg [7:0] mode;
reg [2:0] bs;
integer sz_inc;
integer sz_max, del_max;
integer read;
reg [2:0] bas;
reg [31:0] data;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** ASC Read/Write Test 1 X ... ***");
$display("*****************************************************\n");
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'h0005_2004);
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005);
 
case(quick)
0: sz_max = 32;
1: sz_max = 32;
2: sz_max = 16;
endcase
 
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
endcase
 
size = 1;
del = 0;
mode = 1;
read = 1;
write = 0;
 
 
//for(mode=0;mode<8;mode=mode+1)
begin
 
repeat(1) @(posedge clk);
 
 
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0081_0005);
 
//m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'h0000_2004 + (mode<<16));
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'h0001_200a);
 
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
 
//for(del=0;del<del_max;del=del+1)
//for(size=1;size<sz_max;size=size+1)
begin
m0.mem_fill;
for(n=0;n<1024;n=n+1)
m0.wr_mem[n] = 32'hffff_ffff;
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
 
repeat(10) @(posedge clk);
 
x = 0;
 
for(n=0;n<(size*4);n=n+1)
begin
 
case(mode)
0: data = {16'hzzzz, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
data[23:16] = x[7:0]+2;
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
 
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
end
endcase
 
case(mode)
0: x = x + 1;
1: x = x + 4;
2: x = x + 2;
endcase
 
//$display("INFO: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
// n, data, m0.rd_mem[n], $time);
 
if(data !== m0.rd_mem[n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, m0.rd_mem[n], $time);
error_cnt = error_cnt + 1;
end
end
 
 
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
task boot;
input quick;
 
2950,15 → 2582,17
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);
 
size = 4;
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0803);
 
size = 5;
del = 0;
read = 1;
write = 0;
write = 1;
 
sram0a.mem_fill( 256 );
sram0b.mem_fill( 256 );
sram0a.mem_fill( 1024 );
sram0b.mem_fill( 1024 );
 
repeat(1) @(posedge clk);
 
2968,28 → 2602,26
m0.mem_fill;
 
$display("Size: %0d, Delay: %0d", size, del);
//bw_clear;
 
if(write) m0.wb_wr_mult(`MEM_BASE4 + 0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 0*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 4*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 4*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 8*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 8*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 12*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 12*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + size * 0 * 16, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + size * 0 * 16, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + size * 1 * 16, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + size * 1 * 16, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + size * 2 * 16, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + size * 2 * 16, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + size * 3 * 16, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + size * 3 * 16, 4'hf, del, size);
 
//bw_report;
 
for(m=0;m< 4;m=m+1)
for(n=0;n< size;n=n+1)
begin
 
`ifdef MICRON
data[07:00] = sram0a.bank0[(m*4)+n];
data[15:08] = sram0a.bank1[(m*4)+n];
data[23:16] = sram0b.bank0[(m*4)+n];
data[31:24] = sram0b.bank1[(m*4)+n];
data[07:00] = sram0a.bank0[(m*size*4)+n];
data[15:08] = sram0a.bank1[(m*size*4)+n];
data[23:16] = sram0b.bank0[(m*size*4)+n];
data[31:24] = sram0b.bank1[(m*size*4)+n];
 
`else
data[07:00] = sram0a.memb1[(m*4)+n];
data[15:08] = sram0a.memb2[(m*4)+n];
2997,10 → 2629,11
data[31:24] = sram0b.memb2[(m*4)+n];
`endif
 
 
if(data !== m0.rd_mem[(m*size)+n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*4)+n, data, m0.rd_mem[(m*size)+n], $time);
(m*size*4)+n, data, m0.rd_mem[(m*size)+n], $time);
error_cnt = error_cnt + 1;
end
 
3032,6 → 2665,7
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0803);
 
size = 4;
3236,8 → 2870,8
3'd3 // Burst Length
});
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0921);
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0121);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0921);
 
wb_err_check_dis=1;
case(quick)
3260,7 → 2894,6
 
for(mode=0;mode<20;mode=mode+1)
begin
//sdram0.mem_fill(1024);
fill_mem(1024);
 
case(mode[4:2])
3360,6 → 2993,7
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0903);
 
size = 17;
3497,6 → 3131,8
for(cycle=0;cycle<8;cycle=cycle+1)
for(kro=0;kro<2;kro=kro+1) // Don't Need this for this test
begin
 
// Parity nabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
 
size = 2;
3580,10 → 3216,10
m0.wb_rmw(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
 
for(m=0;m<4;m=m+1)
for(n=0;n<(size*2);n=n+1)
begin
 
case(m)
0: data = mem0[n];
1: data = mem1[n];
3598,7 → 3234,6
(m*size*2)+n, data, m0.rd_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
end
 
end
 
repeat(10) @(posedge clk);
3695,6 → 3330,8
for(cycle=0;cycle<8;cycle=cycle+1)
for(kro=0;kro<2;kro=kro+1) // Don't Need this for this test
begin
 
// Parity nabled !
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
 
size = 1;
3748,7 → 3385,6
m0.mem_fill;
fill_mem(1024);
 
 
if(verbose) $display("KRO: %0d, Mode: %b, Size: %0d, Delay: %0d, Cyc.Del: %0d (%t)",
kro, mode, size, del, cycle, $time);
 
3821,6 → 3457,7
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);
 
size = 1;
3929,7 → 3566,8
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);
// Parity Enabled !
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0803);
 
size = 4;
del = 4;
3936,7 → 3574,7
 
repeat(1) @(posedge clk);
 
//for(del=0;del<16;del=del+1)
for(del=0;del<16;del=del+1)
for(size=1;size<18;size=size+1)
begin
m0.mem_fill;
/trunk/bench/verilog/test_lib.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: test_lib.v,v 1.3 2001-11-11 01:52:03 rudi Exp $
// $Id: test_lib.v,v 1.4 2002-01-21 13:10:37 rudi Exp $
//
// $Date: 2001-11-11 01:52:03 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:10:37 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/11 01:52:03 rudi
//
// Minor fixes to testbench ...
//
// Revision 1.2 2001/09/02 02:29:43 rudi
//
// Fixed the TMS register setup to be tight and correct.
109,18 → 114,17
while(!suspended) @(posedge clk);
#1;
susp_req = 0;
repeat(20) @(posedge clk);
repeat(20) @(posedge clk);
#1;
resume_req = 1;
while(suspended) @(posedge clk);
#1;
resume_req = 0;
repeat(1) @(posedge clk);
repeat(1) @(posedge clk);
 
end
endtask
 
 
/////////////////////////////////////////////////////////////////////
//
// Bus Request/Grant Task
167,12 → 171,6
always @(posedge clk)
wd_cnt = wd_cnt + 1;
 
/*
always @(posedge clk)
if(wb_cyc_i | wb_ack_o ) wd_cnt <= #1 0;
else wd_cnt <= #1 wd_cnt + 1;
*/
 
always @(wd_cnt)
if(wd_cnt>6000)
begin
182,11 → 180,11
$finish;
end
 
/////////////////////////////////////////////////////////////////////
//
// Show Errors
//
 
 
 
 
 
task show_errors;
 
begin
199,6 → 197,10
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Reset Memory Controller
//
 
task mc_reset;
 
211,3 → 213,82
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Fill SDRAMs
//
 
task fill_mem;
input size;
 
integer size, n;
reg [31:0] data;
 
begin
sdram0.mem_fill(size);
 
for(n=0;n<size;n=n+1)
begin
data = sdram0.Bank0[n];
sdram0p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank1[n];
sdram0p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank2[n];
sdram0p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram0.Bank3[n];
sdram0p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
end
 
end
endtask
 
 
task fill_mem1;
input size;
 
integer size, n;
reg [31:0] data;
 
begin
sdram1.mem_fill(size);
 
for(n=0;n<size;n=n+1)
begin
data = sdram1.Bank0[n];
sdram1p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram1.Bank1[n];
sdram1p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram1.Bank2[n];
sdram1p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram1.Bank3[n];
sdram1p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
end
 
end
endtask
 
task fill_mem2;
input size;
 
integer size, n;
reg [31:0] data;
 
begin
sdram2.mem_fill(size);
 
for(n=0;n<size;n=n+1)
begin
data = sdram2.Bank0[n];
sdram2p.Bank0[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram2.Bank1[n];
sdram2p.Bank1[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram2.Bank2[n];
sdram2p.Bank2[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
data = sdram2.Bank3[n];
sdram2p.Bank3[n] = {28'h0, ^data[31:24], ^data[23:16], ^data[15:8], ^data[7:0] };
end
 
end
endtask
 
 

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