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rtfTextController3

+

 

+

Description

+

This is a text mode video display controller that supports +color. The controller uses several internal +dual ported r/w memories to store text, text attributes and character bitmaps. The display memory is +thirty-two bits wide of which only twenty seven bits are implemented, allowing 512 different +simultaneous characters to be displayed along with 512 background and foreground +colors. The use of internal dual ported memories means that the text +controller does not consume any memory bandwidth from the processor.

+ + + + + + + + + + + + + + + + + + + + + +

+ Address	+ Description
+ $FFD0_xxxx	+ text screen and attribute memory area, currently the controller only supports a 4kx27 memory
+ $FFD2_xxxx	+ character bitmap memory, currently the controller only supports a 4k memory, + which allows 512 8x8 character bitmaps.
+ $FFDA_00xx	+ text controller register area

+

Text and Attribute Memory Layout

+ + + + + + + + + + + + + + +

+ 31  28	+ 27        19	+ 18       10	+ 9                + 0
+ unimp	+ Bk Color	+ Fg Color	+ char code

+ +

Clocks

+ +

The text video display controller uses two clocks, a +bus timing clock (clk_i) and a video timing clock (vclk), which can be +completely independent.

+ +

Register Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Reg. No.	+ 31                                                 + 0	+ R/W	Function	Description
0	+ -------- nnnnnnnn	+ RW	+ number of columns
1	-------- nnnnnnnn	+ RW	+ number of row
2	+ ---- nnnnnnnnnnnn	+ W	+ window left	+ Text window position- pixels before the display starts, referenced to the + hsync signal
3	---- + nnnnnnnnnnnn	+ W	+ window top	+ Text window position - scan lines down from the top of + the screen referenced to the vsync signal
4	+ -------- --- nnnnn	+ W	+ max scanline	+ maximum scan + line used to display chars + default 7.
5	-------- + hhhh wwww	+ W	+ pixel size	+ pixel size in + video clocks and scan lines + default is 1 + (2 video clocks per pixel) and 1 (two video scan lines per pixel).
+ 7	+ -------n nnnnnnnn	+ W	+ Transparent Color	+ color value that corresponds to a transparent background + color
+ 8	+ -------T TBB sssss	+ W	+ cursor start	+ sssss=scan line cursor display starts on + + + + + + + + + + + + + + + + + + + + + + TT + = Cursor Type + 00 + Box + 01 + Line + 10 + Underscore + 11 + Asterisk + + + + + + + + + + + + + + + + + + + + + + + BB + = Cursor Blink Rate + 00 + no blink + 01 + no display + 10 + 1/16 frame rate (4 times per second) + 11 + 1/32 frame rate (2 times per second) +
+     + + 9	-------- + --- eeeee	+ W	+ cursor end	+ scan line cursor display ends on
+ 10	+ aaaaaaaa aaaaaaaa	+ W	+ display offset	+ starting address of the text screen in the display + memory, defaults to zero
+ 11	+ aaaaaaaa aaaaaaaa	+ W	+ cursor position	+ location of the cursor in the display memory
+ 12	+ aaaaaaaa aaaaaaaa	+ R	+ light pen position	+ address of the light pen

+

 

+

Module Interface Description

+

+rtfTextController

+

+module rtfTextController(rst_i, +clk_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, +vclk, hsync, vsync, blank, border, rgbIn, rgbOut);
+
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ System	Description
rst_i	This signal is normally connected to the + system reset signal. It resets the text controller + interface forcing it to the reset state. +
clk_i	This is usually + connected to the system clock and is used as a base timing clock for I/O + operations.
+ + Slave Port
cyc_i	indicates that a valid bus cycle is + taking place. The core will not respond to the bus unless this signal is + active.
+ stb_i	+ This strobe signal also indicates that a valid bus cycle is + taking place
ack_o	This signal indicates that the core has + processed the bus transaction (it is the logical and of cyc_i and stb_i).
we_i	This signal is used to signify a write + operation to the text controller.
adr_i	+ This + thirty-two bit address bus + is used + to address one of text controllers's registers + or internal memory. (Registers are described + below). + Registers respond to the address range $FFDA_00xx +
dat_i	This is the sixteen + bit data input bus to the text controller.
dat_o	This is the sixteen bit data output bus + from the text controller.
+ + Video + Ports
+ vclk	+ This input is the video clock input. Pixel timing is derived from it.
+ hsync	+ Horizontal sync. + This input signal signals the start/end of a video scanline (end-of-line)
+ vsync	+ Vertical sync. This input signal indicates + the end of the video frame.
+ blank	This + input signal indicates that the display should be blanked. It is active + during the video blanking period.
+ + border	+ This input signal indicates that a border area is active.
+ rgbIn	+ This 24 bit input bus can be connected to an external RGB input. (The text + controller may display on top of the external input).
+ rgbOut	+ This output signal bus contains the 24 bit RGB display data.
+ Parameters
+ ROWS	Use this parameter to specify the + default number of text rows.
+ COLS	+ Use this parameter to specify the default number of text columns.

+

 

+

---

+

 

+ +

WISHBONE Compatibility +Datasheet

+

The text controller core may be directly +interfaced to a WISHBONE compatible bus.

+

 

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ WISHBONE + Datasheet + WISHBONE SoC + Architecture Specification, Revision B.3
+	+
+ Description:	+ + Specifications:
+ General + Description:	+ + rtfTextController - Text mode video display controller
+ Supported + Cycles:	+ SLAVE, READ / + WRITE + SLAVE, BLOCK + READ / WRITE + SLAVE, RMW
+ Data port, + size: + Data port, + granularity: + Data port, + maximum operand size: + Data transfer + ordering: + Data transfer + sequencing	+ 32 + bit + 32 bit + + 32 bit + Little Endian + any + (undefined)
+ Clock + frequency constraints:
+ Supported + signal list and cross reference to equivalent WISHBONE signals	+ Signal Name: + ack_o + adr_i(31:0) + clk_i + dat_i(31:0) + dat_o(31:0) + cyc_i + stb_i + we_i	+ WISHBONE + Equiv. + ACK_O + ADR_I() + CLK_I + DAT_I() + DAT_O() + CYC_I + STB_I + WE_I +
+ Special + Requirements:	+ external sync generator

+ +

 

+ +

 

+ + + + \ No newline at end of file