URL
https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk
Subversion Repositories simple_fm_receiver
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/trunk/source/loop_filter.vhdl
1,4 → 1,4
-- $Id: loop_filter.vhdl,v 1.3 2005-03-04 08:06:19 arif_endro Exp $ |
-- $Id: loop_filter.vhdl,v 1.4 2008-06-26 06:16:04 arif_endro Exp $ |
------------------------------------------------------------------------------- |
-- Title : Loop filter component |
-- Project : FM Receiver |
120,15 → 120,21
|
loop_out_div <= multiply_output01; |
|
process (clock, clear) |
-- 20080625 |
-- fixme |
-- how to enable clear signal in here... :( |
|
-- process (clock, clear) |
process (clock) |
|
begin |
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if (clear = '1') then |
-- if (clear = '1') then |
if ((clock = '1') and clock'event) then |
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loop_out <= (others => '0'); |
-- loop_out <= (others => '0'); |
|
elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
-- elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
|
-- loop_out (11) <= adder_output01 (12); |
loop_out (11) <= adder_output01 (11); |
/trunk/source/nco.vhdl
1,4 → 1,4
-- $Id: nco.vhdl,v 1.3 2005-03-04 08:06:20 arif_endro Exp $ |
-- $Id: nco.vhdl,v 1.4 2008-06-26 06:16:04 arif_endro Exp $ |
------------------------------------------------------------------------------- |
-- Title : NCO (Numerical Controlled Oscillator) |
-- Project : FM Receiver |
99,16 → 99,22
address_in (01) <= (adder_output(09)); |
address_in (00) <= (adder_output(08)); |
|
process (clock, clear) |
-- process (clock, clear) |
process (clock) |
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begin |
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if (clear = '1') then |
-- 20080625 |
-- fixme |
-- how to enable clear signal in here... :( |
|
output_nco <= (others => '0'); |
-- if (clear = '1') then |
if ((clock = '1') and clock'event) then |
|
elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
-- output_nco <= (others => '0'); |
|
-- elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
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output_nco (07) <= (output_rom(07)); |
output_nco (06) <= (output_rom(06)); |
output_nco (05) <= (output_rom(05)); |
/trunk/source/fir.vhdl
1,4 → 1,4
-- $Id: fir.vhdl,v 1.4 2005-03-12 04:18:38 arif_endro Exp $ |
-- $Id: fir.vhdl,v 1.5 2008-06-26 06:16:04 arif_endro Exp $ |
------------------------------------------------------------------------------- |
-- Title : FIR Low pass filter |
-- Project : FM Receiver |
245,15 → 245,21
fir_out(01) <= (result_adder15(05)); |
fir_out(00) <= (result_adder15(04)); |
|
process (clock, clear) |
-- 20080625 |
-- fixme |
-- how to enable clear signal in here... :( |
|
-- process (clock, clear) |
process (clock) |
|
begin |
|
if (clear = '1') then |
-- if (clear = '1') then |
if ((clock = '1') and clock'event) then |
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dmout <= (others => '0'); |
-- dmout <= (others => '0'); |
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elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
-- elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then |
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fir_in_02 <= fir_in_01; |
fir_in_03 <= fir_in_02; |