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Rev 22 → Rev 23

/trunk/rtl/core/tv80_mcode.v
46,7 → 46,7
 
input [7:0] IR;
input [1:0] ISet ;
input [2:0] MCycle ;
input [6:0] MCycle ;
input [7:0] F ;
input NMICycle ;
input IntCycle ;
293,15 → 293,12
begin
// LD r,n
MCycles = 3'b010;
case (MCycle)
2 :
begin
Inc_PC = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
default :;
endcase // case(MCycle)
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110 :
308,16 → 305,13
begin
// LD r,(HL)
MCycles = 3'b010;
case (MCycle)
1 :
Set_Addr_To = aXY;
2 :
begin
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
default :;
endcase // case(MCycle)
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111 :
324,17 → 318,14
begin
// LD (HL),r
MCycles = 3'b010;
case (MCycle)
1 :
begin
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
2 :
Write = 1'b1;
default :;
endcase // case(MCycle)
if (MCycle[0])
begin
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[1])
Write = 1'b1;
end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
8'b00110110 :
341,18 → 332,15
begin
// LD (HL),n
MCycles = 3'b011;
case (MCycle)
2 :
begin
Inc_PC = 1'b1;
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
3 :
Write = 1'b1;
default :;
endcase // case(MCycle)
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[2])
Write = 1'b1;
end // case: 8'b00110110
8'b00001010 :
359,13 → 347,10
begin
// LD A,(BC)
MCycles = 3'b010;
case (MCycle)
1 :
Set_Addr_To = aBC;
2 :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
if (MCycle[0])
Set_Addr_To = aBC;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00001010
8'b00011010 :
372,13 → 357,10
begin
// LD A,(DE)
MCycles = 3'b010;
case (MCycle)
1 :
Set_Addr_To = aDE;
2 :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
if (MCycle[0])
Set_Addr_To = aDE;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00011010
8'b00111010 :
387,38 → 369,32
begin
// LDD A,(HL)
MCycles = 3'b010;
case (MCycle)
1 :
Set_Addr_To = aXY;
2 :
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b1110;
end
default :;
endcase
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b1110;
end
end
else
begin
// LD A,(nn)
MCycles = 3'b100;
case (MCycle)
2 :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
4 :
begin
Read_To_Acc = 1'b1;
end
default :;
endcase
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
if (MCycle[2])
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
if (MCycle[3])
begin
Read_To_Acc = 1'b1;
end
end // else: !if(Mode == 3 )
end // case: 8'b00111010
426,18 → 402,15
begin
// LD (BC),A
MCycles = 3'b010;
case (MCycle)
1 :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
2 :
begin
Write = 1'b1;
end
default :;
endcase // case(MCycle)
if (MCycle[0])
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
if (MCycle[1])
begin
Write = 1'b1;
end
end // case: 8'b00000010
8'b00010010 :
444,13 → 417,13
begin
// LD (DE),A
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aDE;
Set_BusB_To = 4'b0111;
end
2 :
MCycle[1] :
Write = 1'b1;
default :;
endcase // case(MCycle)
462,13 → 435,13
begin
// LDD (HL),A
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
2 :
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1110;
481,19 → 454,19
begin
// LD (nn),A
MCycles = 3'b100;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
Set_BusB_To = 4'b0111;
end
4 :
MCycle[3] :
begin
Write = 1'b1;
end
508,8 → 481,8
begin
// LD dd,nn
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
524,7 → 497,7
end
end // case: 2
3 :
MCycle[2] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
549,10 → 522,10
begin
// LDI A,(HL)
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b0110;
565,19 → 538,19
begin
// LD HL,(nn)
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
4 :
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
584,7 → 557,7
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end
5 :
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
600,13 → 573,13
begin
// LDI (HL),A
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
2 :
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b0110;
618,14 → 591,14
begin
// LD (nn),HL
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
633,7 → 606,7
Set_BusB_To = 4'b0101; // L
end
4 :
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
640,7 → 613,7
Write = 1'b1;
Set_BusB_To = 4'b0100; // H
end
5 :
MCycle[4] :
Write = 1'b1;
default :;
endcase
658,8 → 631,8
begin
// PUSH qq
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
676,7 → 649,7
end
end // case: 1
2 :
MCycle[1] :
begin
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
693,7 → 666,7
Write = 1'b1;
end // case: 2
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
703,10 → 676,10
begin
// POP qq
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
2 :
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
722,7 → 695,7
end
end // case: 2
3 :
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Read_To_Reg = 1'b1;
758,14 → 731,14
begin
// LD (nn),SP
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
773,7 → 746,7
Set_BusB_To = 4'b1000;
end
4 :
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
781,7 → 754,7
Set_BusB_To = 4'b1001;
end
5 :
MCycle[4] :
Write = 1'b1;
default :;
endcase
799,10 → 772,10
begin
// RETI
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
2 :
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
809,7 → 782,7
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
832,10 → 805,10
begin
// EX (SP),HL
MCycles = 3'b101;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
2 :
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0101;
842,7 → 815,7
Set_BusB_To = 4'b0101;
Set_Addr_To = aSP;
end
3 :
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
849,7 → 822,7
TStates = 3'b100;
Write = 1'b1;
end
4 :
MCycle[3] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0100;
856,7 → 829,7
Set_BusB_To = 4'b0100;
Set_Addr_To = aSP;
end
5 :
MCycle[4] :
begin
IncDec_16 = 4'b1111;
TStates = 3'b101;
904,10 → 877,10
// XOR A,(HL)
// CP A,(HL)
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
955,10 → 928,10
begin
// INC (HL)
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
970,7 → 943,7
Set_BusA_To[2:0] = DDD;
end // case: 2
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
991,10 → 964,10
begin
// DEC (HL)
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
1006,7 → 979,7
Set_BusA_To[2:0] = DDD;
end // case: 2
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
1040,8 → 1013,8
begin
// NMI
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
1049,7 → 1022,7
Set_BusB_To = 4'b1101;
end
2 :
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
1058,7 → 1031,7
Set_BusB_To = 4'b1100;
end
3 :
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
1072,8 → 1045,8
begin
// INT (IM 2)
MCycles = 3'b101;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
LDZ = 1'b1;
TStates = 3'b101;
1082,7 → 1055,7
Set_BusB_To = 4'b1101;
end
2 :
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
1091,19 → 1064,19
Set_BusB_To = 4'b1100;
end
3 :
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
end
4 :
MCycle[3] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
5 :
MCycle[4] :
Jump = 1'b1;
default :;
endcase
1127,8 → 1100,8
begin
// ADD HL,ss
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0000;
1150,7 → 1123,7
Arith16 = 1'b1;
end // case: 2
3 :
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
1208,21 → 1181,18
begin
// JP nn
MCycles = 3'b011;
case (MCycle)
2 :
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
if (MCycle[2])
begin
Inc_PC = 1'b1;
Jump = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b11000011
8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 :
1234,13 → 1204,13
begin
// LD ($FF00+C),A
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
2 :
MCycle[1] :
begin
Write = 1'b1;
IORQ = 1'b1;
1254,14 → 1224,14
begin
// LD (nn),A
MCycles = 3'b100;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
1268,7 → 1238,7
Set_BusB_To = 4'b0111;
end
4 :
MCycle[3] :
Write = 1'b1;
default :;
endcase // case(MCycle)
1278,10 → 1248,10
begin
// LD A,($FF00+C)
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
2 :
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
1294,18 → 1264,18
begin
// LD A,(nn)
MCycles = 3'b100;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
4 :
MCycle[3] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
1316,13 → 1286,13
begin
// JP cc,nn
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Inc_PC = 1'b1;
if (is_cc_true(F, IR[5:3]) )
1342,10 → 1312,10
begin
// JR e
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
Inc_PC = 1'b1;
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1362,8 → 1332,8
begin
// JR C,e
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
if (F[Flag_C] == 1'b0 )
1372,7 → 1342,7
end
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1389,8 → 1359,8
begin
// JR NC,e
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
if (F[Flag_C] == 1'b1 )
1399,7 → 1369,7
end
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1416,8 → 1386,8
begin
// JR Z,e
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
if (F[Flag_Z] == 1'b0 )
1426,7 → 1396,7
end
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1444,8 → 1414,8
begin
// JR NZ,e
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
if (F[Flag_Z] == 1'b1 )
1453,7 → 1423,7
MCycles = 3'b010;
end
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1478,8 → 1448,8
begin
// DJNZ,e
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
I_DJNZ = 1'b1;
1489,12 → 1459,12
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
2 :
MCycle[1] :
begin
I_DJNZ = 1'b1;
Inc_PC = 1'b1;
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
1511,13 → 1481,13
begin
// CALL nn
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
IncDec_16 = 4'b1111;
Inc_PC = 1'b1;
1526,7 → 1496,7
LDW = 1'b1;
Set_BusB_To = 4'b1101;
end
4 :
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
1533,7 → 1503,7
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
5 :
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
1548,13 → 1518,13
begin
// CALL cc,nn
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Inc_PC = 1'b1;
LDW = 1'b1;
1571,7 → 1541,7
end // else: !if(is_cc_true(F, IR[5:3]) )
end // case: 3
4 :
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
1579,7 → 1549,7
Set_BusB_To = 4'b1100;
end
5 :
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
1594,14 → 1564,14
begin
// RET
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aSP;
end
2 :
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
1608,7 → 1578,7
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
1627,8 → 1597,8
begin
// LD ($FF00+nn),A
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
1635,7 → 1605,7
Set_BusB_To = 4'b0111;
end
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
1645,8 → 1615,8
begin
// ADD SP,n
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
ALU_Op = 4'b0000;
Inc_PC = 1'b1;
1656,7 → 1626,7
Set_BusB_To = 4'b0110;
end
3 :
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
1674,14 → 1644,14
begin
// LD A,($FF00+nn)
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
3 :
MCycle[2] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
1691,14 → 1661,14
begin
// LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
1705,7 → 1675,7
LDW = 1'b1;
end
4 :
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
1713,7 → 1683,7
Set_Addr_To = aZI;
end
5 :
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
1730,8 → 1700,8
begin
// RET cc
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
if (is_cc_true(F, IR[5:3]) )
begin
1744,13 → 1714,13
TStates = 3'b101;
end // case: 1
2 :
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
1764,8 → 1734,8
begin
// RST p
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
1773,7 → 1743,7
Set_BusB_To = 4'b1101;
end
2 :
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
1781,7 → 1751,7
Set_BusB_To = 4'b1100;
end
3 :
MCycle[2] :
begin
Write = 1'b1;
RstP = 1'b1;
1798,14 → 1768,14
begin
// IN A,(n)
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
3 :
MCycle[2] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
1822,8 → 1792,8
begin
// OUT (n),A
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
1830,7 → 1800,7
Set_BusB_To = 4'b0111;
end
3 :
MCycle[2] :
begin
Write = 1'b1;
IORQ = 1'b1;
1925,10 → 1895,10
// SLA (HL)
// SLL (HL) (Undocumented) / SWAP (HL)
MCycles = 3'b011;
case (MCycle)
1 , 7 :
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
1937,7 → 1907,7
TStates = 3'b100;
end
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
1964,10 → 1934,10
begin
// BIT b,(HL)
MCycles = 3'b010;
case (MCycle)
1 , 7 :
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
ALU_Op = 4'b1001;
TStates = 3'b100;
1999,10 → 1969,10
begin
// SET b,(HL)
MCycles = 3'b011;
case (MCycle)
1 , 7 :
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
ALU_Op = 4'b1010;
Read_To_Reg = 1'b1;
2010,7 → 1980,7
Set_Addr_To = aXY;
TStates = 3'b100;
end
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
2038,10 → 2008,10
begin
// RES b,(HL)
MCycles = 3'b011;
case (MCycle)
1 , 7 :
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
2 :
MCycle[1] :
begin
ALU_Op = 4'b1011;
Read_To_Reg = 1'b1;
2050,7 → 2020,7
TStates = 3'b100;
end
3 :
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
2135,14 → 2105,14
begin
// LD dd,(nn)
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
2149,7 → 2119,7
LDW = 1'b1;
end
4 :
MCycle[3] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
2165,7 → 2135,7
Set_Addr_To = aZI;
end // case: 4
5 :
MCycle[4] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
2188,14 → 2158,14
begin
// LD (nn),dd
MCycles = 3'b101;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
2212,7 → 2182,7
end
end // case: 3
4 :
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
2229,7 → 2199,7
end
end // case: 4
5 :
MCycle[4] :
begin
Write = 1'b1;
end
2242,14 → 2212,14
begin
// LDI, LDD, LDIR, LDDR
MCycles = 3'b100;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
2 :
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
2265,7 → 2235,7
end
end // case: 2
3 :
MCycle[2] :
begin
I_BT = 1'b1;
TStates = 3'b101;
2280,7 → 2250,7
end
end // case: 3
4 :
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
2294,14 → 2264,14
begin
// CPI, CPD, CPIR, CPDR
MCycles = 3'b100;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
2 :
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
2318,7 → 2288,7
end
end // case: 2
3 :
MCycle[2] :
begin
NoRead = 1'b1;
I_BC = 1'b1;
2325,7 → 2295,7
TStates = 3'b101;
end
4 :
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
2364,8 → 2334,8
begin
// ADC HL,ss
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0001;
2384,7 → 2354,7
TStates = 3'b100;
end // case: 2
3 :
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
2410,8 → 2380,8
begin
// SBC HL,ss
MCycles = 3'b011;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
2430,7 → 2400,7
TStates = 3'b100;
end // case: 2
3 :
MCycle[2] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
2454,14 → 2424,14
begin
// RLD
MCycles = 3'b100;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
Set_Addr_To = aXY;
end
3 :
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
2472,7 → 2442,7
Save_ALU = 1'b1;
end
4 :
MCycle[3] :
begin
I_RLD = 1'b1;
Write = 1'b1;
2486,10 → 2456,10
begin
// RRD
MCycles = 3'b100;
case (MCycle)
2 :
case (1'b1) // MCycle
MCycle[1] :
Set_Addr_To = aXY;
3 :
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
2500,7 → 2470,7
Save_ALU = 1'b1;
end
4 :
MCycle[3] :
begin
I_RRD = 1'b1;
Write = 1'b1;
2514,11 → 2484,11
begin
// RETI, RETN
MCycles = 3'b011;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
2 :
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
2525,7 → 2495,7
LDZ = 1'b1;
end
3 :
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
2540,11 → 2510,11
begin
// IN r,(C)
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
2 :
MCycle[1] :
begin
IORQ = 1'b1;
if (IR[5:3] != 3'b110 )
2564,8 → 2534,8
// OUT (C),r
// OUT (C),0
MCycles = 3'b010;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To[2:0] = IR[5:3];
2575,7 → 2545,7
end
end
2 :
MCycle[1] :
begin
Write = 1'b1;
IORQ = 1'b1;
2589,8 → 2559,8
begin
// INI, IND, INIR, INDR
MCycles = 3'b100;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b1010;
2600,7 → 2570,7
ALU_Op = 4'b0010;
end
2 :
MCycle[1] :
begin
IORQ = 1'b1;
Set_BusB_To = 4'b0110;
2607,7 → 2577,7
Set_Addr_To = aXY;
end
3 :
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
2622,7 → 2592,7
I_BTR = 1'b1;
end // case: 3
4 :
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
2636,8 → 2606,8
begin
// OUTI, OUTD, OTIR, OTDR
MCycles = 3'b100;
case (MCycle)
1 :
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aXY;
2648,13 → 2618,13
ALU_Op = 4'b0010;
end
2 :
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_Addr_To = aBC;
end
3 :
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
2669,7 → 2639,7
I_BTR = 1'b1;
end // case: 3
4 :
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
2751,7 → 2721,7
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.2 2004-09-21 17:32:52 ghutchis Exp $" -type string -quiet
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.3 2004-09-22 18:07:14 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule // T80_MCode
 

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