URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 220 to Rev 221
- ↔ Reverse comparison
Rev 220 → Rev 221
/open8_urisc/trunk/VHDL/o8_register.vhd
81,7 → 81,7
begin |
if( Reset = Reset_Level )then |
Wr_En <= '0'; |
Wr_Data_q <= (others => '0'); |
Wr_Data_q <= x"00"; |
Reg_Out <= Default_Value; |
Rd_En <= '0'; |
Rd_Data <= OPEN8_NULLBUS; |
97,7 → 97,6
if( Rd_En = '1' )then |
Rd_Data <= Reg_Out; |
end if; |
|
end if; |
end process; |
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/open8_urisc/trunk/VHDL/o8_vdsm8.vhd
24,6 → 24,10
-- VHDL Units : o8_vdsm8 |
-- Description: 8-bit variable delta-sigma modulator. |
-- |
-- Register Map: |
-- Offset Bitfield Description Read/Write |
-- 0x00 AAAAAAAA DAC Value (RW) |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
40,6 → 44,7
|
entity o8_vdsm8 is |
generic( |
Default_Value : DATA_TYPE := x"00"; |
Reset_Level : std_logic; |
Address : ADDRESS_TYPE |
); |
59,15 → 64,15
|
architecture behave of o8_vdsm8 is |
|
constant User_Addr : std_logic_vector(15 downto 0) := Address; |
constant User_Addr : std_logic_vector(15 downto 0) |
:= Address(15 downto 0); |
alias Comp_Addr is Bus_Address(15 downto 0); |
signal Addr_Match : std_logic := '0'; |
signal Wr_En : std_logic := '0'; |
signal Wr_Data_q : DATA_TYPE := x"00"; |
signal Rd_En : std_logic := '0'; |
signal DACin : DATA_TYPE := x"00"; |
signal Addr_Match : std_logic; |
signal Wr_En : std_logic; |
signal Wr_Data_q : DATA_TYPE; |
signal Reg_Out : DATA_TYPE; |
signal Rd_En : std_logic; |
|
|
begin |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
77,20 → 82,20
if( Reset = Reset_Level )then |
Wr_En <= '0'; |
Wr_Data_q <= x"00"; |
Reg_Out <= Default_Value; |
Rd_En <= '0'; |
Rd_Data <= OPEN8_NULLBUS; |
DACin <= x"00"; |
elsif( rising_edge( Clock ) )then |
Wr_En <= Addr_Match and Wr_Enable; |
Wr_Data_q <= Wr_Data; |
if( Wr_En = '1' )then |
DACin <= Wr_Data_q; |
Reg_Out <= Wr_Data_q; |
end if; |
|
Rd_Data <= OPEN8_NULLBUS; |
Rd_En <= Addr_Match and Rd_Enable; |
if( Rd_En = '1' )then |
Rd_Data <= DACin; |
Rd_Data <= Reg_Out; |
end if; |
end if; |
end process; |
102,7 → 107,7
port map( |
Clock => Clock, |
Reset => Reset, |
DACin => DACin, |
DACin => Reg_Out, |
DACout => DACout |
); |
|