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https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- from Rev 221 to Rev 222
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Rev 221 → Rev 222
/trunk/rtl/vhdl/dmem_ctrl.vhd
3,7 → 3,7
-- The Data Memory control unit. |
-- All accesses to the Data Memory are managed here. |
-- |
-- $Id: dmem_ctrl.vhd,v 1.4 2005-06-11 10:08:43 arniml Exp $ |
-- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
154,10 → 154,12
-- |
-- Purpose: |
-- Implements the Data Memory Address Register. |
-- This register is necessary to hold the address during a write operation |
-- This register is required to hold the address during a write operation |
-- as we cannot hold the address in the input register of the |
-- synchronous RAM (no clock suppression/gating). |
-- |
-- NOTE: May be obsoleted by clock enable feature of generic RTL RAM. |
-- |
dmem_addr_reg: process (res_i, clk_i) |
begin |
if res_i = res_active_c then |
204,6 → 206,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.4 2005/06/11 10:08:43 arniml |
-- introduce prefix 't48_' for all packages, entities and configurations |
-- |
-- Revision 1.3 2004/04/24 23:44:25 arniml |
-- move from std_logic_arith to numeric_std |
-- |