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Subversion Repositories t48
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- from Rev 223 to Rev 224
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Rev 223 → Rev 224
/trunk/bench/vhdl/t48_rom-lpm-a.vhd
0,0 → 1,101
------------------------------------------------------------------------------- |
-- |
-- T8x48 ROM |
-- Wrapper for ROM model from the LPM library. |
-- |
-- $Id: t48_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
architecture lpm of t48_rom is |
|
component lpm_rom |
generic ( |
LPM_WIDTH : positive; |
LPM_TYPE : string := "LPM_ROM"; |
LPM_WIDTHAD : positive; |
LPM_NUMWORDS : natural := 0; |
LPM_FILE : string; |
LPM_ADDRESS_CONTROL : string := "REGISTERED"; |
LPM_OUTDATA : string := "REGISTERED"; |
LPM_HINT : string := "UNUSED" |
); |
port ( |
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); |
inclock : in std_logic; |
outclock : in std_logic; |
memenab : in std_logic; |
q : out std_logic_vector(LPM_WIDTH-1 downto 0) |
); |
end component; |
|
signal vdd_s : std_logic; |
|
begin |
|
vdd_s <= '1'; |
|
rom_b : lpm_rom |
generic map ( |
LPM_WIDTH => 8, |
LPM_TYPE => "LPM_ROM", |
LPM_WIDTHAD => 10, |
LPM_NUMWORDS => 2 ** 10, |
LPM_FILE => "rom_t48.hex", |
LPM_ADDRESS_CONTROL => "REGISTERED", |
LPM_OUTDATA => "UNREGISTERED", |
LPM_HINT => "UNUSED" |
) |
port map ( |
address => rom_addr_i, |
inclock => clk_i, |
outclock => clk_i, |
memenab => vdd_s, |
q => rom_data_o |
); |
|
end lpm; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/bench/vhdl/t49_rom-lpm-a.vhd
0,0 → 1,101
------------------------------------------------------------------------------- |
-- |
-- T8x49 ROM |
-- Wrapper for ROM model from the LPM library. |
-- |
-- $Id: t49_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
architecture lpm of t49_rom is |
|
component lpm_rom |
generic ( |
LPM_WIDTH : positive; |
LPM_TYPE : string := "LPM_ROM"; |
LPM_WIDTHAD : positive; |
LPM_NUMWORDS : natural := 0; |
LPM_FILE : string; |
LPM_ADDRESS_CONTROL : string := "REGISTERED"; |
LPM_OUTDATA : string := "REGISTERED"; |
LPM_HINT : string := "UNUSED" |
); |
port ( |
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); |
inclock : in std_logic; |
outclock : in std_logic; |
memenab : in std_logic; |
q : out std_logic_vector(LPM_WIDTH-1 downto 0) |
); |
end component; |
|
signal vdd_s : std_logic; |
|
begin |
|
vdd_s <= '1'; |
|
rom_b : lpm_rom |
generic map ( |
LPM_WIDTH => 8, |
LPM_TYPE => "LPM_ROM", |
LPM_WIDTHAD => 11, |
LPM_NUMWORDS => 2 ** 11, |
LPM_FILE => "rom_t49.hex", |
LPM_ADDRESS_CONTROL => "REGISTERED", |
LPM_OUTDATA => "UNREGISTERED", |
LPM_HINT => "UNUSED" |
) |
port map ( |
address => rom_addr_i, |
inclock => clk_i, |
outclock => clk_i, |
memenab => vdd_s, |
q => rom_data_o |
); |
|
end lpm; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/bench/vhdl/t48_rom-lpm-c.vhd
0,0 → 1,31
------------------------------------------------------------------------------- |
-- |
-- T8x48 ROM |
-- Wrapper for ROM model from the LPM library. |
-- |
-- $Id: t48_rom-lpm-c.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration t48_rom_lpm_c0 of t48_rom is |
|
for lpm |
|
for rom_b: lpm_rom |
use configuration work.lpm_rom_c0; |
end for; |
|
end for; |
|
end t48_rom_lpm_c0; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/bench/vhdl/t49_rom-lpm-c.vhd
0,0 → 1,31
------------------------------------------------------------------------------- |
-- |
-- T8x49 ROM |
-- Wrapper for ROM model from the LPM library. |
-- |
-- $Id: t49_rom-lpm-c.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration t49_rom_lpm_c0 of t49_rom is |
|
for lpm |
|
for rom_b: lpm_rom |
use configuration work.lpm_rom_c0; |
end for; |
|
end for; |
|
end t49_rom_lpm_c0; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/t48_rom-e.vhd
0,0 → 1,64
------------------------------------------------------------------------------- |
-- |
-- T8x48 ROM |
-- |
-- $Id: t48_rom-e.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity t48_rom is |
|
port ( |
clk_i : in std_logic; |
rom_addr_i : in std_logic_vector(9 downto 0); |
rom_data_o : out std_logic_vector(7 downto 0) |
); |
|
end t48_rom; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/generic_ram_ena-c.vhd
0,0 → 1,18
------------------------------------------------------------------------------- |
-- |
-- Parametrizable, generic RAM with enable. |
-- |
-- $Id: generic_ram_ena-c.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration generic_ram_ena_rtl_c0 of generic_ram_ena is |
|
for rtl |
end for; |
|
end generic_ram_ena_rtl_c0; |
/trunk/rtl/vhdl/system/t49_rom-e.vhd
0,0 → 1,64
------------------------------------------------------------------------------- |
-- |
-- T8x49 ROM |
-- |
-- $Id: t49_rom-e.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity t49_rom is |
|
port ( |
clk_i : in std_logic; |
rom_addr_i : in std_logic_vector(10 downto 0); |
rom_data_o : out std_logic_vector( 7 downto 0) |
); |
|
end t49_rom; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/t48_rom-struct-a.vhd
0,0 → 1,72
------------------------------------------------------------------------------- |
-- |
-- T8x48 ROM |
-- |
-- $Id: t48_rom-struct-a.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
architecture struct of t48_rom is |
|
component rom_t48x |
port( |
Clk : in std_logic; |
A : in std_logic_vector(9 downto 0); |
D : out std_logic_vector(7 downto 0) |
); |
end component; |
|
begin |
|
rom_b : rom_t48 |
port map ( |
Clk => ck_i, |
A => addr_i, |
D => data_o |
); |
|
end struct; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/t49_rom-struct-a.vhd
0,0 → 1,72
------------------------------------------------------------------------------- |
-- |
-- T8x49 ROM |
-- |
-- $Id: t49_rom-struct-a.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
architecture struct of t49_rom is |
|
component rom_t49x |
port( |
Clk : in std_logic; |
A : in std_logic_vector(10 downto 0); |
D : out std_logic_vector( 7 downto 0) |
); |
end component; |
|
begin |
|
rom_b : rom_t49 |
port map ( |
Clk => ck_i, |
A => addr_i, |
D => data_o |
); |
|
end struct; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/generic_ram_ena.vhd
0,0 → 1,100
------------------------------------------------------------------------------- |
-- |
-- Parametrizable, generic RAM with enable. |
-- |
-- $Id: generic_ram_ena.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $ |
-- |
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity generic_ram_ena is |
|
generic ( |
addr_width_g : integer := 10; |
data_width_g : integer := 8 |
); |
port ( |
clk_i : in std_logic; |
a_i : in std_logic_vector(addr_width_g-1 downto 0); |
we_i : in std_logic; |
ena_i : in std_logic; |
d_i : in std_logic_vector(data_width_g-1 downto 0); |
d_o : out std_logic_vector(data_width_g-1 downto 0) |
); |
|
end generic_ram_ena; |
|
|
library ieee; |
use ieee.numeric_std.all; |
|
architecture rtl of generic_ram_ena is |
|
type mem_t is array (natural range 0 to 2**addr_width_g-1) of |
std_logic_vector(d_i'range); |
signal mem_q : mem_t |
-- pragma translate_off |
:= (others => (others => '0')) |
-- pragma translate_on |
; |
signal a_q : std_logic_vector(a_i'range); |
|
begin |
|
mem: process (clk_i) |
begin |
|
if clk_i'event and clk_i = '1' then |
if ena_i = '1' then |
if we_i = '1' then |
mem_q(to_integer(unsigned(a_i))) <= d_i; |
end if; |
|
a_q <= a_i; |
end if; |
|
end if; |
end process mem; |
|
d_o <= mem_q(to_integer(unsigned(a_q))); |
|
end rtl; |