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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev 224 → Rev 225

/t6507lp/trunk/rtl/verilog/vga_controller.v
44,12 → 44,13
 
`include "timescale.v"
 
module vga_controller ( reset, clk_50, line, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
module vga_controller ( reset, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
 
input reset;
input clk_50;
input [8:0] SW;
input [479:0] line;
input [479:0] line;
input [4:0] vert_counter;
output reg [3:0] VGA_R;
output reg [3:0] VGA_G;
output reg [3:0] VGA_B;
57,7 → 58,6
output reg VGA_VS;
output reg VGA_HS;
 
 
reg clk_25;
reg [9:0] hc;
reg [9:0] vc;
64,7 → 64,8
reg vsenable;
wire vidon;
 
assign LEDR = SW;
assign LEDR[8:0] = SW;
assign LEDR[9] = reset;
 
always @ (posedge clk_50 or negedge reset)
begin
142,11 → 143,67
always @ (posedge clk_25)
begin
if (vidon == 1) begin
if (hc < 320) begin
if (vc < 240) begin
if (hc < 40) begin
if (vert_counter < 10) begin
/*VGA_R[0] <= line[hc*12];
VGA_R[1] <= line[hc*12+1];
VGA_R[2] <= line[hc*12+2];
VGA_R[3] <= line[hc*12+3];
VGA_G[0] <= line[hc*12+4];
VGA_G[1] <= line[hc*12+5];
VGA_G[2] <= line[hc*12+6];
VGA_G[3] <= line[hc*12+7];
VGA_B[0] <= line[hc*12+8];
VGA_B[1] <= line[hc*12+9];
VGA_B[2] <= line[hc*12+10];
VGA_B[3] <= line[hc*12+11];*/
VGA_R[0] <= 1;
VGA_R[1] <= 0;
VGA_R[2] <= 1;
VGA_R[3] <= 0;
VGA_G[0] <= 1;
VGA_G[1] <= 0;
VGA_G[2] <= 1;
VGA_G[3] <= 0;
VGA_B[0] <= 1;
VGA_B[1] <= 0;
VGA_B[2] <= 1;
VGA_B[3] <= 0;
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
/* if (vc < 240) begin
VGA_R[0] <= 1;
VGA_G[0] <= 1;
VGA_B[0] <= 1;
VGA_R[1] <= 1;
VGA_G[1] <= 1;
VGA_B[1] <= 1;
203,6 → 260,8
end
end
end
*/
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
217,6 → 276,7
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
/t6507lp/trunk/rtl/verilog/controller_test.v
45,16 → 45,16
`include "timescale.v"
 
//module vga_tester (reset_n, clk_50);
module controller_test(line, vert_counter);
module controller_test(reset, clk_50, line, vert_counter);
 
//input reset_n;
//input clk_50;
input reset;
input clk_50;
 
output reg [479:0] line;
output reg [4:0] vert_counter;
 
reg reset_n;
reg clk_50;
//reg reset_n;
//reg clk_50;
 
reg clk_358; // 3.58mhz
reg [3:0] counter;
73,17 → 73,18
reg [11:0] pixel7;
reg [11:0] pixel8;
reg [11:0] pixel9;
always #10 clk_50 <= !clk_50;
 
//always #10 clk_50 <= !clk_50;
 
initial begin
reset_n = 1'b0;
clk_50 = 1'b0;
#20;
reset_n = 1'b1;
end
//initial begin
//reset_n = 1'b0;
//clk_50 = 1'b0;
//#20;
//reset_n = 1'b1;
//end
 
always @ (posedge clk_50 or negedge reset_n) begin
if (reset_n == 0) begin
always @ (posedge clk_50 or negedge reset) begin
if (reset == 0) begin
clk_358 <= 1'b0;
counter <= 4'd0;
red <= 4'b1010;
96,16 → 97,19
counter <= 4'd0;
end
else begin
counter <= counter + 4'd1;
counter <= counter + 4'd1;
end
end
end
red <= 4'b1010;
green <= 4'b0001;
blue <= 4'b1110;
end
 
 
 
always @ (posedge clk_358 or negedge reset_n) begin
if (reset_n == 0) begin
vert_counter <= 6'd0;
always @ (posedge clk_358 or negedge reset) begin
if (reset == 0) begin
vert_counter <= 5'd0;
line <= 480'd0;
end
else begin
116,7 → 120,7
pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9};
 
if (vert_counter == 5'd29) begin
vert_counter <= 6'd0;
vert_counter <= 5'd0;
end
else begin
vert_counter <= vert_counter + 5'd1;
/t6507lp/trunk/rtl/verilog/test_top.v
56,13 → 56,14
output VGA_VS;
output VGA_HS;
 
wire [479:0] line;
wire [4:0] vert_counter;
//wire [479:0] line;
//wire [4:0] vert_counter;
 
vga_controller vga_controller (
.reset(reset),
.clk_50(clk_50),
.line(line),
.line(line),
.vert_counter(vert_counter),
.SW(SW),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
72,7 → 73,9
.VGA_HS(VGA_HS)
);
 
controller_test controller_test (
controller_test controller_test (
.reset(reset),
.clk_50(clk_50),
.line(line),
.vert_counter(vert_counter)
);

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