URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 227 to Rev 228
- ↔ Reverse comparison
Rev 227 → Rev 228
/trunk/bench/vhdl/tb-c.vhd
2,7 → 2,7
-- |
-- The testbench for t48_core. |
-- |
-- $Id: tb-c.vhd,v 1.3 2004-05-21 11:22:44 arniml Exp $ |
-- $Id: tb-c.vhd,v 1.4 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
22,12 → 22,12
use configuration work.lpm_rom_c0; |
end for; |
|
for ram_256 : syn_ram |
use configuration work.syn_ram_lpm_c0; |
for ram_256 : generic_ram_ena |
use configuration work.generic_ram_ena_rtl_c0; |
end for; |
|
for ext_ram_b : syn_ram |
use configuration work.syn_ram_lpm_c0; |
for ext_ram_b : generic_ram_ena |
use configuration work.generic_ram_ena_rtl_c0; |
end for; |
|
for t48_core_b : t48_core |
47,6 → 47,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2004/05/21 11:22:44 arniml |
-- exchange syn_rom for lpm_rom |
-- |
-- Revision 1.2 2004/04/25 16:23:21 arniml |
-- added if_timing |
-- |
/trunk/bench/vhdl/tb.vhd
2,7 → 2,7
-- |
-- The testbench for t48_core. |
-- |
-- $Id: tb.vhd,v 1.13 2006-06-20 00:45:26 arniml Exp $ |
-- $Id: tb.vhd,v 1.14 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
148,7 → 148,7
|
----------------------------------------------------------------------------- |
-- Internal ROM, 2k bytes |
-- Initialized by file t48_rom.hex. |
-- Initialized by file rom_t49.hex. |
----------------------------------------------------------------------------- |
rom_internal_2k : lpm_rom |
generic map ( |
156,7 → 156,7
LPM_TYPE => "LPM_ROM", |
LPM_WIDTHAD => 11, |
LPM_NUMWORDS => 2 ** 11, |
LPM_FILE => "t48_rom.hex", |
LPM_FILE => "rom_t49.hex", |
LPM_ADDRESS_CONTROL => "REGISTERED", |
LPM_OUTDATA => "UNREGISTERED", |
LPM_HINT => "UNUSED" |
171,7 → 171,7
|
----------------------------------------------------------------------------- |
-- External ROM, 2k bytes |
-- Initialized by file t48_ext_rom.hex. |
-- Initialized by file rom_t49_ext.hex. |
----------------------------------------------------------------------------- |
ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0); |
ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q; |
181,7 → 181,7
LPM_TYPE => "LPM_ROM", |
LPM_WIDTHAD => 11, |
LPM_NUMWORDS => 2 ** 11, |
LPM_FILE => "t48_ext_rom.hex", |
LPM_FILE => "rom_t49_ext.hex", |
LPM_ADDRESS_CONTROL => "REGISTERED", |
LPM_OUTDATA => "UNREGISTERED", |
LPM_HINT => "UNUSED" |
197,33 → 197,35
----------------------------------------------------------------------------- |
-- Internal RAM, 256 bytes |
----------------------------------------------------------------------------- |
ram_256 : syn_ram |
ram_256 : generic_ram_ena |
generic map ( |
address_width_g => 8 |
addr_width_g => 8, |
data_width_g => 8 |
) |
port map ( |
clk_i => xtal_s, |
res_i => res_n_s, |
ram_addr_i => ram_addr_s, |
ram_data_i => ram_data_to_s, |
ram_we_i => ram_we_s, |
ram_data_o => ram_data_from_s |
clk_i => xtal_s, |
a_i => ram_addr_s, |
we_i => ram_we_s, |
ena_i => one_s, |
d_i => ram_data_to_s, |
d_o => ram_data_from_s |
); |
|
----------------------------------------------------------------------------- |
-- External RAM, 256 bytes |
----------------------------------------------------------------------------- |
ext_ram_b : syn_ram |
ext_ram_b : generic_ram_ena |
generic map ( |
address_width_g => 8 |
addr_width_g => 8, |
data_width_g => 8 |
) |
port map ( |
clk_i => xtal_s, |
res_i => res_n_s, |
ram_addr_i => ext_mem_addr_q, |
ram_data_i => bus_s, |
ram_we_i => ext_ram_we_q, |
ram_data_o => ext_ram_data_from_s |
clk_i => xtal_s, |
a_i => ext_mem_addr_q, |
we_i => ext_ram_we_q, |
ena_i => one_s, |
d_i => bus_s, |
d_o => ext_ram_data_from_s |
); |
|
t48_core_b : t48_core |
563,6 → 565,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.13 2006/06/20 00:45:26 arniml |
-- new input xtal_en_i |
-- |
-- Revision 1.12 2005/11/01 21:21:48 arniml |
-- split low impedance markers for P2 |
-- |
/trunk/bench/vhdl/tb_t8039-c.vhd
2,7 → 2,7
-- |
-- The testbench for t8039. |
-- |
-- $Id: tb_t8039-c.vhd,v 1.1 2004-04-18 19:00:07 arniml Exp $ |
-- $Id: tb_t8039-c.vhd,v 1.2 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
14,12 → 14,12
|
for behav |
|
for ext_ram_b : syn_ram |
use configuration work.syn_ram_lpm_c0; |
for ext_ram_b : generic_ram_ena |
use configuration work.generic_ram_ena_rtl_c0; |
end for; |
|
for ext_rom_b : syn_rom |
use configuration work.syn_rom_lpm_c0; |
for ext_rom_b : lpm_rom |
use configuration work.lpm_rom_c0; |
end for; |
|
for t8039_b : t8039 |
35,4 → 35,7
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2004/04/18 19:00:07 arniml |
-- initial check-in |
-- |
------------------------------------------------------------------------------- |
/trunk/bench/vhdl/tb_t8039.vhd
2,7 → 2,7
-- |
-- The testbench for t8039. |
-- |
-- $Id: tb_t8039.vhd,v 1.2 2005-11-01 21:22:28 arniml Exp $ |
-- $Id: tb_t8039.vhd,v 1.3 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
50,8 → 50,8
|
end tb_t8039; |
|
use work.t48_core_comp_pack.syn_ram; |
use work.t48_core_comp_pack.syn_rom; |
use work.t48_core_comp_pack.generic_ram_ena; |
use work.t48_system_comp_pack.t8039; |
|
use work.t48_tb_pack.all; |
|
60,22 → 60,23
-- clock period, 11 MHz |
constant period_c : time := 90 ns; |
|
component t8039 |
component lpm_rom |
generic ( |
LPM_WIDTH : positive; |
LPM_TYPE : string := "LPM_ROM"; |
LPM_WIDTHAD : positive; |
LPM_NUMWORDS : natural := 0; |
LPM_FILE : string; |
LPM_ADDRESS_CONTROL : string := "REGISTERED"; |
LPM_OUTDATA : string := "REGISTERED"; |
LPM_HINT : string := "UNUSED" |
); |
port ( |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_b : inout std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
db_b : inout std_logic_vector( 7 downto 0); |
t1_i : in std_logic; |
p2_b : inout std_logic_vector( 7 downto 0); |
p1_b : inout std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic |
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); |
inclock : in std_logic; |
outclock : in std_logic; |
memenab : in std_logic; |
q : out std_logic_vector(LPM_WIDTH-1 downto 0) |
); |
end component; |
|
114,27 → 115,41
p2_b <= (others => 'H'); |
p1_b <= (others => 'H'); |
|
ext_rom_b : syn_rom |
----------------------------------------------------------------------------- |
-- External ROM, 4k bytes |
-- Initialized by file t3x_ext_rom.hex. |
----------------------------------------------------------------------------- |
ext_rom_b : lpm_rom |
generic map ( |
address_width_g => 12 |
LPM_WIDTH => 8, |
LPM_TYPE => "LPM_ROM", |
LPM_WIDTHAD => 12, |
LPM_NUMWORDS => 2 ** 12, |
LPM_FILE => "rom_t3x_ext.hex", |
LPM_ADDRESS_CONTROL => "REGISTERED", |
LPM_OUTDATA => "UNREGISTERED", |
LPM_HINT => "UNUSED" |
) |
port map ( |
clk_i => xtal_s, |
rom_addr_i => ext_mem_addr_s, |
rom_data_o => ext_rom_data_s |
address => ext_mem_addr_s, |
inclock => xtal_s, |
outclock => zero_s, -- unused |
memenab => one_s, |
q => ext_rom_data_s |
); |
|
ext_ram_b : syn_ram |
ext_ram_b : generic_ram_ena |
generic map ( |
address_width_g => 8 |
addr_width_g => 8, |
data_width_g => 8 |
) |
port map ( |
clk_i => zero_s, |
res_i => res_n_s, |
ram_addr_i => ext_mem_addr_s(7 downto 0), |
ram_data_i => db_b, |
ram_we_i => ext_ram_we_s, |
ram_data_o => ext_ram_data_from_s |
clk_i => xtal_s, |
a_i => ext_mem_addr_s(7 downto 0), |
we_i => ext_ram_we_s, |
ena_i => one_s, |
d_i => db_b, |
d_o => ext_ram_data_from_s |
); |
|
t8039_b : t8039 |
286,6 → 301,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/11/01 21:22:28 arniml |
-- fix address assignment |
-- |
-- Revision 1.1 2004/04/18 19:00:07 arniml |
-- initial check-in |
-- |
/trunk/bench/vhdl/tb_t8048-c.vhd
2,7 → 2,7
-- |
-- The testbench for t8048. |
-- |
-- $Id: tb_t8048-c.vhd,v 1.1 2004-03-24 21:42:10 arniml Exp $ |
-- $Id: tb_t8048-c.vhd,v 1.2 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
14,8 → 14,8
|
for behav |
|
for ext_ram_b : syn_ram |
use configuration work.syn_ram_lpm_c0; |
for ext_ram_b : generic_ram_ena |
use configuration work.generic_ram_ena_rtl_c0; |
end for; |
|
for t8048_b : t8048 |
31,4 → 31,7
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2004/03/24 21:42:10 arniml |
-- initial check-in |
-- |
------------------------------------------------------------------------------- |
/trunk/bench/vhdl/tb_t8048.vhd
2,7 → 2,7
-- |
-- The testbench for t8048. |
-- |
-- $Id: tb_t8048.vhd,v 1.4 2004-04-18 19:00:58 arniml Exp $ |
-- $Id: tb_t8048.vhd,v 1.5 2006-06-21 01:04:05 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
50,7 → 50,7
|
end tb_t8048; |
|
use work.t48_core_comp_pack.syn_ram; |
use work.t48_core_comp_pack.generic_ram_ena; |
|
use work.t48_tb_pack.all; |
|
112,17 → 112,18
p2_b <= (others => 'H'); |
p1_b <= (others => 'H'); |
|
ext_ram_b : syn_ram |
ext_ram_b : generic_ram_ena |
generic map ( |
address_width_g => 8 |
addr_width_g => 8, |
data_width_g => 8 |
) |
port map ( |
clk_i => zero_s, |
res_i => res_n_s, |
ram_addr_i => ext_ram_addr_s, |
ram_data_i => db_b, |
ram_we_i => ext_ram_we_s, |
ram_data_o => ext_ram_data_from_s |
clk_i => zero_s, |
a_i => ext_ram_addr_s, |
we_i => ext_ram_we_s, |
ena_i => one_s, |
d_i => db_b, |
d_o => ext_ram_data_from_s |
); |
|
t8048_b : t8048 |
259,6 → 260,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.4 2004/04/18 19:00:58 arniml |
-- connect T0 and T1 to P1 |
-- |
-- Revision 1.3 2004/04/14 20:57:44 arniml |
-- wait for instruction strobe after final end-of-simulation detection |
-- this ensures that the last mov instruction is part of the dump and |