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    from Rev 228 to Rev 229
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Rev 228 → Rev 229

/raytrac/branches/fp_sgdma/arithblock.vhd
33,16 → 33,46
sign : in std_logic;
prd32blki : in vectorblock12;
add32blki : in vectorblock06;
factor0 : in std_logic_vector(31 downto 0);
factor1 : in std_logic_vector(31 downto 0);
factor2 : in std_logic_vector(31 downto 0);
factor3 : in std_logic_vector(31 downto 0);
factor4 : in std_logic_vector(31 downto 0);
factor5 : in std_logic_vector(31 downto 0);
factor6 : in std_logic_vector(31 downto 0);
factor7 : in std_logic_vector(31 downto 0);
factor8 : in std_logic_vector(31 downto 0);
factor9 : in std_logic_vector(31 downto 0);
factor10 : in std_logic_vector(31 downto 0);
factor11 : in std_logic_vector(31 downto 0);
--factor : in vectorblock06;
sumando0 : in std_logic_vector(31 downto 0);
sumando1 : in std_logic_vector(31 downto 0);
sumando2 : in std_logic_vector(31 downto 0);
sumando3 : in std_logic_vector(31 downto 0);
sumando4 : in std_logic_vector(31 downto 0);
sumando5 : in std_logic_vector(31 downto 0);
--add32blki : in vectorblock06;
add32blko : out vectorblock03;
prd32blko : out vectorblock06;
a0 : out std_logic_vector(31 downto 0);
a1 : out std_logic_vector(31 downto 0);
a2 : out std_logic_vector(31 downto 0);
a3 : out std_logic_vector(31 downto 0);
--add32blko : out vectorblock03;
sq32o : out xfloat32;
inv32o : out xfloat32
p0 : out std_logic_vector(31 downto 0);
p1 : out std_logic_vector(31 downto 0);
p2 : out std_logic_vector(31 downto 0);
p3 : out std_logic_vector(31 downto 0);
p4 : out std_logic_vector(31 downto 0);
p5 : out std_logic_vector(31 downto 0);
--p : out vectorblock06;
sq32o : out std_logic_vector(31 downto 0);
inv32o : out std_logic_vector(31 downto 0)
);
end entity;
49,8 → 79,8
 
architecture arithblock_arch of arithblock is
 
signal sadd32blko_01 : xfloat32;
signal ssq32o : xfloat32;
signal sadd32blko_01 : std_logic_vector(31 downto 0);
signal ssq32o : std_logic_vector(31 downto 0);
--! Componentes Aritméticos
component fadd32long
57,17 → 87,17
port (
clk : in std_logic;
dpc : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
c32 : out xfloat32
a32 : in std_logic_vector(31 downto 0);
b32 : in std_logic_vector(31 downto 0);
c32 : out std_logic_vector(31 downto 0)
);
end component;
component fmul32
port (
clk : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
p32 : out xfloat32
a32 : in std_logic_vector(31 downto 0);
b32 : in std_logic_vector(31 downto 0);
p32 : out std_logic_vector(31 downto 0)
);
end component;
--! Bloque de Raiz Cuadrada
75,8 → 105,8
port (
clk : in std_logic;
rd32: in xfloat32;
sq32: out xfloat32
rd32: in std_logic_vector(31 downto 0);
sq32: out std_logic_vector(31 downto 0)
);
end component;
--! Bloque de Inversores.
84,8 → 114,8
port (
clk : in std_logic;
dvd32 : in xfloat32;
qout32 : out xfloat32
dvd32 : in std_logic_vector(31 downto 0);
qout32 : out std_logic_vector(31 downto 0)
);
end component;
 
93,7 → 123,7
begin
 
sq32o <= ssq32o;
add32blko(1) <= sadd32blko_01;
a1 <= sadd32blko_01;
 
--!TBXINSTANCESTART
adder_i_0 : fadd32long
100,9 → 130,9
port map (
clk => clk,
dpc => sign,
a32 => add32blki(0),
b32 => add32blki(1),
c32 => add32blko(0)
a32 => sumando0,
b32 => sumando1,
c32 => a0
);
--!TBXINSTANCESTART
adder_i_1 : fadd32long
109,8 → 139,8
port map (
clk => clk,
dpc => sign,
a32 => add32blki(2),
b32 => add32blki(3),
a32 => sumando2,
b32 => sumando3,
c32 => sadd32blko_01
);
--!TBXINSTANCESTART
118,57 → 148,65
port map (
clk => clk,
dpc => sign,
a32 => add32blki(4),
b32 => add32blki(5),
c32 => add32blko(2)
a32 => sumando4,
b32 => sumando5,
c32 => a2
);
adder_i_3 : fadd32long
port map (
clk => clk,
dpc => sign,
a32 => sumando4,
b32 => sumando5,
c32 => a3
);
--!TBXINSTANCESTART
mul_i_0 : fmul32
port map (
clk => clk,
a32 => prd32blki(0),
b32 => prd32blki(1),
p32 => prd32blko(0)
a32 => factor0,
b32 => factor1,
p32 => p0
);
--!TBXINSTANCESTART
mul_i_1 : fmul32
port map (
clk => clk,
a32 => prd32blki(2),
b32 => prd32blki(3),
p32 => prd32blko(1)
a32 => factor2,
b32 => factor3,
p32 => p1
);
--!TBXINSTANCESTART
mul_i_2 : fmul32
port map (
clk => clk,
a32 => prd32blki(4),
b32 => prd32blki(5),
p32 => prd32blko(2)
a32 => factor4,
b32 => factor5,
p32 => p2
);
--!TBXINSTANCESTART
mul_i_3 : fmul32
port map (
clk => clk,
a32 => prd32blki(6),
b32 => prd32blki(7),
p32 => prd32blko(3)
a32 => factor6,
b32 => factor7,
p32 => p3
);
--!TBXINSTANCESTART
mul_i_4 : fmul32
port map (
clk => clk,
a32 => prd32blki(8),
b32 => prd32blki(9),
p32 => prd32blko(4)
a32 => factor8,
b32 => factor9,
p32 => p4
);
--!TBXINSTANCESTART
mul_i_5 : fmul32
port map (
clk => clk,
a32 => prd32blki(10),
b32 => prd32blki(11),
p32 => prd32blko(5)
a32 => factor10,
b32 => factor11,
p32 => p5
);
--!TBXINSTANCESTART
square_root : sqrt32
/raytrac/branches/fp_sgdma/ap_n_dpc.vhd
32,21 → 32,41
entity ap_n_dpc is
port (
sumando5 : out std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
paraminput : in vectorblock06; --! Vectores A,B
dx : out std_logic_vector(31 downto 0);
dy : out std_logic_vector(31 downto 0);
dz : out std_logic_vector(31 downto 0);
dsc : out std_logic_vector(31 downto 0);
ax : in std_logic_vector(31 downto 0);
ay : in std_logic_vector(31 downto 0);
az : in std_logic_vector(31 downto 0);
bx : in std_logic_vector(31 downto 0);
by : in std_logic_vector(31 downto 0);
bz : in std_logic_vector(31 downto 0);
vx : out std_logic_vector(31 downto 0);
vy : out std_logic_vector(31 downto 0);
vz : out std_logic_vector(31 downto 0);
sc : out std_logic_vector(31 downto 0);
ack : in std_logic;
empty : out std_logic;
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
--paraminput : in vectorblock06; --! Vectores A,B
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
sync_chain_pending : out std_logic; --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
pipeline_pending : out std_logic --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
 
 
 
);
end entity;
 
58,20 → 78,58
--!TBXSTART:FACTORS_N_ADDENDS
signal sfactor : vectorblock12;
signal ssumando : vectorblock06;
signal sdpfifo_q : xfloat32;
signal sfactor0 : std_logic_vector(31 downto 0);
signal sfactor1 : std_logic_vector(31 downto 0);
signal sfactor2 : std_logic_vector(31 downto 0);
signal sfactor3 : std_logic_vector(31 downto 0);
signal sfactor4 : std_logic_vector(31 downto 0);
signal sfactor5 : std_logic_vector(31 downto 0);
signal sfactor6 : std_logic_vector(31 downto 0);
signal sfactor7 : std_logic_vector(31 downto 0);
signal sfactor8 : std_logic_vector(31 downto 0);
signal sfactor9 : std_logic_vector(31 downto 0);
signal sfactor10 : std_logic_vector(31 downto 0);
signal sfactor11 : std_logic_vector(31 downto 0);
--signal sfactor : vectorblock12;
signal ssumando0 : std_logic_vector(31 downto 0);
signal ssumando1 : std_logic_vector(31 downto 0);
signal ssumando2 : std_logic_vector(31 downto 0);
signal ssumando3 : std_logic_vector(31 downto 0);
signal ssumando4 : std_logic_vector(31 downto 0);
signal ssumando5 : std_logic_vector(31 downto 0);
--signal ssumando : vectorblock06;
signal sq0_q : std_logic_vector(31 downto 0);
--!TBXEND
--!TBXSTART:ARITHMETIC_RESULTS
signal sresult : vectorblock04;
signal sprd32blk : vectorblock06;
signal sadd32blk : vectorblock03;
signal ssqr32blk : xfloat32;
signal sinv32blk : xfloat32;
signal sqxyz_q : vectorblock03;
signal sqxyz_e : std_logic;
 
signal sp0 : std_logic_vector(31 downto 0);
signal sp1 : std_logic_vector(31 downto 0);
signal sp2 : std_logic_vector(31 downto 0);
signal sp3 : std_logic_vector(31 downto 0);
signal sp4 : std_logic_vector(31 downto 0);
signal sp5 : std_logic_vector(31 downto 0);
--signal sprd32blk : vectorblock06;
signal sa0 : std_logic_vector(31 downto 0);
signal sa1 : std_logic_vector(31 downto 0);
signal sa2 : std_logic_vector(31 downto 0);
signal sa3 : std_logic_vector(31 downto 0);
--signal sadd32blk : vectorblock03;
signal ssq32 : std_logic_vector(31 downto 0);
signal sinv32 : std_logic_vector(31 downto 0);
signal sqx_q : std_logic_vector(31 downto 0);
signal sqy_q : std_logic_vector(31 downto 0);
signal sqz_q : std_logic_vector(31 downto 0);
--signal sqxyz_q : vectorblock03;
signal sq1_e : std_logic;
--!TBXEND
79,20 → 137,41
signal ssync_chain : std_logic_vector(ssync_chain_max downto ssync_chain_min);
--!TBXEND
 
signal qxyzd : std_logic_vector(95 downto 0);
signal qxyzq : std_logic_vector(95 downto 0);
--signal qxyzd : std_logic_vector(95 downto 0);
--signal qxyzq : std_logic_vector(95 downto 0);
signal sq2_d : std_logic_vector(31 downto 0);
signal sq2_q : std_logic_vector(31 downto 0);
signal sq2_w : std_logic;
signal sq2_e : std_logic;
 
signal sqr_e : std_logic;
signal sqr_w : std_logic; --! Salidas de escritura y lectura en las colas de resultados.
signal sqr_dx : std_logic_vector(31 downto 0);
signal sqr_dy : std_logic_vector(31 downto 0);
signal sqr_dz : std_logic_vector(31 downto 0);
signal sqr_dsc : std_logic_vector(31 downto 0);
 
signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
 
signal sinv32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
signal ssqr32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
signal sa0o : std_logic_vector(31 downto 0);
signal sa1o : std_logic_vector(31 downto 0);
signal sa2o : std_logic_vector(31 downto 0);
signal sa3o : std_logic_vector(31 downto 0);
--signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
signal sp0o : std_logic_vector(31 downto 0);
signal sp1o : std_logic_vector(31 downto 0);
signal sp2o : std_logic_vector(31 downto 0);
signal sp3o : std_logic_vector(31 downto 0);
signal sp4o : std_logic_vector(31 downto 0);
signal sp5o : std_logic_vector(31 downto 0);
--signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
signal sinv32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
signal ssq32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
component arithblock
port (
101,20 → 180,52
rst : in std_logic;
sign : in std_logic;
factor0 : in std_logic_vector(31 downto 0);
factor1 : in std_logic_vector(31 downto 0);
factor2 : in std_logic_vector(31 downto 0);
factor3 : in std_logic_vector(31 downto 0);
factor4 : in std_logic_vector(31 downto 0);
factor5 : in std_logic_vector(31 downto 0);
factor6 : in std_logic_vector(31 downto 0);
factor7 : in std_logic_vector(31 downto 0);
factor8 : in std_logic_vector(31 downto 0);
factor9 : in std_logic_vector(31 downto 0);
factor10 : in std_logic_vector(31 downto 0);
factor11 : in std_logic_vector(31 downto 0);
--prd32blki : in vectorblock06;
prd32blki : in vectorblock12;
add32blki : in vectorblock06;
sumando0 : in std_logic_vector(31 downto 0);
sumando1 : in std_logic_vector(31 downto 0);
sumando2 : in std_logic_vector(31 downto 0);
sumando3 : in std_logic_vector(31 downto 0);
sumando4 : in std_logic_vector(31 downto 0);
sumando5 : in std_logic_vector(31 downto 0);
--add32blki : in vectorblock06;
add32blko : out vectorblock03;
prd32blko : out vectorblock06;
a0 : out std_logic_vector(31 downto 0);
a1 : out std_logic_vector(31 downto 0);
a2 : out std_logic_vector(31 downto 0);
a3 : out std_logic_vector(31 downto 0);
--add32blko : out vectorblock03;
sq32o : out xfloat32;
inv32o : out xfloat32
p0 : out std_logic_vector(31 downto 0);
p1 : out std_logic_vector(31 downto 0);
p2 : out std_logic_vector(31 downto 0);
p3 : out std_logic_vector(31 downto 0);
p4 : out std_logic_vector(31 downto 0);
p5 : out std_logic_vector(31 downto 0);
--prd32blko : out vectorblock06;
sq32o : out std_logic_vector(31 downto 0);
inv32o : out std_logic_vector(31 downto 0)
);
end component;
begin
--! Debug
sumando5 <= sa2o;
 
--! Bloque Aritm&eacute;tico
ap : arithblock
122,168 → 233,246
clk => clk,
rst => rst,
sign => s,
sign => dcs(0),
prd32blki => sfactor,
add32blki => ssumando,
factor0 =>sfactor0,
factor1 =>sfactor1,
factor2 =>sfactor2,
factor3 =>sfactor3,
factor4 =>sfactor4,
factor5 =>sfactor5,
factor6 =>sfactor6,
factor7 =>sfactor7,
factor8 =>sfactor8,
factor9 =>sfactor9,
factor10=>sfactor10,
factor11=>sfactor11,
--prd32blki => sfactor,
 
sumando0=>ssumando0,
sumando1=>ssumando1,
sumando2=>ssumando2,
sumando3=>ssumando3,
sumando4=>ssumando4,
sumando5=>ssumando5,
--add32blki => ssumando,
add32blko => sadd32blko,
prd32blko => sprd32blko,
a0=>sa0o,
a1=>sa1o,
a2=>sa2o,
a3=>sa3o,
--add32blko => sadd32blko,
sq32o => ssqr32blko,
inv32o => sinv32blko
p0=>sp0o,
p1=>sp1o,
p2=>sp2o,
p3=>sp3o,
p4=>sp4o,
p5=>sp5o,
--prd32blko => sprd32blko,
sq32o=> ssq32o,
inv32o=> sinv32o
);
--! Cadena de sincronizaci&oacute;n: 29 posiciones.
sync_chain_pending <= sync_chain_1 or not(sq2_e) or not(sqxyz_e);
pipeline_pending <= sync_chain_1 or not(sq2_e) or not(sq1_e) or not(sqr_e);
empty <= sqr_e;
sync_chain_proc:
process(clk,rst,sync_chain_1)
begin
if rst=rstMasterValue then
 
ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
dx <= (others => '0');
dy <= (others => '0');
dz <= (others => '0');
dsc <= (others => '0');
elsif clk'event and clk='1' then
elsif clk'event and clk='1' then
 
 
if sqr_w='1' then
dx <= ssumando4;
dy <= ssumando5;
dz <= sa3;
dsc <= sqr_dsc;
end if;
for i in ssync_chain_max downto ssync_chain_min+1 loop
ssync_chain(i) <= ssync_chain(i-1);
end loop;
ssync_chain(ssync_chain_min) <= sync_chain_1;
 
end if;
end process sync_chain_proc;
--! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, simplemente son abstracciones a nivel de c&oacute;digo y no representar&aacute; cambios en la s&iacute;ntesis.
qresult_d <= sresult;
--! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, son abstracciones de c&oacute;digo tambi&eacute;n, sin embargo se realizan a trav&eacute;s de registros.
register_products_outputs:
process (clk)
begin
if clk'event and clk='1' then
sprd32blk <= sprd32blko;
sadd32blk <= sadd32blko;
sinv32blk <= sinv32blko;
--! Raiz Cuadrada.
ssqr32blk <= ssqr32blko;
sp0 <= sp0o;
sp1 <= sp1o;
sp2 <= sp2o;
sp3 <= sp3o;
sp4 <= sp4o;
sp5 <= sp5o;
sa0 <= sa0o;
sa1 <= sa1o;
sa2 <= sa2o;
sa3 <= sa3o;
sinv32 <= sinv32o;
ssq32 <= ssq32o;
end if;
end process;
--! Decodificaci&oacute;n del Datapath.
datapathproc:process(s,d,c,paraminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,sqxyz_q,ssync_chain,ssqr32blk,sq2_q)
datapathproc:process(dcs,ax,bx,ay,by,az,bz,sinv32,sp0,sp1,sp2,sp3,sp4,sp5,sa0,sa1,sa2,sq0_q,sqx_q,sqy_q,sqz_q,ssync_chain,ssq32,sq2_q)
begin
--Summador 0: DORC!
if (d or c)='1' then
ssumando(s0) <= sprd32blk(p0);
ssumando(s1) <= sprd32blk(p1);
else
ssumando(s0) <= paraminput(ax);
ssumando(s1) <= paraminput(bx);
end if;
--Sumador 1:
if d='1' then
ssumando(s2) <= sadd32blk(a0);
ssumando(s3) <= sdpfifo_q;
elsif c='0' then
ssumando(s2) <= paraminput(ay);
ssumando(s3) <= paraminput(by);
else
ssumando(s2) <= sprd32blk(p2);
ssumando(s3) <= sprd32blk(p3);
end if;
--S2
if c='0' then
ssumando(s4) <= paraminput(az);
ssumando(s5) <= paraminput(bz);
else
ssumando(s4) <= sprd32blk(p4);
ssumando(s5) <= sprd32blk(p5);
end if;
--P0,P1,P2
sfactor(f4) <= paraminput(az);
if (not(d) and c)='1' then
sfactor(f0) <= paraminput(ay);
sfactor(f1) <= paraminput(bz);
sfactor(f2) <= paraminput(az);
sfactor(f3) <= paraminput(by);
sfactor(f5) <= paraminput(bx);
else
sfactor(f0) <= paraminput(ax);
sfactor(f2) <= paraminput(ay);
sfactor(f1) <= paraminput(bx) ;
sfactor(f3) <= paraminput(by) ;
sfactor(f5) <= paraminput(bz) ;
end if;
--P3 P4 P5
if (c and s)='1' then
sfactor(f6) <= paraminput(ax);
sfactor(f9) <= paraminput(by);
else
sfactor(f6) <= sinv32blk;
sfactor(f9) <= sqxyz_q(qy);
end if;
if d='1' then
if s='0' then
sfactor(f7) <= sqxyz_q(qx);
sfactor(f8) <= sinv32blk;
sfactor(f10) <= sinv32blk;
sfactor(f11) <= sqxyz_q(qz);
else
sfactor(f7) <= paraminput(bx);
sfactor(f8) <= paraminput(ay);
sfactor(f10) <= paraminput(az);
sfactor(f11) <= paraminput(bz);
end if;
else
sfactor(f7) <= paraminput(bz);
sfactor(f8) <= paraminput(ax);
sfactor(f10) <= paraminput(ay);
sfactor(f11) <= paraminput(bx);
end if;
--res0,1,2
if d='1' then
sresult(qx) <= sprd32blk(p3);
sresult(qy) <= sprd32blk(p4);
sresult(qz) <= sprd32blk(p5);
else
sresult(qx) <= sadd32blk(a0);
sresult(qy) <= sadd32blk(a1);
sresult(qz) <= sadd32blk(a2);
end if;
--res3
sresult(qsc) <= sq2_q;
if c='1' then
sq2_d <= ssqr32blk;
sq2_w <= ssync_chain(22) and d and not(s);
else
sq2_w <= ssync_chain(21) and d and not(s);
sq2_d <= sadd32blk(a1);
end if;
if d='1' then
if s='1'then
qresult_w <= ssync_chain(5);
else
qresult_w<= ssync_chain(27);
end if;
else
if c='1' and s='1' then
qresult_w <= ssync_chain(13);
elsif c='0' then
qresult_w <= ssync_chain(9);
else
qresult_w <= '0';
end if;
end if;
case dcs is
when "011" =>
 
sq2_w <= '0';
sq2_d <= ssq32;
sfactor0 <= ay;
sfactor1 <= bz;
sfactor2 <= az;
sfactor3 <= by;
sfactor4 <= az;
sfactor5 <= bx;
sfactor6 <= ax;
sfactor7 <= bz;
sfactor8 <= ax;
sfactor9 <= by;
sfactor10 <= ay;
sfactor11 <= bx;
ssumando0 <= sp0;
ssumando1 <= sp1;
ssumando2 <= sp2;
ssumando3 <= sp3;
ssumando4 <= sp4;
ssumando5 <= sp5;
sqr_dx <= sa0;
sqr_dy <= sa1;
sqr_dz <= sa2;
sqr_w <= ssync_chain(13);
when"000"|"001" =>
 
sq2_w <= '0';
sq2_d <= ssq32;
 
sfactor0 <= ay;
sfactor1 <= bz;
sfactor2 <= az;
sfactor3 <= by;
sfactor4 <= az;
sfactor5 <= bx;
sfactor6 <= ax;
sfactor7 <= bz;
sfactor8 <= ax;
sfactor9 <= by;
sfactor10 <= ay;
sfactor11 <= bx;
 
ssumando0 <= ax;
ssumando1 <= bx;
ssumando2 <= ay;
ssumando3 <= by;
ssumando4 <= az;
ssumando5 <= bz;
sqr_dx <= sa0;
sqr_dy <= sa1;
sqr_dz <= sa2;
sqr_w <= ssync_chain(9);
when"110" |"100" =>
sfactor0 <= ax;
sfactor1 <= bx;
sfactor2 <= ay;
sfactor3 <= by;
sfactor4 <= az;
sfactor5 <= bz;
sfactor6 <= sinv32;
sfactor7 <= sqx_q;
sfactor8 <= sinv32;
sfactor9 <= sqy_q;
sfactor10 <= sinv32;
sfactor11 <= sqz_q;
ssumando0 <= sp0;
ssumando1 <= sp1;
ssumando2 <= sa0;
ssumando3 <= sq0_q;
ssumando4 <= az;
ssumando5 <= bz;
if dcs(1)='1' then
sq2_d <= ssq32;
sq2_w <= ssync_chain(22);
else
sq2_d <= sa1;
sq2_w <= ssync_chain(21);
end if;
sqr_dx <= sp3;
sqr_dy <= sp4;
sqr_dz <= sp5;
sqr_w <= ssync_chain(27);
when others =>
sq2_w <= '0';
sq2_d <= ssq32;
sfactor0 <= ax;
sfactor1 <= bx;
sfactor2 <= ay;
sfactor3 <= by;
sfactor4 <= az;
sfactor5 <= bz;
sfactor6 <= ax;
sfactor7 <= bx;
sfactor8 <= ay;
sfactor9 <= by;
sfactor10 <= az;
sfactor11 <= bz;
ssumando0 <= sp0;
ssumando1 <= sp1;
ssumando2 <= sa0;
ssumando3 <= sq0_q;
ssumando4 <= az;
ssumando5 <= bz;
 
sqr_dx <= sp3;
sqr_dy <= sp4;
sqr_dz <= sp5;
 
sqr_w <= ssync_chain(5);
end case;
end process;
--! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.
290,8 → 479,8
q0 : scfifo --! Debe ir registrada la salida.
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 3,
lpm_numwords => 6,
lpm_widthu => 4,
lpm_numwords => 16,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
303,15 → 492,15
clock => clk,
rdreq => ssync_chain(13),
wrreq => ssync_chain(5),
data => sprd32blk(p2),
q => sdpfifo_q
data => sp2,
q => sq0_q
);
--! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.
q2 : scfifo --! Debe ir registrada la salida.
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 3,
lpm_numwords => 5,
lpm_widthu => 4,
lpm_numwords => 16,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 32,
324,26 → 513,19
sclr => '0',
clock => clk,
empty => sq2_e,
q => sq2_q,
q => sqr_dsc,
wrreq => sq2_w,
data => sq2_d
);
--! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
qxyzd(ax*32+31 downto ax*32) <= paraminput(ax);
qxyzd(ay*32+31 downto ay*32) <= paraminput(ay);
qxyzd(az*32+31 downto az*32) <= paraminput(az);
sqxyz_q(ax) <= qxyzq(ax*32+31 downto ax*32);
sqxyz_q(ay) <= qxyzq(ay*32+31 downto ay*32);
sqxyz_q(az) <= qxyzq(az*32+31 downto az*32);
q1xyz : scfifo
qx : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 96,
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
351,14 → 533,132
port map (
aclr => '0',
clock => clk,
empty => sqxyz_e,
empty => sq1_e,
rdreq => ssync_chain(23),
wrreq => sync_chain_1,
data => qxyzd,
q => qxyzq
data => ax,
q => sqx_q
);
 
qy : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
rdreq => ssync_chain(23),
wrreq => sync_chain_1,
data => ay,
q => sqy_q
);
qz : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
rdreq => ssync_chain(23),
wrreq => sync_chain_1,
data => az,
q => sqz_q
);
--!***********************************************************************************************************
--!Q RESULT
--!***********************************************************************************************************
--Colas de resultados
rx : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
empty => sqr_e,
rdreq => ack,
wrreq => sqr_w,
data => sqr_dx,
q => vx
);
ry : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
rdreq => ack,
wrreq => sqr_w,
data => sqr_dy,
q => vy
);
rz : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
rdreq => ack,
wrreq => sqr_w,
data => sqr_dz,
q => vz
);
rsc : scfifo
generic map (
allow_rwcycle_when_full => "ON",
lpm_widthu => 5,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_width => 32,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
aclr => '0',
clock => clk,
rdreq => ack,
wrreq => sqr_w,
data => sqr_dsc,
q => sc
);
end architecture;
/raytrac/branches/fp_sgdma/fadd32long.vhd
34,15 → 34,15
port (
clk,dpc : in std_logic;
a32,b32 : in xfloat32;
c32 : out xfloat32
a32,b32 : in std_logic_vector(31 downto 0);
c32 : out std_logic_vector(31 downto 0)
);
end entity;
architecture fadd32_arch of fadd32long is
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
attribute altera_attribute : string;
attribute altera_attribute of fadd32_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
--attribute altera_attribute : string;
--attribute altera_attribute of fadd32_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
--!TBXSTART:STAGE0
signal s0delta : std_logic_vector(8 downto 0);
/raytrac/branches/fp_sgdma/raytrac.vhd
74,9 → 74,13
 
architecture raytrac_arch of raytrac is
 
--! Debug
signal ssumando5 : xfloat32;
signal sphantom_q: std_logic_vector(31 downto 0);
 
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
attribute altera_attribute : string;
attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
--attribute altera_attribute : string;
--attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
 
type registerblock is array (15 downto 0) of xfloat32;
123,12 → 127,16
constant reg_ctrl_rlsc : integer:=14; --! RLSC bit : Reload Load Sync Chain.
constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
constant reg_ctrl_nfetch_low : integer:=16; --! NFETCH_LOW : Lower bit to program the number of addresses to load in the interconnection.
constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
constant reg_ctrl_aeb : integer:=17; --! A==B.
constant reg_ctrl_ageb : integer:=18; --! A>=B.
constant reg_ctrl_nfetch_low : integer:=19; --! NFETCH_LOW : Lower bit to program the number of addresses to load in the interconnection.
constant reg_ctrl_nfetch_high : integer:=30; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
--! Avalon MM Slave
signal sreg_block : registerblock;
signal sslave_read : std_logic;
signal sslave_write : std_logic;
143,27 → 151,24
--! State Machine and event signaling
signal sm : transferState;
signal sres_ack : std_logic;
signal sr_e : std_logic;
signal sr_ack : std_logic;
signal soutb_ack : std_logic;
signal sres_q : std_logic_vector (4*wd-1 downto 0);
signal sres_d : vectorblock04;
signal soutb_d : std_logic_vector(wd-1 downto 0);
signal sres_w : std_logic;
signal soutb_w : std_logic;
signal sres_e : std_logic;
signal soutb_e : std_logic;
signal soutb_ae : std_logic;
signal soutb_af : std_logic;
signal soutb_usedw : std_logic_vector(fd-1 downto 0);
 
signal ssync_chain_1 : std_logic;
signal ssync_chain_pending : std_logic;
signal sfetch_data_pending : std_logic;
signal sload_add_pending : std_logic;
196,23 → 201,44
--! Arithmetic Pipeline and Data Path Control
component ap_n_dpc
port (
sumando5 : out xfloat32;
clk : in std_logic;
rst : in std_logic;
paraminput : in vectorblock06; --! Vectores A,B
dx : out std_logic_vector(31 downto 0);
dy : out std_logic_vector(31 downto 0);
dz : out std_logic_vector(31 downto 0);
dsc : out std_logic_vector(31 downto 0);
ax : in std_logic_vector(31 downto 0);
ay : in std_logic_vector(31 downto 0);
az : in std_logic_vector(31 downto 0);
bx : in std_logic_vector(31 downto 0);
by : in std_logic_vector(31 downto 0);
bz : in std_logic_vector(31 downto 0);
vx : out std_logic_vector(31 downto 0);
vy : out std_logic_vector(31 downto 0);
vz : out std_logic_vector(31 downto 0);
sc : out std_logic_vector(31 downto 0);
ack : in std_logic;
empty : out std_logic;
--paraminput : in vectorblock06; --! Vectores A,B
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
sync_chain_pending : out std_logic;
pipeline_pending : out std_logic --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end component;
signal sparaminput : vectorblock06;
signal svx,svy,svz,ssc : std_logic_vector(31 downto 0);
signal sdx,sdy,sdz,sdsc : std_logic_vector(31 downto 0);
begin
 
219,12 → 245,6
--!Zero agreggate
zero <= (others => '0');
sparaminput(ax) <= sreg_block(reg_ax);
sparaminput(ay) <= sreg_block(reg_ay);
sparaminput(az) <= sreg_block(reg_az);
sparaminput(bx) <= sreg_block(reg_bx);
sparaminput(by) <= sreg_block(reg_by);
sparaminput(bz) <= sreg_block(reg_bz);
--! *************************************************************************************************************************************************************************************************************************************************************
--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
233,18 → 253,29
--! Arithpipeline and Datapath Control Instance
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
port map (
sumando5 => ssumando5,
 
clk => clk,
rst => rst,
paraminput => sparaminput,
d => sreg_block(reg_ctrl)(reg_ctrl_d),
c => sreg_block(reg_ctrl)(reg_ctrl_c),
s => sreg_block(reg_ctrl)(reg_ctrl_s),
dx => sdx,
dy => sdy,
dz => sdz,
dsc => sdsc,
ax => sreg_block(reg_ax),
ay => sreg_block(reg_ay),
az => sreg_block(reg_az),
bx => sreg_block(reg_bx),
by => sreg_block(reg_by),
bz => sreg_block(reg_bz),
vx => svx,
vy => svy,
vz => svz,
sc => ssc,
ack => sr_ack,
empty => sr_e,
dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
sync_chain_1 => ssync_chain_1,
sync_chain_pending => ssync_chain_pending,
qresult_w => sres_w,
qresult_d => sres_d
pipeline_pending => spipeline_pending
);
252,7 → 283,7
--! TRANSFER CONTROL RTL CODE
--! ******************************************************************************************************************************************************
TRANSFER_CONTROL:
process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
begin
--! Conexi&oacuteln a se&ntilde;ales externas.
270,12 → 301,6
--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a trav&eacute;s de la interconexi&oacute;n
swrite_pending <= not(soutb_e);
--! ELEMENTO DE SINCRONIZACION ARITH PIPELINE: Hay datos transitando por el pipeline aritm&eacute;tico.
if ssync_chain_pending='1' or sres_e='0' then
spipeline_pending <= '1';
else
spipeline_pending <= '0';
end if;
--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a trav&eacute;s de la interconexi&oacute;n.
if sdata_fetch_counter=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) then
433,7 → 458,7
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
sreg_block(reg_ctrl)(reg_ctrl_flags_dc downto reg_ctrl_flags_fc) <= sdrain_condition & sflood_condition;
sreg_block(reg_ctrl)(reg_ctrl_flags_ap downto reg_ctrl_flags_wp) <= sload_add_pending & sfetch_data_pending & sparamload_pending & spipeline_pending & swrite_pending;
else
--! Flow Control: Cambiar a Source porque aun hay elementos transitando.
483,6 → 508,8
if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
sreg_block(reg_ctrl)(reg_ctrl_irq downto reg_ctrl_nfetch_low) <= sslave_writedata(reg_ctrl_irq downto reg_ctrl_nfetch_low);
sreg_block(reg_ctrl)(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb) <= sslave_writedata(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb);
sreg_block(reg_ctrl)(reg_ctrl_rlsc) <= sslave_writedata(reg_ctrl_rlsc);
sreg_block(reg_ctrl)(reg_ctrl_ageb downto reg_ctrl_alb) <=sslave_writedata(reg_ctrl_ageb downto reg_ctrl_alb);
end if;
when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
511,11 → 538,8
--! ******************************************************************************************************************************************************
--! FLOW CONTROL RTL CODE
--! ******************************************************************************************************************************************************
--! Colas de resultados y buffer de salida
--! buffer de salida
--! ******************************************************************************************************************************************************
res:scfifo
generic map (lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 128, lpm_widthu => fd, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d(qsc)&sres_d(qx)&sres_d(qy)&sres_d(qz));
output_buffer:scfifo
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
524,7 → 548,7
--! ******************************************************************************************************************************************************
 
FLOW_CONTROL_OUTPUT_STAGE:
process (clk,rst,master_readdata, master_readdatavalid,sres_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,sres_q,supload_start)
process (clk,rst,master_readdata, master_readdatavalid,sr_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,supload_start)
begin
 
536,20 → 560,20
soutb_w <= master_readdatavalid;
else
--!Modo Arithmetic Pipeline
soutb_w <= not(sres_e);
soutb_w <= not(sr_e);
end if;
--! Control de lectura de la cola de resultados.
if sres_e='0' then
if sr_e='0' then
--!Hay datos en la cola de resultados.
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
sres_ack <= '1';
sr_ack <= '1';
else
sres_ack <= '0';
sr_ack <= '0';
end if;
else
sres_ack <= '0';
sr_ack <= '0';
end if;
557,13 → 581,13
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexi&oacute;n
case supload_chain is
when UPVX =>
soutb_d <= sres_q (32*qx+31 downto 32*qx);
soutb_d <= svx;
when UPVY =>
soutb_d <= sres_q (32*qy+31 downto 32*qy);
soutb_d <= svy;
when UPVZ =>
soutb_d <= sres_q (32*qz+31 downto 32*qz);
soutb_d <= svz;
when SC =>
soutb_d <= sres_q (32*qsc+31 downto 32*qsc);
soutb_d <= ssc;
when DMA =>
soutb_d <= master_readdata;
end case;
584,7 → 608,7
--! Modo de operaci&oacute;n normal.
case supload_chain is
when UPVX =>
if sres_e='1' then
if sr_e='1' then
supload_chain <= supload_start;
else
supload_chain <= UPVY;
701,7 → 725,7
--! *************************************************************************************************************************************************************************************************************************************************************
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
low_register_bank:
process (clk,rst,sreg_block)
process (clk,rst,sreg_block,soutb_w,supload_chain)
begin
if rst=rstMasterValue then
for i in reg_scratch00 downto reg_vz loop
720,7 → 744,33
sslave_write <= slave_write;
sslave_read <= slave_read;
sslave_writedata <= slave_writedata;
for i in reg_scratch00 downto reg_vz loop
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_vx) <= sdx;
else
sreg_block(reg_vx) <= sdx;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_vy) <= sdy;
else
sreg_block(reg_vy) <= sdy;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_scratch00) <= sdz;
sreg_block(reg_vz) <= sdz;
else
sreg_block(reg_scratch00) <= sdz;
sreg_block(reg_vz) <= sdz;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_scalar) <= sdsc;
else
sreg_block(reg_scalar) <= sdsc;
end if;
for i in reg_scratch00-5 downto reg_vz loop
if sslave_address=i then
if sslave_write='1' then
sreg_block(i) <= sslave_writedata;
/raytrac/branches/fp_sgdma/arithpack.vhd
19,13 → 19,13
package arithpack is
--!Constantes usadas por los RTLs
constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant qsc: integer := 03;
constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
--constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant qsc: integer := 03;
--constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
--constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
--constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
--constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
--constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
--constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
subtype xfloat32 is std_logic_vector(31 downto 0);

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