OpenCores
URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

Subversion Repositories apbi2c

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/apbi2c/trunk/rtl/apb.v
97,6 → 97,7
 
//internal pin
output reg [13:0] INTERNAL_I2C_REGISTER_CONFIG,
output reg [13:0] INTERNAL_I2C_REGISTER_TIMEOUT,
output [31:0] WRITE_DATA_ON_TX,
output WR_ENA,
output RD_ENA,
119,7 → 120,7
assign RD_ENA = (PWRITE == 1'b0 & PENABLE == 1'b1 & PADDR == 32'd4 & PSELx == 1'b1)? 1'b1:1'b0;
 
//WRITE ON I2C MODULE
assign PREADY = ((WR_ENA == 1'b1 | RD_ENA == 1'b1 | PADDR == 32'd8) & (PENABLE == 1'b1 & PSELx == 1'b1))? 1'b1:1'b0;
assign PREADY = ((WR_ENA == 1'b1 | RD_ENA == 1'b1 | PADDR == 32'd8 | PADDR == 32'd12) & (PENABLE == 1'b1 & PSELx == 1'b1))? 1'b1:1'b0;
 
//INPUT TO WRITE ON TX FIFO
assign WRITE_DATA_ON_TX = (PADDR == 32'd0)? PWDATA:PWDATA;
143,6 → 144,7
if(!PRESETn)
begin
INTERNAL_I2C_REGISTER_CONFIG <= 14'd0;
INTERNAL_I2C_REGISTER_TIMEOUT <= 14'd0;
end
else
begin
152,6 → 154,10
begin
INTERNAL_I2C_REGISTER_CONFIG <= PWDATA[13:0];
end
else if(PADDR == 32'd12 && PSELx == 1'b1 && PWRITE == 1'b1 && PREADY == 1'b1)
begin
INTERNAL_I2C_REGISTER_TIMEOUT <= PWDATA[13:0];
end
else
begin
INTERNAL_I2C_REGISTER_CONFIG <= INTERNAL_I2C_REGISTER_CONFIG;
/apbi2c/trunk/rtl/module_i2c.v
1130,7 → 1130,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[9:9];
 
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
1669,7 → 1669,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[26:26];
 
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
1913,7 → 1913,7
begin
fifo_tx_rd_en <= 1'b0;
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd3)
begin
count_send_data <= count_send_data + 12'd1;
/apbi2c/trunk/rtl/fifo.v
26,7 → 26,6
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
//// Ronal Dario Celaya ,rcelaya.dario@gmail.com
////
/////////////////////////////////////////////////////////////////
////
88,17 → 87,19
);
 
 
// reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
parameter integer DEPTH = 1 << AWIDTH;
wire [DWIDTH-1:0] data_ram_out;
wire wr_en_ram;
wire rd_en_ram;
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
//parameter integer DEPTH = 1 << AWIDTH;
//wire [DWIDTH-1:0] data_ram_out;
//wire wr_en_ram;
//wire rd_en_ram;
 
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
reg [AWIDTH:0] counter;
reg [AWIDTH-1:0] counter;
 
 
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
wire [AWIDTH-1:0] w_counter;
//Write pointer
always@(posedge clock)
begin
108,7 → 109,8
end
else if (wr_en && !f_full)
begin
wr_ptr <= wr_ptr + 1'b1;
mem[wr_ptr]<=data_in;
wr_ptr <= wr;
end
end
 
121,7 → 123,7
end
else if (rd_en && !f_empty)
begin
rd_ptr <= rd_ptr + 1'b1;
rd_ptr <= rd;
end
end
 
130,27 → 132,32
begin
if (reset)
begin
counter <= {(AWIDTH+1){1'b0}};
counter <= {(AWIDTH){1'b0}};
end
else
begin
if (rd_en && !f_empty && !wr_en)
begin
counter <= counter - 1'b1;
counter <= w_counter;
end
else if (wr_en && !f_full && !rd_en)
begin
counter <= counter + 1'b1;
counter <= w_counter;
end
end
end
 
assign f_full = (counter == DEPTH- 1) ;
assign f_empty = (counter == {AWIDTH{1'b0}});
assign wr_en_ram = wr_en;
assign rd_en_ram = rd_en;
assign data_out = data_ram_out;
 
assign f_full = (counter == 4'd15)?1'b1:1'b0;//DEPTH- 1) ;
assign f_empty = (counter == 4'd0)?1'b1:1'b0;//{AWIDTH{1'b0}});
assign wr = (wr_en && !f_full)?wr_ptr + 4'd1:wr_ptr + 4'd0;
assign rd = (rd_en && !f_empty)?rd_ptr+ 4'd1:rd_ptr+ 4'd0;
assign w_counter = (rd_en && !f_empty && !wr_en)? counter - 4'd1:
(wr_en && !f_full && !rd_en)? counter + 4'd1:
w_counter + 4'd0;
//assign wr_en_ram = wr_en;
//assign rd_en_ram = rd_en;
assign data_out = mem[rd_ptr];//data_ram_out;
/*
dp_ram #(DWIDTH, AWIDTH)
RAM_1 (
.clock(clock),
162,5 → 169,5
.data_out(data_ram_out),
.rd_addr(rd_ptr)
);
 
*/
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.