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URL https://opencores.org/ocsvn/ax8/ax8/trunk

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Rev 23 → Rev 24

/trunk/rtl/vhdl/A90S1200.vhd
1,7 → 1,7
--
-- 90S1200 compatible microcontroller core
--
-- Version : 0220b
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
47,6 → 47,7
-- 0146 : First release
-- 0220 : Changed to synchronous ROM
-- 0220b : Changed reset
-- 0221 : Changed to configurable buses
 
--Registers: Comments:
--$3F SREG Status Register Implemented in the AX8 core
74,7 → 75,8
 
entity A90S1200 is
generic(
SyncReset : boolean := true
SyncReset : boolean := true;
TriState : boolean := false
);
port(
Clk : in std_logic;
103,6 → 105,7
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
signal ROM_Data : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(7 downto 0);
signal IO_Rd : std_logic;
signal IO_Wr : std_logic;
signal IO_Addr : std_logic_vector(5 downto 0);
126,6 → 129,14
signal TOV0 : std_logic;
signal Int_Trig : std_logic_vector(15 downto 1);
signal Int_Acc : std_logic_vector(15 downto 1);
signal TCCR : std_logic_vector(2 downto 0);
signal TCNT : std_logic_vector(7 downto 0);
signal DirB : std_logic_vector(7 downto 0);
signal Port_InB : std_logic_vector(7 downto 0);
signal Port_OutB : std_logic_vector(7 downto 0);
signal DirD : std_logic_vector(7 downto 0);
signal Port_InD : std_logic_vector(7 downto 0);
signal Port_OutD : std_logic_vector(7 downto 0);
 
begin
 
151,10 → 162,6
end generate;
 
-- Registers/Interrupts
IO_RData <= "00" & Sleep_En & "000" & ISC0 when IO_Rd = '1' and IO_Addr = "110101" else "ZZZZZZZZ"; -- $35 MCUCR
IO_RData <= "0" & Int0_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ"; -- $3B GIMSK
IO_RData <= "000000" & TOIE0 & "0" when IO_Rd = '1' and IO_Addr = "111001" else "ZZZZZZZZ"; -- $39 TIMSK
IO_RData <= "000000" & TOV0 & "0" when IO_Rd = '1' and IO_Addr = "111000" else "ZZZZZZZZ"; -- $38 TIFR
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
220,11 → 227,12
Sleep_En => Sleep_En,
Int_Trig => Int_Trig,
Int_Acc => Int_Acc,
SREG => SREG,
IO_Rd => IO_Rd,
IO_Wr => IO_Wr,
IO_Addr => IO_Addr,
IO_WData => IO_WData,
IO_RData => IO_RData);
IO_RData => IO_RData,
IO_WData => IO_WData);
 
TCCR_Sel <= '1' when IO_Addr = "110011" else '0'; -- $33 TCCR0
TCNT_Sel <= '1' when IO_Addr = "110010" else '0'; -- $32 TCNT0
234,10 → 242,10
T => T0,
TCCR_Sel => TCCR_Sel,
TCNT_Sel => TCNT_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
TCCR => TCCR,
TCNT => TCNT,
Int => TC_Trig);
 
PINB_Sel <= '1' when IO_Addr = "010101" else '0';
246,27 → 254,66
PIND_Sel <= '1' when IO_Addr = "010000" else '0';
DDRD_Sel <= '1' when IO_Addr = "010001" else '0';
PORTD_Sel <= '1' when IO_Addr = "010010" else '0';
porta : AX_Port port map(
portb : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTB_Sel,
DDR_Sel => DDRB_Sel,
PIN_Sel => PINB_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
Dir => DirB,
Port_Input => Port_InB,
Port_Output => Port_OutB,
IOPort => Port_B);
portb : AX_Port port map(
portd : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTD_Sel,
DDR_Sel => DDRD_Sel,
PIN_Sel => PIND_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
Dir => DirD,
Port_Input => Port_InD,
Port_Output => Port_OutD,
IOPort => Port_D);
 
gNoTri : if not TriState generate
with IO_Addr select
IO_RData <= SREG when "111111",
"00" & Sleep_En & "000" & ISC0 when "110101",
"0" & Int0_En & "000000" when "111011",
"000000" & TOIE0 & "0" when "111001",
"000000" & TOV0 & "0" when "111000",
"00000" & TCCR when "110011",
TCNT when "110010",
Port_InB when "010101",
DirB when "010111",
Port_OutB when "011000",
Port_InD when "010000",
DirD when "010001",
Port_OutD when "010010",
"--------" when others;
end generate;
gTri : if TriState generate
IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";
 
IO_RData <= "00" & Sleep_En & "000" & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";
IO_RData <= "0" & Int0_En & "000000" when IO_Addr = "111011" else "ZZZZZZZZ";
IO_RData <= "000000" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";
IO_RData <= "000000" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";
 
IO_RData <= "00000" & TCCR when TCCR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= TCNT when TCNT_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirD when DDRD_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutD when PORTD_Sel = '1' else "ZZZZZZZZ";
end generate;
 
end;
/trunk/rtl/vhdl/AX8.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
-- Version : 0221b
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
48,6 → 48,7
-- 0146 : First release
-- 0220 : Added support for synchronous ROM
-- 0221 : Changed tristate buses
-- 0221b : Changed tristate buses
 
library IEEE;
use IEEE.std_logic_1164.all;
69,11 → 70,13
Sleep_En : in std_logic;
Int_Trig : in std_logic_vector(15 downto 1);
Int_Acc : out std_logic_vector(15 downto 1);
SREG : out std_logic_vector(7 downto 0);
SP : out std_logic_vector(15 downto 0);
IO_Rd : out std_logic;
IO_Wr : out std_logic;
IO_Addr : out std_logic_vector(5 downto 0);
IO_RData : in std_logic_vector(7 downto 0);
IO_WData : out std_logic_vector(7 downto 0);
IO_RData : inout std_logic_vector(7 downto 0);
WDR : out std_logic
);
end AX8;
81,8 → 84,8
architecture rtl of AX8 is
 
-- Registers
signal SREG : std_logic_vector(7 downto 0);
signal SP : unsigned(15 downto 0);
signal SREG_i : std_logic_vector(7 downto 0);
signal SP_i : unsigned(15 downto 0);
signal NPC : std_logic_vector(15 downto 0);
signal PC : std_logic_vector(15 downto 0);
signal PCH : std_logic_vector(7 downto 0);
205,7 → 208,7
RAM_Wr_ID <= RAM_IW;
end if;
end process;
process (ROM_Data, Inst, DidPause, Pause, SP, X, Y, Z, Disp, IPush)
process (ROM_Data, Inst, DidPause, Pause, SP_i, X, Y, Z, Disp, IPush)
begin
Rd_Addr <= (others => '-');
Rr_Addr <= (others => '-');
279,7 → 282,7
Dec_X <= '1';
end if;
if Inst(3 downto 0) = "1111" then -- POP
Rr_Addr <= std_logic_vector(SP + 1);
Rr_Addr <= std_logic_vector(SP_i + 1);
Inc_SP <= '1';
end if;
end if;
316,7 → 319,7
Dec_X <= '1';
end if;
if Inst(3 downto 0) = "1111" then -- PUSH
Rd_Addr <= std_logic_vector(SP);
Rd_Addr <= std_logic_vector(SP_i);
Dec_SP <= '1';
end if;
end if;
333,12 → 336,12
end if;
if ((DidPause /= "01" and (Inst = "1001010100001001" or Inst(15 downto 12) = "1101")) or IPush = '1') and BigISet then
-- RCALL, ICALL
Rd_Addr <= std_logic_vector(SP);
Rd_Addr <= std_logic_vector(SP_i);
Dec_SP <= '1';
end if;
if DidPause(0) = DidPause(1) and (Inst = "1001010100001000" or Inst = "1001010100011000") and BigISet then
-- RET, RETI
Rr_Addr <= std_logic_vector(SP + 1);
Rr_Addr <= std_logic_vector(SP_i + 1);
Inc_SP <= '1';
end if;
if DidPause = "00" and Inst = "1001010111001000" and BigISet then
388,12 → 391,11
end process;
 
-- IO access
SP <= std_logic_vector(SP_i);
IO_Addr <= IO_Addr_i;
IO_Rd <= IO_Rd_i;
IO_Wr <= IO_Wr_i;
IO_WData <= IO_BMData when Inst(15 downto 11) = "10011" and Inst(8) = '0' else Rd_Data;
IO_RData <= std_logic_vector(SP(7 downto 0)) when IO_Addr_i = "111101" and BigIset else "ZZZZZZZZ";
IO_RData <= std_logic_vector(SP(15 downto 8)) when IO_Addr_i = "111110" and BigIset else "ZZZZZZZZ";
IO_BTest <= Bit_Pattern and IO_RData;
IOZ_Skip <= '1' when ((IO_BTest /= "00000000") and (Do_SBIS = '1')) or
((IO_BTest = "00000000") and (Do_SBIC = '1')) else '0';
401,7 → 403,7
begin
if Reset_n = '0' then
if BigISet then
SP <= (others => '0');
SP_i <= (others => '0');
end if;
IO_Addr_i <= (others => '0');
IO_BMData <= (others => '0');
440,17 → 442,17
end if;
if IO_Wr_i = '1' and BigISet then
if IO_Addr_i = "111101" then --$3D ($5D) SPL Stack Pointer Low
SP(7 downto 0) <= unsigned(Rd_Data);
SP_i(7 downto 0) <= unsigned(Rd_Data);
end if;
if IO_Addr_i = "111110" then --$3E ($5E) SPH Stack Pointer High
SP(15 downto 8) <= unsigned(Rd_Data);
SP_i(15 downto 8) <= unsigned(Rd_Data);
end if;
end if;
if Dec_SP = '1' and BigISet then
SP <= SP - 1;
SP_i <= SP_i - 1;
end if;
if Inc_SP = '1' and BigISet then
SP <= SP + 1;
SP_i <= SP_i + 1;
end if;
end if;
end process;
499,30 → 501,30
end process;
 
-- Status register
IO_RData <= SREG when IO_Addr_i = "111111" else "ZZZZZZZZ";
SREG <= SREG_i;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
SREG <= "00000000";
SREG_i <= "00000000";
elsif Clk'event and Clk = '1' then
if IO_Wr_i = '1' and IO_Addr_i = "111111" then --$3F ($5F) SREG Status Register
SREG <= Rd_Data;
SREG_i <= Rd_Data;
end if;
if Inst(15 downto 8) = "10010100" and Inst(3 downto 0) = "1000" then
SREG(to_integer(unsigned(Inst(6 downto 4)))) <= not Inst(7); -- BSET, BCLR
SREG_i(to_integer(unsigned(Inst(6 downto 4)))) <= not Inst(7); -- BSET, BCLR
end if;
if Inst = "1001010100011000" then SREG(7) <= '1'; end if;
if Inst = "1001010100011000" then SREG_i(7) <= '1'; end if;
if IPush = '1' then
SREG(7) <= '0';
SREG_i(7) <= '0';
end if;
if Status_Wr(6) = '1' then SREG(6) <= Status_D(6); end if;
if Status_Wr(5) = '1' then SREG(5) <= Status_D(5); end if;
if Status_Wr(4) = '1' then SREG(4) <= Status_D(4); end if;
if Status_Wr(3) = '1' then SREG(3) <= Status_D(3); end if;
if Status_Wr(2) = '1' then SREG(2) <= Status_D(2); end if;
if Status_Wr(1) = '1' then SREG(1) <= Status_D(1); end if;
if Status_Wr(0) = '1' then SREG(0) <= Status_D(0); end if;
if Status_D_Wr = '1' and BigISet then SREG(4 downto 0) <= Status_D_R; end if;
if Status_Wr(6) = '1' then SREG_i(6) <= Status_D(6); end if;
if Status_Wr(5) = '1' then SREG_i(5) <= Status_D(5); end if;
if Status_Wr(4) = '1' then SREG_i(4) <= Status_D(4); end if;
if Status_Wr(3) = '1' then SREG_i(3) <= Status_D(3); end if;
if Status_Wr(2) = '1' then SREG_i(2) <= Status_D(2); end if;
if Status_Wr(1) = '1' then SREG_i(1) <= Status_D(1); end if;
if Status_Wr(0) = '1' then SREG_i(0) <= Status_D(0); end if;
if Status_D_Wr = '1' and BigISet then SREG_i(4 downto 0) <= Status_D_R; end if;
end if;
end process;
 
596,8 → 598,8
PCPause <= '1' when (IndSkip = '0' and ((Pause /= "00" and DidPause = "00") or DidPause(1) = '1')) or Sleep = '1' else '0';
RJmp <= '1' when Inst(15 downto 12) = "1100" or
(Inst(15 downto 12) = "1101" and DidPause = "10") or
(CBranch = '1' and Inst(10) = '0' and ((SREG and Bit_Pattern) /= "00000000")) or
(CBranch = '1' and Inst(10) = '1' and ((SREG and Bit_Pattern) = "00000000")) else '0';
(CBranch = '1' and Inst(10) = '0' and ((SREG_i and Bit_Pattern) /= "00000000")) or
(CBranch = '1' and Inst(10) = '1' and ((SREG_i and Bit_Pattern) = "00000000")) else '0';
HRet <= '1' when DidPause = "11" and BigIset and
(Inst = "1001010100001000" or Inst = "1001010100011000") else '0';
LRet <= '1' when DidPause = "10" and BigIset and
710,7 → 712,7
A => Rd_Data,
B => Op_Mux,
Q => Q,
SREG => SREG,
SREG => SREG_i,
PassB => PassB,
Skip => Inst_Skip,
Do_Other => Do_Other,
736,7 → 738,7
if Inst = "1001010110001000" and Sleep_En = '1' then
Sleep <= '1';
end if;
if Int_Trig /= "000000000000000" and SREG(7) = '1' then
if Int_Trig /= "000000000000000" and SREG_i(7) = '1' then
Sleep <= '0';
IPending <= '1';
end if;
/trunk/rtl/vhdl/AX_UART.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
44,6 → 44,8
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
61,7 → 63,10
Wr : in std_logic;
TXC_Clr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
UDR : out std_logic_vector(7 downto 0);
USR : out std_logic_vector(7 downto 3);
UCR : out std_logic_vector(7 downto 0);
UBRR : out std_logic_vector(7 downto 0);
RXD : in std_logic;
TXD : out std_logic;
Int_RX : out std_logic;
72,10 → 77,10
 
architecture rtl of AX_UART is
 
signal UDR : std_logic_vector(7 downto 0); -- UART I/O Data Register
signal USR : std_logic_vector(7 downto 3); -- UART Status Register
signal UCR : std_logic_vector(7 downto 0); -- UART Control Register
signal UBRR : std_logic_vector(7 downto 0); -- UART Baud Rate Register
signal UDR_i : std_logic_vector(7 downto 0); -- UART I/O Data Register
signal USR_i : std_logic_vector(7 downto 3); -- UART Status Register
signal UCR_i : std_logic_vector(7 downto 0); -- UART Control Register
signal UBRR_i : std_logic_vector(7 downto 0); -- UART Baud Rate Register
 
signal Baud16 : std_logic;
 
93,23 → 98,23
begin
 
-- Registers
Data_Out <= UDR when UDR_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
Data_Out <= USR & "000" when USR_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
Data_Out <= UCR(7 downto 1) & "0" when UCR_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
Data_Out <= UBRR when UBRR_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
UDR <= UDR_i;
USR <= USR_i;
UCR <= UCR_i;
UBRR <= UBRR_i;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
UCR(7 downto 2) <= "000000";
UCR(0) <= '0';
UBRR <= "00000000";
UCR_i(7 downto 2) <= "000000";
UCR_i(0) <= '0';
UBRR_i <= "00000000";
elsif Clk'event and Clk = '1' then
if UCR_Sel = '1' and Wr = '1' then
UCR(7 downto 2) <= Data_In(7 downto 2);
UCR(0) <= Data_In(0);
UCR_i(7 downto 2) <= Data_In(7 downto 2);
UCR_i(0) <= Data_In(0);
end if;
if UBRR_Sel = '1' and Wr = '1' then
UBRR <= Data_In;
UBRR_i <= Data_In;
end if;
end if;
end process;
123,7 → 128,7
Baud16 <= '0';
elsif Clk'event and Clk='1' then
if Baud_Cnt = "00000000" then
Baud_Cnt := unsigned(UBRR);
Baud_Cnt := unsigned(UBRR_i);
Baud16 <= '1';
else
Baud_Cnt := Baud_Cnt - 1;
154,15 → 159,15
end process;
 
-- Receive state machine
Int_RX <= USR(7) and UCR(7);
Int_RX <= USR_i(7) and UCR_i(7);
process (Clk, Reset_n)
begin
if Reset_n = '0' then
USR(7) <= '0';
USR(4) <= '0';
USR(3) <= '0';
UCR(1) <= '1';
UDR <= "00000000";
USR_i(7) <= '0';
USR_i(4) <= '0';
USR_i(3) <= '0';
UCR_i(1) <= '1';
UDR_i <= "00000000";
Overflow_t <= '0';
Bit_Phase <= "0000";
RX_ShiftReg(8 downto 0) <= "000000000";
169,8 → 174,8
RX_Bit_Cnt <= 0;
elsif Clk'event and Clk = '1' then
if UDR_Sel = '1' and Rd = '1' then
USR(7) <= '0';
USR(3) <= Overflow_t;
USR_i(7) <= '0';
USR_i(3) <= Overflow_t;
end if;
if Baud16 = '1' then
if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
184,23 → 189,23
end if;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if (UCR(2) = '0' and RX_Bit_Cnt = 9) or
(UCR(2) = '1' and RX_Bit_Cnt = 10) then -- Stop bit
if (UCR_i(2) = '0' and RX_Bit_Cnt = 9) or
(UCR_i(2) = '1' and RX_Bit_Cnt = 10) then -- Stop bit
RX_Bit_Cnt <= 0;
if UCR(4) = '1' then
USR(7) <= '1'; -- UART Receive complete
USR(4) <= not RX_Filtered; -- Framing error
Overflow_t <= USR(7);
if USR(7) = '0' or (UDR_Sel = '1' and Rd = '1') then
if UCR_i(4) = '1' then
USR_i(7) <= '1'; -- UART Receive complete
USR_i(4) <= not RX_Filtered; -- Framing error
Overflow_t <= USR_i(7);
if USR_i(7) = '0' or (UDR_Sel = '1' and Rd = '1') then
Overflow_t <= '0';
USR(3) <= '0';
UDR <= RX_ShiftReg(7 downto 0);
UCR(1) <= RX_ShiftReg(8);
USR_i(3) <= '0';
UDR_i <= RX_ShiftReg(7 downto 0);
UCR_i(1) <= RX_ShiftReg(8);
end if;
end if;
else
RX_ShiftReg(7 downto 0) <= RX_ShiftReg(8 downto 1);
if UCR(2) = '1' then -- CHR9
if UCR_i(2) = '1' then -- CHR9
RX_ShiftReg(8) <= RX_Filtered;
else
RX_ShiftReg(7) <= RX_Filtered;
230,13 → 235,13
end process;
 
-- Transmit state machine
Int_TR <= USR(5) and UCR(5);
Int_TC <= USR(6) and UCR(6);
Int_TR <= USR_i(5) and UCR_i(5);
Int_TC <= USR_i(6) and UCR_i(6);
process (Clk, Reset_n)
begin
if Reset_n = '0' then
USR(6) <= '0';
USR(5) <= '1';
USR_i(6) <= '0';
USR_i(5) <= '1';
TX_Bit_Cnt <= 0;
TX_ShiftReg <= (others => '0');
TX_Data <= (others => '0');
243,36 → 248,36
TXD <= '1';
elsif Clk'event and Clk = '1' then
if TXC_Clr = '1' or (USR_Sel = '1' and Wr = '1' and Data_In(6) = '1') then
USR(6) <= '0';
USR_i(6) <= '0';
end if;
if UDR_Sel = '1' and Wr = '1' and UCR(3) = '1' then
USR(5) <= '0';
if UDR_Sel = '1' and Wr = '1' and UCR_i(3) = '1' then
USR_i(5) <= '0';
TX_Data <= Data_In;
end if;
if TX_Tick = '1' then
case TX_Bit_Cnt is
when 0 =>
if USR(5) = '0' then
if USR_i(5) = '0' then
TX_Bit_Cnt <= 1;
end if;
TXD <= '1';
when 1 => -- Start bit
TX_ShiftReg(7 downto 0) <= TX_Data;
TX_ShiftReg(8) <= UCR(0);
USR(5) <= '1';
TX_ShiftReg(8) <= UCR_i(0);
USR_i(5) <= '1';
TXD <= '0';
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
when others =>
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
if UCR(2) = '1' then -- CHR9
if UCR_i(2) = '1' then -- CHR9
if TX_Bit_Cnt = 10 then
TX_Bit_Cnt <= 0;
USR(6) <= '1';
USR_i(6) <= '1';
end if;
else
if TX_Bit_Cnt = 9 then
TX_Bit_Cnt <= 0;
USR(6) <= '1';
USR_i(6) <= '1';
end if;
end if;
TXD <= TX_ShiftReg(0);
/trunk/rtl/vhdl/A90S2313.vhd
1,7 → 1,7
--
-- 90S2313 compatible microcontroller core
--
-- Version : 0220b
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
47,6 → 47,7
-- 0146 : First release
-- 0220 : Changed to synchronous ROM
-- 0220b : Changed reset
-- 0221 : Changed to configurable buses
 
--Registers: Comments:
--$3F SREG Status Register Implemented in the AX8 core
88,7 → 89,8
 
entity A90S2313 is
generic(
SyncReset : boolean := true
SyncReset : boolean := true;
TriState : boolean := false
);
port(
Clk : in std_logic;
123,6 → 125,8
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
signal ROM_Data : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(7 downto 0);
signal SP : std_logic_vector(15 downto 0);
signal IO_Rd : std_logic;
signal IO_Wr : std_logic;
signal IO_Addr : std_logic_vector(5 downto 0);
165,6 → 169,26
signal TOV1 : std_logic;
signal Int_Trig : std_logic_vector(15 downto 1);
signal Int_Acc : std_logic_vector(15 downto 1);
signal TCCR0 : std_logic_vector(2 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal COM : std_logic_vector(1 downto 0);
signal PWM : std_logic_vector(1 downto 0);
signal CRBH : std_logic_vector(1 downto 0);
signal CRBL : std_logic_vector(3 downto 0);
signal TCNT1 : std_logic_vector(15 downto 0);
signal IC : std_logic_vector(15 downto 0);
signal OCR : std_logic_vector(15 downto 0);
signal Tmp : std_logic_vector(15 downto 0);
signal UDR : std_logic_vector(7 downto 0);
signal USR : std_logic_vector(7 downto 3);
signal UCR : std_logic_vector(7 downto 0);
signal UBRR : std_logic_vector(7 downto 0);
signal DirB : std_logic_vector(7 downto 0);
signal Port_InB : std_logic_vector(7 downto 0);
signal Port_OutB : std_logic_vector(7 downto 0);
signal DirD : std_logic_vector(7 downto 0);
signal Port_InD : std_logic_vector(7 downto 0);
signal Port_OutD : std_logic_vector(7 downto 0);
 
begin
 
190,10 → 214,6
end generate;
 
-- Registers/Interrupts
IO_RData <= "00" & Sleep_En & "0" & ISC1 & ISC0 when IO_Rd = '1' and IO_Addr = "110101" else "ZZZZZZZZ"; -- $35 MCUCR
IO_RData <= Int_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ"; -- $3B GIMSK
IO_RData <= TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when IO_Rd = '1' and IO_Addr = "111001" else "ZZZZZZZZ"; -- $39 TIMSK
IO_RData <= TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when IO_Rd = '1' and IO_Addr = "111000" else "ZZZZZZZZ"; -- $38 TIFR
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
310,11 → 330,13
Sleep_En => Sleep_En,
Int_Trig => Int_Trig,
Int_Acc => Int_Acc,
SREG => SREG,
SP => SP,
IO_Rd => IO_Rd,
IO_Wr => IO_Wr,
IO_Addr => IO_Addr,
IO_WData => IO_WData,
IO_RData => IO_RData);
IO_RData => IO_RData,
IO_WData => IO_WData);
 
TCCR0_Sel <= '1' when IO_Addr = "110011" else '0'; -- $33 TCCR0
TCNT0_Sel <= '1' when IO_Addr = "110010" else '0'; -- $32 TCNT0
324,10 → 346,10
T => T0,
TCCR_Sel => TCCR0_Sel,
TCNT_Sel => TCNT0_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
TCCR => TCCR0,
TCNT => TCNT0,
Int => TC_Trig);
 
TCCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10111" else '0'; -- $2E TCCR1
347,7 → 369,14
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
COM => COM,
PWM => PWM,
CRBH => CRBH,
CRBL => CRBL,
TCNT => TCNT1,
IC => IC,
OCR => OCR,
Tmp => Tmp,
OC => OC,
Int_TO => TO_Trig,
Int_OC => OC_Trig,
368,7 → 397,10
Wr => IO_Wr,
TXC_Clr => Int_Acc(9),
Data_In => IO_WData,
Data_Out => IO_RData,
UDR => UDR,
USR => USR,
UCR => UCR,
UBRR => UBRR,
RXD => RXD,
TXD => TXD,
Int_RX => Int_Trig(7),
381,27 → 413,92
PIND_Sel <= '1' when IO_Addr = "010000" else '0';
DDRD_Sel <= '1' when IO_Addr = "010001" else '0';
PORTD_Sel <= '1' when IO_Addr = "010010" else '0';
porta : AX_Port port map(
portb : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTB_Sel,
DDR_Sel => DDRB_Sel,
PIN_Sel => PINB_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
Dir => DirB,
Port_Input => Port_InB,
Port_Output => Port_OutB,
IOPort => Port_B);
portb : AX_Port port map(
portd : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTD_Sel,
DDR_Sel => DDRD_Sel,
PIN_Sel => PIND_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
Data_Out => IO_RData,
Dir => DirD,
Port_Input => Port_InD,
Port_Output => Port_OutD,
IOPort => Port_D);
 
gNoTri : if not TriState generate
with IO_Addr select
IO_RData <= SREG when "111111",
SP(7 downto 0) when "111101",
SP(15 downto 8) when "111110",
"00" & Sleep_En & "0" & ISC1 & ISC0 when "110101",
Int_En & "000000" when "111011",
TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when "111001",
TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when "111000",
UDR when "001100",
USR & "000" when "001011",
UCR(7 downto 1) & "0" when "001010",
UBRR when "001001",
"00000" & TCCR0 when "110011",
TCNT0 when "110010",
COM & "0000" & PWM when "101111",
CRBH & "00" & CRBL when "101110",
TCNT1(7 downto 0) when "101100",
OCR(7 downto 0) when "101010",
IC(7 downto 0) when "101000",
Tmp(15 downto 8) when "101101" | "101001" | "101011",
Port_InB when "010101",
DirB when "010111",
Port_OutB when "011000",
Port_InD when "010000",
DirD when "010001",
Port_OutD when "010010",
"--------" when others;
end generate;
gTri : if TriState generate
IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";
IO_RData <= SP(7 downto 0) when IO_Addr = "111101" and BigIset else "ZZZZZZZZ";
IO_RData <= SP(15 downto 8) when IO_Addr = "111110" and BigIset else "ZZZZZZZZ";
 
IO_RData <= "00" & Sleep_En & "0" & ISC1 & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";
IO_RData <= Int_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ";
IO_RData <= TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";
IO_RData <= TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";
 
IO_RData <= UDR when UDR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= USR & "000" when USR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= UCR(7 downto 1) & "0" when UCR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= UBRR when UBRR_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= "00000" & TCCR0 when TCCR0_Sel = '1' else "ZZZZZZZZ";
IO_RData <= TCNT0 when TCNT0_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= COM & "0000" & PWM when TCCR1_Sel = '1' and IO_Addr(0) = '1' else "ZZZZZZZZ";
IO_RData <= CRBH & "00" & CRBL when TCCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= TCNT1(7 downto 0) when TCNT1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= OCR(7 downto 0) when OCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= IC(7 downto 0) when ICR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= Tmp(15 downto 8) when (TCNT1_Sel = '1' or ICR1_Sel = '1' or OCR1_Sel = '1') and IO_Addr(0) = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirD when DDRD_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutD when PORTD_Sel = '1' else "ZZZZZZZZ";
end generate;
 
end;
/trunk/rtl/vhdl/AX_Reg.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
-- Version : 0221b
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
45,6 → 45,7
-- File history :
--
-- 0221 : Moved register bank to separate file
-- 0221 : Changed buses
 
library IEEE;
use IEEE.std_logic_1164.all;
54,7 → 55,7
entity AX_Reg is
generic(
BigISet : boolean;
TriState : boolean := true
TriState : boolean := false
);
port (
Clk : in std_logic;
119,48 → 120,55
Status_D(4) <= ASR(15) xor Carry_v xor Carry15_v; -- S
end generate;
 
gNoTri : if not TriState generate
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when Rd_Addr_r = "11000" and BigISet else
std_logic_vector(W_i(15 downto 8)) when Rd_Addr_r = "11001" and BigISet else
std_logic_vector(X_i(7 downto 0)) when Rd_Addr_r = "11010" and BigISet else
std_logic_vector(X_i(15 downto 8)) when Rd_Addr_r = "11011" and BigISet else
std_logic_vector(Y_i(7 downto 0)) when Rd_Addr_r = "11100" and BigISet else
std_logic_vector(Y_i(15 downto 8)) when Rd_Addr_r = "11101" and BigISet else
std_logic_vector(Z_i(7 downto 0)) when Rd_Addr_r = "11110" and BigISet else
std_logic_vector(Z_i(15 downto 8)) when Rd_Addr_r = "11111" and BigISet else
Reg_D_i;
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when Rr_Addr_r = "11000" and BigISet else
std_logic_vector(W_i(15 downto 8)) when Rr_Addr_r = "11001" and BigISet else
std_logic_vector(X_i(7 downto 0)) when Rr_Addr_r = "11010" and BigISet else
std_logic_vector(X_i(15 downto 8)) when Rr_Addr_r = "11011" and BigISet else
std_logic_vector(Y_i(7 downto 0)) when Rr_Addr_r = "11100" and BigISet else
std_logic_vector(Y_i(15 downto 8)) when Rr_Addr_r = "11101" and BigISet else
std_logic_vector(Z_i(7 downto 0)) when Rr_Addr_r = "11110" and BigISet else
std_logic_vector(Z_i(15 downto 8)) when Rr_Addr_r = "11111" and BigISet else
Reg_R_i;
gNoTri : if not TriState and BigISet generate
with Rd_Addr_r select
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when "11000",
std_logic_vector(W_i(15 downto 8)) when "11001",
std_logic_vector(X_i(7 downto 0)) when "11010",
std_logic_vector(X_i(15 downto 8)) when "11011",
std_logic_vector(Y_i(7 downto 0)) when "11100",
std_logic_vector(Y_i(15 downto 8)) when "11101",
std_logic_vector(Z_i(7 downto 0)) when "11110",
std_logic_vector(Z_i(15 downto 8)) when "11111",
Reg_D_i when others;
with Rr_Addr_r select
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when "11000",
std_logic_vector(W_i(15 downto 8)) when "11001",
std_logic_vector(X_i(7 downto 0)) when "11010",
std_logic_vector(X_i(15 downto 8)) when "11011",
std_logic_vector(Y_i(7 downto 0)) when "11100",
std_logic_vector(Y_i(15 downto 8)) when "11101",
std_logic_vector(Z_i(7 downto 0)) when "11110",
std_logic_vector(Z_i(15 downto 8)) when "11111",
Reg_R_i when others;
end generate;
 
gTri : if TriState generate
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when Rd_Addr_r = "11000" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(W_i(15 downto 8)) when Rd_Addr_r = "11001" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(7 downto 0)) when Rd_Addr_r = "11010" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(15 downto 8)) when Rd_Addr_r = "11011" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(7 downto 0)) when Rd_Addr_r = "11100" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(15 downto 8)) when Rd_Addr_r = "11101" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(7 downto 0)) when Rd_Addr_r = "11110" and BigISet else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(15 downto 8)) when Rd_Addr_r = "11111" and BigISet else "ZZZZZZZZ";
Rd_Data <= Reg_D_i when not BigISet or (Rd_Addr_r(4 downto 3) /= "11" and BigISet) else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when Rr_Addr_r = "11000" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(15 downto 8)) when Rr_Addr_r = "11001" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(7 downto 0)) when Rr_Addr_r = "11010" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(15 downto 8)) when Rr_Addr_r = "11011" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(7 downto 0)) when Rr_Addr_r = "11100" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(15 downto 8)) when Rr_Addr_r = "11101" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(7 downto 0)) when Rr_Addr_r = "11110" and BigISet else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(15 downto 8)) when Rr_Addr_r = "11111" and BigISet else "ZZZZZZZZ";
Rr_Data <= Reg_R_i when not BigISet or (Rr_Addr_r(4 downto 3) /= "11" and BigISet) else "ZZZZZZZZ";
gTri : if TriState and BigISet generate
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when Rd_Addr_r = "11000" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(W_i(15 downto 8)) when Rd_Addr_r = "11001" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(7 downto 0)) when Rd_Addr_r = "11010" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(15 downto 8)) when Rd_Addr_r = "11011" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(7 downto 0)) when Rd_Addr_r = "11100" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(15 downto 8)) when Rd_Addr_r = "11101" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(7 downto 0)) when Rd_Addr_r = "11110" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(15 downto 8)) when Rd_Addr_r = "11111" else "ZZZZZZZZ";
Rd_Data <= Reg_D_i when (Rd_Addr_r(4 downto 3) /= "11") else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when Rr_Addr_r = "11000" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(15 downto 8)) when Rr_Addr_r = "11001" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(7 downto 0)) when Rr_Addr_r = "11010" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(15 downto 8)) when Rr_Addr_r = "11011" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(7 downto 0)) when Rr_Addr_r = "11100" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(15 downto 8)) when Rr_Addr_r = "11101" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(7 downto 0)) when Rr_Addr_r = "11110" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(15 downto 8)) when Rr_Addr_r = "11111" else "ZZZZZZZZ";
Rr_Data <= Reg_R_i when (Rr_Addr_r(4 downto 3) /= "11") else "ZZZZZZZZ";
end generate;
 
gSmall : if not BigISet generate
Rd_Data <= Reg_D_i;
Rr_Data <= Reg_R_i;
end generate;
 
dpramd : AX_DPRAM
port map(
Clk => Clk,
/trunk/rtl/vhdl/AX_TC16.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
45,6 → 45,8
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
64,7 → 66,14
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
COM : out std_logic_vector(1 downto 0);
PWM : out std_logic_vector(1 downto 0);
CRBH : out std_logic_vector(1 downto 0);
CRBL : out std_logic_vector(3 downto 0);
TCNT : out std_logic_vector(15 downto 0);
IC : out std_logic_vector(15 downto 0);
OCR : out std_logic_vector(15 downto 0);
Tmp : out std_logic_vector(15 downto 0);
OC : out std_logic;
Int_TO : out std_logic;
Int_OC : out std_logic;
74,14 → 83,14
 
architecture rtl of AX_TC16 is
 
signal COM : std_logic_vector(1 downto 0);
signal PWM : std_logic_vector(1 downto 0);
signal CRBH : std_logic_vector(1 downto 0); -- ICNC, ICES
signal CRBL : std_logic_vector(3 downto 0); -- CTC, CS
signal TCNT : std_logic_vector(15 downto 0);
signal IC : std_logic_vector(15 downto 0);
signal OCR : std_logic_vector(15 downto 0);
signal TEMP : std_logic_vector(15 downto 0);
signal COM_i : std_logic_vector(1 downto 0);
signal PWM_i : std_logic_vector(1 downto 0);
signal CRBH_i : std_logic_vector(1 downto 0); -- ICNC, ICES
signal CRBL_i : std_logic_vector(3 downto 0); -- CTC, CS
signal TCNT_i : std_logic_vector(15 downto 0);
signal IC_i : std_logic_vector(15 downto 0);
signal OCR_i : std_logic_vector(15 downto 0);
signal Tmp_i : std_logic_vector(15 downto 0);
 
signal OC_i : std_logic;
signal IC_Trig : std_logic;
91,30 → 100,32
 
begin
 
COM <= COM_i;
PWM <= PWM_i;
CRBH <= CRBH_i;
CRBL <= CRBL_i;
TCNT <= TCNT_i;
IC <= IC_i;
OCR(7 downto 0) <= OCR_i(7 downto 0) when PWM_Load = '0' else Tmp_i(7 downto 0);
OCR(15 downto 8) <= OCR_i(15 downto 8);
Tmp <= Tmp_i;
OC <= OC_i;
Int_IC <= IC_Trig;
 
-- Registers and counter
Data_Out <= COM & "0000" & PWM when Rd = '1' and TCCR_Sel = '1' and A0 = '1' else "ZZZZZZZZ";
Data_Out <= CRBH & "00" & CRBL when Rd = '1' and TCCR_Sel = '1' and A0 = '0' else "ZZZZZZZZ";
Data_Out <= TCNT(7 downto 0) when Rd = '1' and TCNT_Sel = '1' and A0 = '0' else "ZZZZZZZZ";
Data_Out <= OCR(7 downto 0) when Rd = '1' and OCR_Sel = '1' and A0 = '0' and PWM_Load = '0' else "ZZZZZZZZ";
Data_Out <= Temp(7 downto 0) when Rd = '1' and OCR_Sel = '1' and A0 = '0' and PWM_Load = '1' else "ZZZZZZZZ";
Data_Out <= IC(7 downto 0) when Rd = '1' and ICR_Sel = '1' and A0 = '0' else "ZZZZZZZZ";
Data_Out <= TEMP(15 downto 8) when Rd = '1' and (TCNT_Sel = '1' or ICR_Sel = '1' or OCR_Sel = '1') and A0 = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
variable PWM_T : std_logic;
variable PWM_B : std_logic;
begin
if Reset_n = '0' then
COM <= "00";
PWM <= "00";
CRBH <= "00";
CRBL <= "0000";
TCNT <= (others => '0');
OCR <= (others => '0');
IC <= (others => '0');
Temp <= (others => '0');
COM_i <= "00";
PWM_i <= "00";
CRBH_i <= "00";
CRBL_i <= "0000";
TCNT_i <= (others => '0');
OCR_i <= (others => '0');
IC_i <= (others => '0');
Tmp_i <= (others => '0');
OC_i <= '0';
Int_TO <= '0';
Int_OC <= '0';
124,78 → 135,78
Int_TO <= '0';
Int_OC <= '0';
if Tick = '1' then
TCNT <= std_logic_vector(unsigned(TCNT) + 1);
if TCNT = "1111111111111111" then
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
if TCNT_i = "1111111111111111" then
Int_TO <= '1';
end if;
if TCNT = OCR then
if PWM = "00" then
if TCNT_i = OCR_i then
if PWM_i = "00" then
Int_OC <= '1';
if CRBL(3) = '1' then
TCNT <= (others => '0');
if CRBL_i(3) = '1' then
TCNT_i <= (others => '0');
end if;
if COM = "01" then
if COM_i = "01" then
OC_i <= not OC_i;
end if;
if COM = "10" then
if COM_i = "10" then
OC_i <= '0';
end if;
if COM = "11" then
if COM_i = "11" then
OC_i <= '1';
end if;
end if;
end if;
if PWM /= "00" then
if PWM_i /= "00" then
PWM_T := '0';
PWM_B := '0';
if PWM_Dn = '0' then
TCNT <= std_logic_vector(unsigned(TCNT) + 1);
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
else
TCNT <= std_logic_vector(unsigned(TCNT) - 1);
TCNT_i <= std_logic_vector(unsigned(TCNT_i) - 1);
end if;
if PWM = "01" and TCNT(7 downto 0) = OCR(7 downto 0) then
OC_i <= COM(0) xor PWM_Dn;
if PWM_i = "01" and TCNT_i(7 downto 0) = OCR_i(7 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM = "10" and TCNT(8 downto 0) = OCR(8 downto 0) then
OC_i <= COM(0) xor PWM_Dn;
if PWM_i = "10" and TCNT_i(8 downto 0) = OCR_i(8 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM = "11" and TCNT(9 downto 0) = OCR(9 downto 0) then
OC_i <= COM(0) xor PWM_Dn;
if PWM_i = "11" and TCNT_i(9 downto 0) = OCR_i(9 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM = "01" then
if TCNT(7 downto 0) = "11111110" and PWM_Dn = '0' then
if PWM_i = "01" then
if TCNT_i(7 downto 0) = "11111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT(7 downto 0) = "00000001" and PWM_Dn = '1' then
if TCNT_i(7 downto 0) = "00000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM = "10" then
if TCNT(8 downto 0) = "111111110" and PWM_Dn = '0' then
if PWM_i = "10" then
if TCNT_i(8 downto 0) = "111111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT(8 downto 0) = "000000001" and PWM_Dn = '1' then
if TCNT_i(8 downto 0) = "000000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM = "11" then
if TCNT(9 downto 0) = "1111111110" and PWM_Dn = '0' then
if PWM_i = "11" then
if TCNT_i(9 downto 0) = "1111111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT(9 downto 0) = "0000000001" and PWM_Dn = '1' then
if TCNT_i(9 downto 0) = "0000000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM_T = '1' then
if PWM_Load = '1' and COM(0) = '0' then
OCR <= Temp;
if PWM_Load = '1' and COM_i(0) = '0' then
OCR_i <= Tmp_i;
PWM_Load <= '0';
end if;
PWM_Dn <= '1';
end if;
if PWM_B = '1' then
if PWM_Load = '1' and COM(0) = '1' then
OCR <= Temp;
if PWM_Load = '1' and COM_i(0) = '1' then
OCR_i <= Tmp_i;
PWM_Load <= '0';
end if;
PWM_Dn <= '0';
204,36 → 215,36
end if;
end if;
if IC_Trig = '1' then
TCNT <= IC;
TCNT_i <= IC_i;
end if;
-- Register read with temp
if Rd = '1' and TCNT_Sel = '1' and A0 = '0' then
Temp(15 downto 8) <= TCNT(15 downto 8);
Tmp_i(15 downto 8) <= TCNT_i(15 downto 8);
end if;
if Rd = '1' and OCR_Sel = '1' and A0 = '0' then
Temp(15 downto 8) <= OCR(15 downto 8);
Tmp_i(15 downto 8) <= OCR_i(15 downto 8);
end if;
if Rd = '1' and ICR_Sel = '1' and A0 = '0' then
Temp(15 downto 8) <= IC(15 downto 8);
Tmp_i(15 downto 8) <= IC_i(15 downto 8);
end if;
-- Register write
if TCNT_Sel = '1' and Wr = '1' then
if A0 = '1' then
Temp(15 downto 8) <= Data_In;
Tmp_i(15 downto 8) <= Data_In;
else
TCNT(7 downto 0) <= Data_In;
TCNT(15 downto 8) <= Temp(15 downto 8);
TCNT_i(7 downto 0) <= Data_In;
TCNT_i(15 downto 8) <= Tmp_i(15 downto 8);
end if;
Int_TO <= '0';
end if;
if OCR_Sel = '1' and Wr = '1' then
if A0 = '1' then
Temp(15 downto 8) <= Data_In;
Tmp_i(15 downto 8) <= Data_In;
else
Temp(7 downto 0) <= Data_In;
if PWM = "00" then
OCR(7 downto 0) <= Data_In;
OCR(15 downto 8) <= Temp(15 downto 8);
Tmp_i(7 downto 0) <= Data_In;
if PWM_i = "00" then
OCR_i(7 downto 0) <= Data_In;
OCR_i(15 downto 8) <= Tmp_i(15 downto 8);
else
PWM_Load <= '1';
end if;
241,19 → 252,19
end if;
if ICR_Sel = '1' and Wr = '1' then
if A0 = '1' then
Temp(15 downto 8) <= Data_In;
Tmp_i(15 downto 8) <= Data_In;
else
IC(7 downto 0) <= Data_In;
IC(15 downto 8) <= Temp(15 downto 8);
IC_i(7 downto 0) <= Data_In;
IC_i(15 downto 8) <= Tmp_i(15 downto 8);
end if;
end if;
if TCCR_Sel = '1' and Wr = '1' and A0 = '1' then
COM <= Data_In(7 downto 6);
PWM <= Data_In(1 downto 0);
COM_i <= Data_In(7 downto 6);
PWM_i <= Data_In(1 downto 0);
end if;
if TCCR_Sel = '1' and Wr = '1' and A0 = '0' then
CRBH <= Data_In(7 downto 6);
CRBL <= Data_In(3 downto 0);
CRBH_i <= Data_In(7 downto 6);
CRBL_i <= Data_In(3 downto 0);
end if;
end if;
end process;
264,18 → 275,18
begin
if Clk'event and Clk = '1' then
IC_Trig <= '0';
if CRBH(1) = '1' then
if Samples = "10000" and CRBH(0) = '0' then
if CRBH_i(1) = '1' then
if Samples = "10000" and CRBH_i(0) = '0' then
IC_Trig <= '1';
end if;
if Samples = "01111" and CRBH(0) = '1' then
if Samples = "01111" and CRBH_i(0) = '1' then
IC_Trig <= '1';
end if;
else
if Samples(1 downto 0) = "10" and CRBH(0) = '0' then
if Samples(1 downto 0) = "10" and CRBH_i(0) = '0' then
IC_Trig <= '1';
end if;
if Samples(1 downto 0) = "01" and CRBH(0) = '1' then
if Samples(1 downto 0) = "01" and CRBH_i(0) = '1' then
IC_Trig <= '1';
end if;
end if;
295,7 → 306,7
T_r := "00";
elsif Clk'event and Clk='1' then
Tick <= '0';
case CRBL(2 downto 0) is
case CRBL_i(2 downto 0) is
when "000" =>
when "001" =>
Tick <= '1';
/trunk/rtl/vhdl/AX_Pack.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
-- Version : 0221b
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
163,11 → 163,13
Sleep_En : in std_logic;
Int_Trig : in std_logic_vector(15 downto 1);
Int_Acc : out std_logic_vector(15 downto 1);
SREG : out std_logic_vector(7 downto 0);
SP : out std_logic_vector(15 downto 0);
IO_Rd : out std_logic;
IO_Wr : out std_logic;
IO_Addr : out std_logic_vector(5 downto 0);
IO_RData : in std_logic_vector(7 downto 0);
IO_WData : out std_logic_vector(7 downto 0);
IO_RData : inout std_logic_vector(7 downto 0);
WDR : out std_logic
);
end component;
176,13 → 178,14
port(
Clk : in std_logic;
Reset_n : in std_logic;
PORT_Sel : std_logic;
DDR_Sel : std_logic;
PIN_Sel : std_logic;
Rd : in std_logic;
PORT_Sel : in std_logic;
DDR_Sel : in std_logic;
PIN_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Dir : out std_logic_vector(7 downto 0);
Port_Input : out std_logic_vector(7 downto 0);
Port_Output : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end component;
199,7 → 202,10
Wr : in std_logic;
TXC_Clr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
UDR : out std_logic_vector(7 downto 0);
USR : out std_logic_vector(7 downto 3);
UCR : out std_logic_vector(7 downto 0);
UBRR : out std_logic_vector(7 downto 0);
RXD : in std_logic;
TXD : out std_logic;
Int_RX : out std_logic;
215,10 → 221,10
T : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
TCCR : out std_logic_vector(2 downto 0);
TCNT : out std_logic_vector(7 downto 0);
Int : out std_logic
);
end component;
237,7 → 243,14
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
COM : out std_logic_vector(1 downto 0);
PWM : out std_logic_vector(1 downto 0);
CRBH : out std_logic_vector(1 downto 0);
CRBL : out std_logic_vector(3 downto 0);
TCNT : out std_logic_vector(15 downto 0);
IC : out std_logic_vector(15 downto 0);
OCR : out std_logic_vector(15 downto 0);
Tmp : out std_logic_vector(15 downto 0);
OC : out std_logic;
Int_TO : out std_logic;
Int_OC : out std_logic;
/trunk/rtl/vhdl/AX_TC8.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
44,6 → 44,8
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
56,10 → 58,10
T : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
TCCR : out std_logic_vector(2 downto 0);
TCNT : out std_logic_vector(7 downto 0);
Int : out std_logic
);
end AX_TC8;
66,35 → 68,36
 
architecture rtl of AX_TC8 is
 
signal TCCR : std_logic_vector(2 downto 0); -- Control Register
signal TCNT : std_logic_vector(7 downto 0); -- Timer/Counter
signal TCCR_i : std_logic_vector(2 downto 0); -- Control Register
signal TCNT_i : std_logic_vector(7 downto 0); -- Timer/Counter
 
signal Tick : std_logic;
 
begin
 
TCCR <= TCCR_i;
TCNT <= TCNT_i;
 
-- Registers and counter
Data_Out <= "00000" & TCCR when Rd = '1' and TCCR_Sel = '1' else "ZZZZZZZZ";
Data_Out <= TCNT when Rd = '1' and TCNT_Sel = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
TCCR <= "000";
TCNT <= "00000000";
TCCR_i<= "000";
TCNT_i <= "00000000";
Int <= '0';
elsif Clk'event and Clk = '1' then
if TCCR_Sel = '1' and Wr = '1' then
TCCR <= Data_In(2 downto 0);
TCCR_i <= Data_In(2 downto 0);
end if;
Int <= '0';
if Tick = '1' then
TCNT <= std_logic_vector(unsigned(TCNT) + 1);
if TCNT = "11111111" then
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
if TCNT_i = "11111111" then
Int <= '1';
end if;
end if;
if TCNT_Sel = '1' and Wr = '1' then
TCNT <= Data_In;
TCNT_i <= Data_In;
Int <= '0';
end if;
end if;
111,7 → 114,7
T_r := "00";
elsif Clk'event and Clk='1' then
Tick <= '0';
case TCCR is
case TCCR_i is
when "000" =>
when "001" =>
Tick <= '1';
/trunk/rtl/vhdl/AX_Port.vhd
1,7 → 1,7
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
41,10 → 41,12
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- No pull-up (for obvious reasons)
-- No pull-up
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
53,13 → 55,14
port(
Clk : in std_logic;
Reset_n : in std_logic;
PORT_Sel : std_logic;
DDR_Sel : std_logic;
PIN_Sel : std_logic;
Rd : in std_logic;
PORT_Sel : in std_logic;
DDR_Sel : in std_logic;
PIN_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Dir : out std_logic_vector(7 downto 0);
Port_Input : out std_logic_vector(7 downto 0);
Port_Output : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end AX_Port;
66,24 → 69,22
 
architecture rtl of AX_Port is
 
signal Dir : std_logic_vector(7 downto 0);
signal Port_Output : std_logic_vector(7 downto 0);
signal Port_Input : std_logic_vector(7 downto 0);
signal Dir_i : std_logic_vector(7 downto 0);
signal Port_Output_i : std_logic_vector(7 downto 0);
 
begin
 
IOPort(0) <= Port_Output(0) when Dir(0) = '1' else 'Z';
IOPort(1) <= Port_Output(1) when Dir(1) = '1' else 'Z';
IOPort(2) <= Port_Output(2) when Dir(2) = '1' else 'Z';
IOPort(3) <= Port_Output(3) when Dir(3) = '1' else 'Z';
IOPort(4) <= Port_Output(4) when Dir(4) = '1' else 'Z';
IOPort(5) <= Port_Output(5) when Dir(5) = '1' else 'Z';
IOPort(6) <= Port_Output(6) when Dir(6) = '1' else 'Z';
IOPort(7) <= Port_Output(7) when Dir(7) = '1' else 'Z';
Dir <= Dir_i;
Port_Output <= Port_Output_i;
 
Data_Out <= Port_Input when PIN_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
Data_Out <= Dir when DDR_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
Data_Out <= Port_Output when PORT_Sel = '1' and Rd = '1' else "ZZZZZZZZ";
IOPort(0) <= Port_Output_i(0) when Dir_i(0) = '1' else 'Z';
IOPort(1) <= Port_Output_i(1) when Dir_i(1) = '1' else 'Z';
IOPort(2) <= Port_Output_i(2) when Dir_i(2) = '1' else 'Z';
IOPort(3) <= Port_Output_i(3) when Dir_i(3) = '1' else 'Z';
IOPort(4) <= Port_Output_i(4) when Dir_i(4) = '1' else 'Z';
IOPort(5) <= Port_Output_i(5) when Dir_i(5) = '1' else 'Z';
IOPort(6) <= Port_Output_i(6) when Dir_i(6) = '1' else 'Z';
IOPort(7) <= Port_Output_i(7) when Dir_i(7) = '1' else 'Z';
 
process (Clk)
begin
95,14 → 96,14
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Dir <= "00000000";
Port_Output <= "00000000";
Dir_i <= "00000000";
Port_Output_i <= "00000000";
elsif Clk'event and Clk = '1' then
if DDR_Sel = '1' and Wr = '1' then
Dir <= Data_In;
Dir_i <= Data_In;
end if;
if PORT_Sel = '1' and Wr = '1' then
Port_Output <= Data_In;
Port_Output_i <= Data_In;
end if;
end if;
end process;

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