URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 23 to Rev 24
- ↔ Reverse comparison
Rev 23 → Rev 24
/ft816float/trunk/rtl/verilog/fpAddsub.v
1,7 → 1,7
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo |
// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
208,12 → 208,14
wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob; |
wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa; |
wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb; |
wire xoinf = &xo; |
|
always @* |
casez({aInf1&bInf1,aNan1,bNan1}) |
3'b1??: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add |
3'b01?: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}}; |
3'b001: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}}; |
casez({aInf1&bInf1,aNan1,bNan1,xoinf}) |
4'b1???: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add |
4'b01??: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}}; |
4'b001?: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}}; |
4'b0001: mo1 = 1'd0; |
default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits |
endcase |
|