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URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 23 to Rev 24
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  •

Rev 23 → Rev 24

/ion/trunk/src/hello/makefile
2,6 → 2,8
# Get common makefile stuff (toolchain & system config)
include ../common/makefile
# We'll run the simulation for 2000 clock cycles
SIM_LENGTH = 2000
clean:
-$(RM) *.o *.obj *.map *.lst *.hex *.exe *.axf *.code *.data
26,9 → 28,11
# Create VHDL file for simulation test bench
hello_sim: hello.code hello.data
$(TO_VHDL) $(VHDL_FLAGS) --code hello.code --data hello.data \
-v $(SRC_DIR)/mips_tb1_template.vhdl -o $(TB_DIR)/mips_tb1.vhdl -e mips_tb1
-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb1_template.vhdl \
-o $(TB_DIR)/mips_tb1.vhdl -e mips_tb1
 
# Create VHDL file for hardware demo
hello_demo: hello.code hello.data
$(TO_VHDL) $(VHDL_FLAGS) --code hello.code --data hello.data \
-v $(SRC_DIR)/mips_mpu_template.vhdl -o $(DEMO_DIR)/mips_mpu.vhdl -e mips_mpu
-v $(SRC_DIR)/mips_mpu_template.vhdl
-o $(DEMO_DIR)/mips_mpu.vhdl -e mips_mpu
/ion/trunk/src/mips_tb0_template.vhdl
43,8 → 43,9
-- WARNING: slite does not simulate this. The logs may be different when > 0.0!
constant SIMULATED_UART_TX_TIME : time := 0.0 us;
 
-- Simulation length in clock cycles -- 2000 is enough for 'hello' sample
constant SIMULATION_LENGTH : integer := 2000;
-- Simulation length in clock cycles
-- 2000 is enough for 'hello' sample, 22000 enough for 10 digits of pi
constant SIMULATION_LENGTH : integer := @sim_len@;
 
--------------------------------------------------------------------------------
92,7 → 93,18
-- Log file
file l_file: TEXT open write_mode is "hw_sim_log.txt";
 
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
 
-- Maximum line size of for console output log. Lines longer than this will be
-- truncated.
constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
 
-- Console log line buffer
signal con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
signal con_line_ix : integer := 1;
 
 
--------------------------------------------------------------------------------
 
constant MEM_SIZE : integer := @code_table_size@;
153,12 → 165,20
 
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
 
-- Flush console output to log console file (in case the end of the
-- simulation caugh an unterminated line in the buffer)
if con_line_ix > 1 then
write(l, con_line_buf(1 to con_line_ix));
writeline(con_file, l);
end if;
 
print("TB0 finished");
done <= '1';
wait;
190,8 → 210,6
process(clk)
variable i : integer;
variable uart_data : integer;
variable s: string(1 to 100);
variable si : integer := 1;
begin
if clk'event and clk='1' then
if reset='1' then
233,18 → 251,18
-- and editing
if uart_data = 10 then
-- CR received: print output string and clear it
print(s);
si := 1;
for i in 1 to s'high loop
s(i) := ' ';
print(con_file, con_line_buf(1 to con_line_ix));
con_line_ix <= 1;
for i in 1 to con_line_buf'high loop
con_line_buf(i) <= ' ';
end loop;
elsif uart_data = 13 then
-- ignore LF
else
-- append char to output string
if si < s'high then
s(si) := character'val(uart_data);
si := si + 1;
if con_line_ix < con_line_buf'high then
con_line_buf(con_line_ix) <= character'val(uart_data);
con_line_ix <= con_line_ix + 1;
end if;
end if;
else
/ion/trunk/src/bin2hdl.py
21,6 → 21,7
print "data_size <number> Size of data memory in words (decimal)"
print ""
print "Additionally, any of these arguments can be given:"
print "{s|sim_len} <number> Length of simulation in clock cycles"
print "{d|data} <filename> Data binary image file name"
print "{h|help} Display some help text and exit"
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
35,6 → 36,7
print "Other template tags are replaced as follows:"
print "@entity_name@ : Name of entity in target vhdl file"
print "@arch_name@ : Name of architecture in target vhdl file"
print "@sim_len@ : Length of simulation in clock cycles"
print "@code_table_size@ : Size of code RAM block, in words"
print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
print "@data_table_size@ : Size of data RAM block, in words"
91,13 → 93,15
code_table_size = -1 # size of VHDL table
data_table_size = -1 # size of VHDL table
bin_words = 0 # size of binary file in 32-bit words
simulation_length = 22000 # length of logic simulation in clock cycles
#
 
try:
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:",
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:",
["help", "code=", "data=", "vhdl=", "architecture=",
"entity=", "output=", "indent=", "code_size=", "data_size="])
"entity=", "output=", "indent=", "sim_len=",
"code_size=", "data_size="])
except getopt.GetoptError:
usage()
sys.exit(2)
122,6 → 126,8
entity_name = arg
elif opt in ("-i", "--indent"):
indent = int(arg)
elif opt in ("-s", "--sim_len"):
simulation_length = int(arg)
elif opt == "--code_size":
code_table_size = int(arg)
elif opt == "--data_size":
188,10 → 194,12
keywords = ["@code0@","@code1@","@code2@","@code3@",
"@data0@","@data1@","@data2@","@data3@",
"@entity_name@","@arch_name@",
"@sim_len@",
"@code_table_size@","@code_addr_size@",
"@data_table_size@","@data_addr_size@"];
replacement = vhdl_code_strings + vhdl_data_strings + \
[entity_name, arch_name,
str(simulation_length),
str(code_table_size),
str(int(math.floor(math.log(code_table_size,2)))),
str(data_table_size),
/ion/trunk/src/opcodes/makefile
2,6 → 2,8
# Get common makefile stuff (toolchain & system config)
include ../common/makefile
 
# We'll run the simulation for 2000 clock cycles
SIM_LENGTH = 2000
 
clean:
-$(RM) -f *.o *.obj *.map *.lst *.hex \
18,5 → 20,6
# Create VHDL file for simulation test bench
opcodes_sim: opcodes
$(TO_VHDL) $(VHDL_FLAGS) --code opcodes.bin \
-v $(SRC_DIR)\\mips_tb0_template.vhdl -o $(TB_DIR)\\mips_tb1.vhdl -e mips_tb1
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb0_template.vhdl \
-o $(TB_DIR)\\mips_tb1.vhdl -e mips_tb1
 

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