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    from Rev 23 to Rev 24
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Rev 23 → Rev 24

/trunk/vhdl/mips_cpu.vhd
124,6 → 124,7
 
component reg_bank
port(clk : in std_logic;
reset_in : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
280,6 → 281,7
 
u4_reg_bank: reg_bank port map (
clk => clk,
reset_in => reset_reg,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
/trunk/vhdl/reg_bank.vhd
17,6 → 17,7
 
entity reg_bank is
port(clk : in std_logic;
reset_in : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
79,10 → 80,10
end if;
 
if rising_edge(clk) then
if rd_index = "101100" then
if reset_in = '1' or rd_index = "101110" then --reg_epc CP0 14
reg_status <= '0'; --disable interrupts
elsif rd_index = "101100" then
reg_status <= reg_dest_new(0);
elsif rd_index = "101110" then --reg_epc CP0 14
reg_status <= '0'; --disable interrupts
end if;
end if;
 

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