Subversion Repositories openmsp430

/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom File deleted

openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream =================================================================== --- openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream (revision 23) +++ openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream (nonexistent) @@ -1,47 +0,0 @@ -#!/bin/tcsh - -# Cleanup -rm -rf ./WORK -mkdir WORK -cd ./WORK - -# Create links for RAM & ROM ngc files -ln -s ../../../rtl/verilog/coregen/ram_8x512_hi.ngc . -ln -s ../../../rtl/verilog/coregen/ram_8x512_lo.ngc . -ln -s ../../../rtl/verilog/coregen/rom_8x2k_hi.ngc . -ln -s ../../../rtl/verilog/coregen/rom_8x2k_lo.ngc . - -# Create links for the timescale and the openMSP430 configuration -ln -s ../../../rtl/verilog/timescale.v . -ln -s ../../../rtl/verilog/openMSP430_defines.v . - -# Create link to the Xilinx constraints file -ln -s ../openMSP430_fpga_top.ucf . - - -# XFLOW -#--------------- - -xflow -p 3S200FT256-4 -implement high_effort.opt \ - -config bitgen.opt \ - -synth xst_verilog.opt \ - ../openMSP430_fpga_top.v - -# MANUAL FLOW -#--------------- - -#xst -intstyle xflow -ifn ../openMSP430_fpga.xst - -#ngdbuild -p xc3s200-4-ft256 -uc ../openMSP430_fpga.ucf openMSP430_fpga - -#map -k 6 -detail -pr b openMSP430_fpga - -#par -ol med -w openMSP430_fpga.ncd openMSP430_fpga - -#trce -e -o openMSP430_fpga_err.twr openMSP430_fpga -#trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga - -#bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga - - -cd ..

openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh =================================================================== --- openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh (nonexistent) +++ openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh (revision 24) @@ -0,0 +1,44 @@ +#!/bin/sh +############################################################################### +# # +# Xilinx RAM update script for LINUX # +# # +############################################################################### + +############################################################################### +# Parameter Check # +############################################################################### +EXPECTED_ARGS=1 +if [ $# -ne $EXPECTED_ARGS ]; then + echo "ERROR : wrong number of arguments" + echo "USAGE : load_rom " + echo "Example : load_rom leds" + echo "Available tests:" + ls ../../software/ + exit 1 +fi + +############################################################################### +# Check if the required files exist # +############################################################################### +softdir=../../software/$1; +elffile=../../software/$1/$1.elf; + +if [ ! -e $softdir ]; then + echo "Software directory doesn't exist: $softdir" + exit 1 +fi + +############################################################################### +# Update FPGA Bitstream # +############################################################################### + + +rm -f ./WORK/$1.elf +rm -f ./WORK/$1.bit + +cp -f $elffile ./WORK/ + +cd ./WORK +data2mem -bm ../memory.bmm -bd $1.elf -bt openMSP430_fpga_top.bit -o b $1.bit +cd ../

openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh =================================================================== --- openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh (nonexistent) +++ openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh (revision 24) @@ -0,0 +1,52 @@ +#!/bin/tcsh +###################################################### +# # +# Xilinx Synthesis, Place & Route script for LINUX # +# # +###################################################### + +# Cleanup +rm -rf ./WORK +mkdir WORK +cd ./WORK + +# Create links for RAM & ROM ngc files +ln -s ../../../rtl/verilog/coregen/ram_8x512_hi.ngc . +ln -s ../../../rtl/verilog/coregen/ram_8x512_lo.ngc . +ln -s ../../../rtl/verilog/coregen/rom_8x2k_hi.ngc . +ln -s ../../../rtl/verilog/coregen/rom_8x2k_lo.ngc . + +# Create links for the timescale and the openMSP430 configuration +ln -s ../../../rtl/verilog/timescale.v . +ln -s ../../../rtl/verilog/openMSP430_defines.v . + +# Create link to the Xilinx constraints file +ln -s ../openMSP430_fpga_top.ucf . + + +# XFLOW +#--------------- + +xflow -p 3S200FT256-4 -implement high_effort.opt \ + -config bitgen.opt \ + -synth xst_verilog.opt \ + ../openMSP430_fpga_top.v + +# MANUAL FLOW +#--------------- + +#xst -intstyle xflow -ifn ../openMSP430_fpga.xst + +#ngdbuild -p xc3s200-4-ft256 -uc ../openMSP430_fpga.ucf openMSP430_fpga + +#map -k 6 -detail -pr b openMSP430_fpga + +#par -ol med -w openMSP430_fpga.ncd openMSP430_fpga + +#trce -e -o openMSP430_fpga_err.twr openMSP430_fpga +#trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga + +#bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga + + +cd ..

openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property