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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
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/trunk/rtl/verilog/T6507LP_FSM.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2009/03/06 18:57:12 creep |
// Updated file header standard. |
// |
// Revision 1.3 2009/03/06 18:52:23 creep |
// *** empty log message *** |
// |
68,6 → 71,8
parameter WRITE_EFFECTIVE = 3'b110; |
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module t6507lp_fsm(clk_in, n_rst_in, data, address); |
input clk_in; |
input n_rst_in; |
74,31 → 79,62
inout [7:0] data; |
output [12:0] address; |
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reg [12:0] PC; |
reg [7:0] SP; |
reg [12:0] pc; |
reg [7:0] sp; |
reg [7:0] ir; |
reg [7:0] templow; |
reg [7:0] temphigh; |
reg [7:0] tempdata; |
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reg [3:0] state; |
reg [3:0] state; // not sure if this will be 4 bits wide |
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always @ (posedge clk_in) begin |
if (n_rst_in == 1'b0) begin |
// TODO: all the reset stuff |
pc <= 8'h00; // TODO: this is written somewhere. something about a reset vector. must be checked. |
sp <= 8'h00; // TODO: the default is not 0. maybe $0100 or something like that. must be checked. |
ir <= 8'h00; |
templow <= 8'h00; |
temphigh <= 8'h00; |
tempdata <= 8'h00; |
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state <= FETCH_OP; |
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end |
else begin |
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PC <= PC + 1'b1; |
pc <= pc + 1'b1; |
state <= next_state; |
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case (state) |
FETCH_OP: begin // TODO: bus controller enables memory or cpu enables it? |
address = PC; |
FETCH_OP: begin // this state is the simplest one. whenever a instruction is done you must fetch the next op. |
// TODO: bus controller enables memory or cpu enables it? |
address = pc; |
ir <= data; |
end |
FETCH_1: begin |
address = PC; |
address = pc; |
templow <= data; |
end |
FETCH_HIGH_TO_PC: begin |
address = PC; |
address = pc; |
pc <= {data[4:0],templow}; |
end |
FETCH_HIGH_TO_TEMP: begin |
temphigh <= data; |
end |
READ_EFFECTIVE: begin |
address = {temphigh[4:0],templow}; |
tempdata <= data; |
end |
DO_OPERATION: begin |
address = 1'bZ; // TODO: the spec says to write the value again... this means more power used. not sure it is necessay. |
// TODO: connect alu here and perform the desired operation |
end |
WRITE_EFFECTIVE: begin |
address = {temphigh[4:0],templow}; |
data = alu.output; |
end |
endcase |
end |
end |