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/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG.vhd
0,0 → 1,205
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: It is the top most module which interfaces with the system and
-- the memory.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG is
port(
cntrl0_ddr_dq : inout std_logic_vector(31 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(3 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
clk_100_top : in std_logic;
clk_200_top : in std_logic;
init_done : out std_logic;
sys_reset_in_n : in std_logic;
cntrl0_clk_tb : out std_logic;
cntrl0_reset_tb : out std_logic;
cntrl0_wdf_almost_full : out std_logic;
cntrl0_af_almost_full : out std_logic;
cntrl0_read_data_valid : out std_logic;
cntrl0_app_wdf_wren : in std_logic;
cntrl0_app_af_wren : in std_logic;
cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);
cntrl0_app_af_addr : in std_logic_vector(35 downto 0);
cntrl0_app_wdf_data : in std_logic_vector(63 downto 0);
cntrl0_read_data_fifo_out : out std_logic_vector(63 downto 0);
cntrl0_app_mask_data : in std_logic_vector(7 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(3 downto 0);
cntrl0_ddr_ck : out std_logic_vector(1 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(1 downto 0)
);
end MIG;
 
architecture arc_mem_interface_top of MIG is
 
component MIG_top_0 port (
ddr_dq : inout std_logic_vector(31 downto 0);
ddr_a : out std_logic_vector(12 downto 0);
ddr_ba : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic;
ddr_cs_n : out std_logic;
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_dm : out std_logic_vector(3 downto 0);
init_done : out std_logic;
clk_tb : out std_logic;
reset_tb : out std_logic;
wdf_almost_full : out std_logic;
af_almost_full : out std_logic;
read_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
burst_length_div2 : out std_logic_vector(2 downto 0);
app_af_addr : in std_logic_vector(35 downto 0);
app_wdf_data : in std_logic_vector(63 downto 0);
read_data_fifo_out : out std_logic_vector(63 downto 0);
app_mask_data : in std_logic_vector(7 downto 0);
ddr_dqs : inout std_logic_vector(3 downto 0);
ddr_ck : out std_logic_vector(1 downto 0);
ddr_ck_n : out std_logic_vector(1 downto 0);
clk_0 : in std_logic;
clk_90 : in std_logic;
sys_rst : in std_logic;
sys_rst90 : in std_logic;
idelay_ctrl_rdy : in std_logic
 
);
end component;
 
component MIG_infrastructure
port(
idelay_ctrl_rdy : in std_logic;
clk : out std_logic;
clk90 : out std_logic;
clk200 : out std_logic;
sys_rst : out std_logic;
sys_rst90 : out std_logic;
sys_rst_r1 : out std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
clk_100_top : in std_logic;
clk_200_top : in std_logic;
sys_reset_in_n : in std_logic
);
end component;
 
component MIG_idelay_ctrl
port(
clk200 : in std_logic;
reset : in std_logic;
rdy_status : out std_logic
);
end component;
 
 
 
signal clk_0 : std_logic;
signal clk_90 : std_logic;
signal clk_200 : std_logic;
signal sys_rst : std_logic;
signal sys_rst90 : std_logic;
signal idelay_ctrl_rdy : std_logic;
signal sys_rst_r1 : std_logic;
 
attribute syn_useioff : boolean ;
attribute syn_useioff of arc_mem_interface_top : architecture is true;
 
begin
 
top_00 : MIG_top_0 port map (
ddr_dq => cntrl0_ddr_dq,
ddr_a => cntrl0_ddr_a,
ddr_ba => cntrl0_ddr_ba,
ddr_cke => cntrl0_ddr_cke,
ddr_cs_n => cntrl0_ddr_cs_n,
ddr_ras_n => cntrl0_ddr_ras_n,
ddr_cas_n => cntrl0_ddr_cas_n,
ddr_we_n => cntrl0_ddr_we_n,
ddr_dm => cntrl0_ddr_dm,
init_done => init_done,
clk_tb => cntrl0_clk_tb,
reset_tb => cntrl0_reset_tb,
wdf_almost_full => cntrl0_wdf_almost_full,
af_almost_full => cntrl0_af_almost_full,
read_data_valid => cntrl0_read_data_valid,
app_wdf_wren => cntrl0_app_wdf_wren,
app_af_wren => cntrl0_app_af_wren,
burst_length_div2 => cntrl0_burst_length_div2,
app_af_addr => cntrl0_app_af_addr,
app_wdf_data => cntrl0_app_wdf_data,
read_data_fifo_out => cntrl0_read_data_fifo_out,
app_mask_data => cntrl0_app_mask_data,
ddr_dqs => cntrl0_ddr_dqs,
ddr_ck => cntrl0_ddr_ck,
ddr_ck_n => cntrl0_ddr_ck_n,
clk_0 => clk_0,
clk_90 => clk_90,
idelay_ctrl_rdy => idelay_ctrl_rdy,
sys_rst => sys_rst,
sys_rst90 => sys_rst90
);
 
 
infrastructure0 : MIG_infrastructure
port map (
clk => clk_0,
clk90 => clk_90,
clk200 => clk_200,
idelay_ctrl_rdy => idelay_ctrl_rdy,
sys_rst => sys_rst,
sys_rst90 => sys_rst90,
sys_rst_r1 => sys_rst_r1,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
clk200_p => clk200_p,
clk200_n => clk200_n,
clk_100_top => clk_100_top,
clk_200_top => clk_200_top,
sys_reset_in_n => sys_reset_in_n
);
 
idelay_ctrl0 : MIG_idelay_ctrl
port map (
clk200 => clk_200,
reset => sys_rst_r1,
rdy_status => idelay_ctrl_rdy
);
 
end arc_mem_interface_top;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_data_path_0/MIG_data_path_0.vhd
0,0 → 1,138
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_data_path_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the tap logic and the data write modules. Gives
-- the rise and the fall data and the calibration information for
-- IDELAY elements.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_data_path_0 is
port(
clk : in std_logic;
clk90 : in std_logic;
reset0 : in std_logic;
reset90 : in std_logic;
idelay_ctrl_rdy : in std_logic;
dummy_write_pattern : in std_logic;
ctrl_dummyread_start : in std_logic;
wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
ctrl_wren : in std_logic;
ctrl_dqs_rst : in std_logic;
ctrl_dqs_en : in std_logic;
dqs_delayed : in std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
data_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
sel_done : out std_logic;
dqs_rst : out std_logic;
dqs_en : out std_logic;
wr_en : out std_logic;
wr_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
);
end MIG_data_path_0;
 
architecture arch of MIG_data_path_0 is
 
component MIG_data_write_0
port(
clk : in std_logic;
clk90 : in std_logic;
reset90 : in std_logic;
wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
dummy_write_pattern : in std_logic;
ctrl_wren : in std_logic;
ctrl_dqs_rst : in std_logic;
ctrl_dqs_en : in std_logic;
dqs_rst : out std_logic;
dqs_en : out std_logic;
wr_en : out std_logic;
wr_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
);
end component;
 
component MIG_tap_logic_0
port(
clk : in std_logic;
reset0 : in std_logic;
idelay_ctrl_rdy : in std_logic;
ctrl_dummyread_start : in std_logic;
dqs_delayed : in std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
data_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
sel_done : out std_logic
);
end component;
 
begin
 
data_write_10: MIG_data_write_0
port map (
clk => clk,
clk90 => clk90,
reset90 => reset90,
wdf_data => wdf_data,
mask_data => mask_data,
dummy_write_pattern => dummy_write_pattern,
ctrl_wren => ctrl_wren,
ctrl_dqs_rst => ctrl_dqs_rst,
ctrl_dqs_en => ctrl_dqs_en,
dqs_rst => dqs_rst,
dqs_en => dqs_en,
wr_en => wr_en,
wr_data_rise => wr_data_rise,
wr_data_fall => wr_data_fall,
mask_data_rise => mask_data_rise,
mask_data_fall => mask_data_fall
);
 
tap_logic_00: MIG_tap_logic_0
port map (
clk => clk,
reset0 => reset0,
idelay_ctrl_rdy => idelay_ctrl_rdy,
ctrl_dummyread_start => ctrl_dummyread_start,
dqs_delayed => dqs_delayed,
data_idelay_inc => data_idelay_inc,
data_idelay_ce => data_idelay_ce,
data_idelay_rst => data_idelay_rst,
dqs_idelay_inc => dqs_idelay_inc,
dqs_idelay_ce => dqs_idelay_ce,
dqs_idelay_rst => dqs_idelay_rst,
sel_done => sel_done
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_data_path_0/MIG_tap_logic/MIG_data_tap_inc.vhd
0,0 → 1,141
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_data_tap_inc.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: The tap logic for calibration of the memory data with respect
-- to FPGA clock is provided here. According to the edge detection
-- or not the taps in the IDELAY element of the Virtex4 devices
-- are either increased or decreased.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_data_tap_inc is
port(
clk : in std_logic;
reset : in std_logic;
data_dlyinc : out std_logic;
data_dlyce : out std_logic;
data_dlyrst : out std_logic;
data_tap_sel_done : out std_logic;
dqs_sel_done : in std_logic;
valid_data_tap_count : in std_logic;
data_tap_count : in std_logic_vector(5 downto 0)
);
end MIG_data_tap_inc;
 
architecture arch of MIG_data_tap_inc is
 
signal data_dlyinc_clk0 : std_logic;
signal data_dlyce_clk0 : std_logic;
signal data_dlyrst_clk0 : std_logic;
signal data_tap_inc_counter : std_logic_vector(5 downto 0) := "000000";
signal data_tap_sel_clk : std_logic;
signal data_tap_sel_r1 : std_logic;
signal dqs_sel_done_r : std_logic;
signal valid_data_tap_count_r : std_logic;
signal rst_r : std_logic;
 
begin
 
data_tap_sel_done <= data_tap_sel_r1;
data_dlyinc <= data_dlyinc_clk0;
data_dlyce <= data_dlyce_clk0;
data_dlyrst <= data_dlyrst_clk0;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
rst_r <= reset;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
data_tap_sel_clk <= '0';
elsif(data_tap_inc_counter = "000001") then
data_tap_sel_clk <= '1';
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
data_tap_sel_r1 <= '0';
else
data_tap_sel_r1 <= data_tap_sel_clk;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
dqs_sel_done_r <= '0';
elsif(dqs_sel_done = '1') then
dqs_sel_done_r <= '1';
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
valid_data_tap_count_r <= '0';
else
valid_data_tap_count_r <= valid_data_tap_count;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1' or dqs_sel_done_r = '0') then
data_dlyinc_clk0 <= '0';
data_dlyce_clk0 <= '0';
data_dlyrst_clk0 <= '1';
data_tap_inc_counter <= "000000";
elsif(valid_data_tap_count_r = '1') then
data_dlyinc_clk0 <= '0';
data_dlyce_clk0 <= '0';
data_dlyrst_clk0 <= '0';
data_tap_inc_counter <= data_tap_count;
elsif(data_tap_inc_counter /= "000000") then -- Data IDELAY incremented
data_dlyinc_clk0 <= '1';
data_dlyce_clk0 <= '1';
data_dlyrst_clk0 <= '0';
data_tap_inc_counter <= data_tap_inc_counter - '1';
else -- Data IDELAY no change mode
data_dlyinc_clk0 <= '0';
data_dlyce_clk0 <= '0';
data_dlyrst_clk0 <= '0';
data_tap_inc_counter <= "000000";
end if;
end if;
end process;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_data_path_0/MIG_tap_logic/MIG_tap_ctrl_0.vhd
0,0 → 1,473
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_tap_ctrl.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: The tap control logic which claculates the relation between the
-- FPGA clock and the dqs from memory. It delays the dqs so as to
-- detect the edges of the dqs and then calculates the mid point
-- so that the data can be registered properly.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_tap_ctrl is
port(
clk : in std_logic;
reset : in std_logic;
rdy_status : in std_logic;
dqs : in std_logic;
ctrl_dummyread_start : in std_logic;
dlyinc : out std_logic;
dlyce : out std_logic;
dlyrst : out std_logic;
sel_done : out std_logic;
valid_data_tap_count : out std_logic;
data_tap_count : out std_logic_vector(5 downto 0)
);
end MIG_tap_ctrl;
 
architecture arch of MIG_tap_ctrl is
 
signal prev_dqs_level : std_logic;
signal dly_inc : std_logic;
signal dly_ce : std_logic;
signal dly_rst : std_logic;
signal transition : std_logic_vector(1 downto 0);
signal first_edge : std_logic;
signal second_edge : std_logic;
signal second_edge_r1 : std_logic;
signal second_edge_r2 : std_logic;
signal second_edge_r3 : std_logic;
signal transition_rst : std_logic;
signal sel_complete : std_logic;
signal tap_counter : std_logic_vector(5 downto 0);
signal first_edge_tap_count : std_logic_vector(5 downto 0);
signal second_edge_tap_count : std_logic_vector(5 downto 0);
signal pulse_width_tap_count : std_logic_vector(5 downto 0);
signal data_bit_tap_count : std_logic_vector(5 downto 0);
signal state : std_logic_vector(2 downto 0);
signal idelay_rst_idle : std_logic;
signal idelay_rst_idle_r1 : std_logic;
signal idelay_rst_idle_r2 : std_logic;
signal idelay_rst_idle_r3 : std_logic;
signal idelay_rst_idle_r4 : std_logic;
signal idelay_rst_idle_r5 : std_logic;
signal idelay_rst_idle_r6 : std_logic;
signal idelay_inc_idle : std_logic;
signal idelay_inc_idle_r1 : std_logic;
signal idelay_inc_idle_r2 : std_logic;
signal idelay_inc_idle_r3 : std_logic;
signal idelay_inc_idle_r4 : std_logic;
signal idelay_inc_idle_r5 : std_logic;
signal idelay_inc_idle_r6 : std_logic;
signal detect_edge_idle : std_logic;
signal detect_edge_idle_r1 : std_logic;
signal detect_edge_idle_r2 : std_logic;
signal detect_edge_idle_r3 : std_logic;
signal detect_edge_idle_r4 : std_logic;
signal detect_edge_idle_r5 : std_logic;
signal detect_edge_idle_r6 : std_logic;
signal flag : std_logic_vector(3 downto 0);
signal dly_after_first_cnt : std_logic_vector(3 downto 0);
signal pulse_center_tap_count : std_logic_vector(5 downto 0);
signal valid_data_count : std_logic;
signal data_count_valid : std_logic;
signal dly_after_first : std_logic_vector(3 downto 0);
signal curr_dqs_level : std_logic;
signal delay_sel_done : std_logic;
signal reset_int : std_logic;
signal rst_r : std_logic;
 
constant IDELAY_RST : std_logic_vector(2 downto 0) := "000";
constant IDLE : std_logic_vector(2 downto 0) := "001";
constant IDELAY_INC : std_logic_vector(2 downto 0) := "010";
constant DETECT_EDGE : std_logic_vector(2 downto 0) := "011";
 
attribute syn_preserve : boolean;
attribute syn_preserve of pulse_width_tap_count : signal is true ;
 
begin
 
process(clk)
begin
if clk'event and clk = '1' then
rst_r <= reset;
end if;
end process;
 
dlyinc <= dly_inc;
dlyce <= dly_ce;
dlyrst <= dly_rst;
sel_done <= sel_complete;
valid_data_tap_count <= valid_data_count;
data_tap_count <= data_bit_tap_count;
 
data_count_valid <= '1' when (second_edge_r3 = '1') or (tap_counter = "111111") else '0';
reset_int <= not(rdy_status) or rst_r;
 
delay_sel_done <= '1' when ((second_edge = '1') or (tap_counter = "111111")) else
'0' when (ctrl_dummyread_start = '0') else
sel_complete;
 
dly_after_first <= "1001" when ((transition = "01") and (first_edge = '0')) else
(dly_after_first_cnt - '1') when ((dly_after_first_cnt /= "0000")
and (dly_inc = '1')) else
dly_after_first_cnt;
 
curr_dqs_level <= dqs;
 
-- Shift registers for controls
process(clk)
begin
if clk'event and clk = '1' then
if reset_int = '1' then
second_edge_r1 <= '0';
second_edge_r2 <= '0';
second_edge_r3 <= '0';
idelay_rst_idle_r1 <= '0';
idelay_rst_idle_r2 <= '0';
idelay_rst_idle_r3 <= '0';
idelay_rst_idle_r4 <= '0';
idelay_rst_idle_r5 <= '0';
idelay_rst_idle_r6 <= '0';
idelay_inc_idle_r1 <= '0';
idelay_inc_idle_r2 <= '0';
idelay_inc_idle_r3 <= '0';
idelay_inc_idle_r4 <= '0';
idelay_inc_idle_r5 <= '0';
idelay_inc_idle_r6 <= '0';
detect_edge_idle_r1 <= '0';
detect_edge_idle_r2 <= '0';
detect_edge_idle_r3 <= '0';
detect_edge_idle_r4 <= '0';
detect_edge_idle_r5 <= '0';
detect_edge_idle_r6 <= '0';
valid_data_count <= '0';
else
second_edge_r1 <= second_edge;
second_edge_r2 <= second_edge_r1;
second_edge_r3 <= second_edge_r2;
idelay_rst_idle_r1 <= idelay_rst_idle;
idelay_rst_idle_r2 <= idelay_rst_idle_r1;
idelay_rst_idle_r3 <= idelay_rst_idle_r2;
idelay_rst_idle_r4 <= idelay_rst_idle_r3;
idelay_rst_idle_r5 <= idelay_rst_idle_r4;
idelay_rst_idle_r6 <= idelay_rst_idle_r5;
idelay_inc_idle_r1 <= idelay_inc_idle;
idelay_inc_idle_r2 <= idelay_inc_idle_r1;
idelay_inc_idle_r3 <= idelay_inc_idle_r2;
idelay_inc_idle_r4 <= idelay_inc_idle_r3;
idelay_inc_idle_r5 <= idelay_inc_idle_r4;
idelay_inc_idle_r6 <= idelay_inc_idle_r5;
detect_edge_idle_r1 <= detect_edge_idle;
detect_edge_idle_r2 <= detect_edge_idle_r1;
detect_edge_idle_r3 <= detect_edge_idle_r2;
detect_edge_idle_r4 <= detect_edge_idle_r3;
detect_edge_idle_r5 <= detect_edge_idle_r4;
detect_edge_idle_r6 <= detect_edge_idle_r5;
valid_data_count <= data_count_valid;
end if;
end if;
end process;
 
-- Tap Delay Selection Complete for Data bus associated with a dqs
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
sel_complete <= '0';
else
sel_complete <= delay_sel_done;
end if;
end if;
end process;
 
 
-- Start detection of second transition only after 10 taps from first transition
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
dly_after_first_cnt <= "0000";
else
dly_after_first_cnt <= dly_after_first;
end if;
end if;
end process;
 
 
-- Tap Counter
process(clk)
begin
if(clk'event and clk = '1') then
if ((reset_int = '1') or (tap_counter = "111111")) then
tap_counter <= "000000";
elsif (dly_inc = '1') then
tap_counter <= tap_counter + '1';
end if;
end if;
end process;
 
-- Tap value for Data IDELAY circuit
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
first_edge_tap_count <= "000000";
elsif ((transition = "01") and (first_edge = '0')) then
first_edge_tap_count <= tap_counter;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
second_edge_tap_count <= "000000";
elsif ((transition = "10") and (second_edge = '0')) then
second_edge_tap_count <= tap_counter;
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
pulse_width_tap_count <= "000000";
elsif (second_edge_r1 = '1') then
pulse_width_tap_count <= (second_edge_tap_count - first_edge_tap_count);
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
pulse_center_tap_count <= "000000";
elsif (second_edge_r2 = '1') then
pulse_center_tap_count <= '0' & pulse_width_tap_count(5 downto 1);
-- Shift right to divide by 2 and find pulse center
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
data_bit_tap_count <= "000000";
elsif (second_edge_r3 = '1') then -- 2 edges detected
data_bit_tap_count <= first_edge_tap_count + pulse_center_tap_count;
elsif ((transition = "01") and ((tap_counter = "111111"))) then
if (first_edge_tap_count(5) = '0') then
data_bit_tap_count <= first_edge_tap_count + "010000";
else
data_bit_tap_count <= first_edge_tap_count - "010000";
end if;
elsif ((transition = "00") and ((tap_counter = "111111"))) then
data_bit_tap_count <= "100000";
end if;
end if;
end process;
 
 
-- Logic required to determine whether the registered dqs is on the edge of
-- meeting setup time in the FPGA clock domain.
-- If dqs is on the edge, then the vector 'flag' will not be "1111" or "0000" and
-- edge detection will not be executed.
-- If dqs is not on the edge, then the vector 'flag' will be "1111" or "0000" and
-- edge detection will be executed.
 
process(clk)
begin
if clk'event and clk = '1' then
if (reset_int = '1') then
flag <= (others => '0');
elsif (detect_edge_idle_r3 = '1' or idelay_inc_idle_r3 = '1' or
idelay_rst_idle_r3 = '1') then
if (curr_dqs_level /= prev_dqs_level) then
flag(0) <= '0';
else
flag(0) <= '1';
end if;
elsif (detect_edge_idle_r4 = '1' or idelay_inc_idle_r4 = '1' or
idelay_rst_idle_r4 = '1') then
if (curr_dqs_level /= prev_dqs_level) then
flag(1) <= '0';
else
flag(1) <= '1';
end if;
elsif (detect_edge_idle_r5 = '1' or idelay_inc_idle_r5 = '1' or
idelay_rst_idle_r5 = '1') then
if (curr_dqs_level /= prev_dqs_level) then
flag(2) <= '0';
else
flag(2) <= '1';
end if;
elsif (detect_edge_idle_r6 = '1' or idelay_inc_idle_r6 = '1' or
idelay_rst_idle_r6 = '1') then
if (curr_dqs_level /= prev_dqs_level) then
flag(3) <= '0';
else
flag(3) <= '1';
end if;
 
end if;
end if;
end process;
 
 
-- First and second edge assignment logic
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
transition(1 downto 0) <= "00";
elsif ((dly_after_first_cnt = "0000") and (state = DETECT_EDGE) and
((flag = X"0") or (flag = X"F"))) then
if ((curr_dqs_level /= prev_dqs_level) and (transition_rst = '0') and
(tap_counter > "000000")) then
transition <= transition + '1';
end if;
elsif (transition_rst = '1') then
transition <= "00";
else
transition <= transition;
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then
transition_rst <= '0';
first_edge <= '0';
second_edge <= '0';
else
case transition is
when "01" =>
first_edge <= '1';
 
when "10" =>
if (transition_rst = '1') then
second_edge <= '0';
transition_rst <= '0';
else
second_edge <= '1';
transition_rst <= '1';
end if;
when others =>
first_edge <= '0';
second_edge <= '0';
end case;
end if;
end if;
end process;
 
-- State Machine for edge detection and midpoint determination
process(clk)
begin
if(clk'event and clk = '1') then
if (reset_int = '1') then -- dqs IDELAY in reset
dly_rst <= '1';
dly_ce <= '0';
dly_inc <= '0';
idelay_rst_idle <= '0';
detect_edge_idle <= '0';
idelay_inc_idle <= '0';
prev_dqs_level <= curr_dqs_level;
state(2 downto 0) <= IDELAY_RST;
elsif ((ctrl_dummyread_start = '1') and (sel_complete = '0')) then
case state is
when "000" => -- IDELAY_RST
dly_rst <= '1';
dly_ce <= '0';
dly_inc <= '0';
idelay_rst_idle <= '1';
state(2 downto 0) <= IDLE;
when "001" => -- IDLE
dly_rst <= '0';
dly_ce <= '0';
dly_inc <= '0';
idelay_rst_idle <= '0';
detect_edge_idle <= '0';
idelay_inc_idle <= '0';
if (idelay_rst_idle_r5 = '1') then
state(2 downto 0) <= IDELAY_INC;
elsif ((idelay_inc_idle_r6 = '1') or ((detect_edge_idle_r6 = '1')
and (second_edge_r2 = '0') and (tap_counter /= "111111"))) then
state(2 downto 0) <= DETECT_EDGE;
else
state(2 downto 0) <= IDLE;
end if;
when "010" => -- IDELAY_INC
dly_rst <= '0';
dly_ce <= '1';
dly_inc <= '1';
idelay_inc_idle <= '1';
state(2 downto 0) <= IDLE;
if((flag(3 downto 0) = X"0") or (flag(3 downto 0) = X"F")) then
prev_dqs_level <= curr_dqs_level;
else
prev_dqs_level <= prev_dqs_level;
end if;
 
when "011" => -- DETECT_EDGE
dly_rst <= '0';
dly_ce <= '1';
dly_inc <= '1';
detect_edge_idle <= '1';
state(2 downto 0) <= IDLE;
if((flag(3 downto 0) = X"0") or (flag(3 downto 0) = X"F")) then
prev_dqs_level <= curr_dqs_level;
else
prev_dqs_level <= prev_dqs_level;
end if;
when others =>
dly_rst <= '0';
dly_ce <= '0';
dly_inc <= '0';
idelay_rst_idle <= '0';
detect_edge_idle <= '0';
idelay_inc_idle <= '0';
prev_dqs_level <= curr_dqs_level;
state(2 downto 0) <= IDLE;
end case;
else
dly_rst <= '0';
dly_ce <= '0';
dly_inc <= '0';
idelay_rst_idle <= '0';
detect_edge_idle <= '0';
idelay_inc_idle <= '0';
prev_dqs_level <= curr_dqs_level;
state <= IDELAY_RST;
end if;
end if;
end process;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_data_path_0/MIG_tap_logic/MIG_tap_logic_0.vhd
0,0 → 1,152
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_tap_logic_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the tap_cntrl and the data_tap_inc modules.
-- Used for calibration of the memory data with the FPGA clock.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_tap_logic_0 is
port(
clk : in std_logic;
reset0 : in std_logic;
idelay_ctrl_rdy : in std_logic;
ctrl_dummyread_start : in std_logic;
dqs_delayed : in std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
sel_done : out std_logic;
data_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0)
);
end MIG_tap_logic_0;
 
architecture arch of MIG_tap_logic_0 is
 
component MIG_tap_ctrl
port(
clk : in std_logic;
reset : in std_logic;
rdy_status : in std_logic;
dqs : in std_logic;
ctrl_dummyread_start : in std_logic;
dlyinc : out std_logic;
dlyce : out std_logic;
dlyrst : out std_logic;
sel_done : out std_logic;
valid_data_tap_count : out std_logic;
data_tap_count : out std_logic_vector(5 downto 0)
);
end component;
 
component MIG_data_tap_inc
port(
clk : in std_logic;
reset : in std_logic;
data_dlyinc : out std_logic;
data_dlyce : out std_logic;
data_dlyrst : out std_logic;
data_tap_sel_done : out std_logic;
dqs_sel_done : in std_logic;
valid_data_tap_count : in std_logic;
data_tap_count : in std_logic_vector(5 downto 0)
);
end component;
 
signal data_tap_select : std_logic_vector((READENABLE - 1) downto 0);
signal dqs_tap_sel_done : std_logic_vector((READENABLE - 1) downto 0);
signal valid_tap_count : std_logic_vector((READENABLE - 1) downto 0);
signal data_tap_inc_done : std_logic;
signal tap_sel_done : std_logic;
signal rst_r : std_logic;
signal data_tap_count0 : std_logic_vector(5 downto 0);
 
 
begin
 
-- For controller to stop dummy reads
sel_done <= tap_sel_done;
 
process(clk)
begin
if(clk'event and clk = '1') then
rst_r <= reset0;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
data_tap_inc_done <= '0';
tap_sel_done <= '0';
else
data_tap_inc_done <= data_tap_select(0) ;
tap_sel_done <= data_tap_inc_done;
 
end if;
end if;
end process;
 
--**********************************************************************
-- tap_ctrl instances for ddr_dqs strobes
--**********************************************************************
 
tap_ctrl_0: MIG_tap_ctrl
port map (
clk => clk,
reset => reset0,
rdy_status => idelay_ctrl_rdy,
dqs => dqs_delayed(3),
ctrl_dummyread_start => ctrl_dummyread_start,
dlyinc => dqs_idelay_inc(0),
dlyce => dqs_idelay_ce(0),
dlyrst => dqs_idelay_rst(0),
sel_done => dqs_tap_sel_done(0),
valid_data_tap_count => valid_tap_count(0),
data_tap_count => data_tap_count0(5 downto 0)
);
 
 
--**********************************************************************
-- instances of data_tap_inc for each dqs and associated tap_ctrl
--**********************************************************************
 
data_tap_inc_0: MIG_data_tap_inc
port map (
clk => clk,
reset => reset0,
data_dlyinc => data_idelay_inc(0),
data_dlyce => data_idelay_ce(0),
data_dlyrst => data_idelay_rst(0),
data_tap_sel_done => data_tap_select(0),
dqs_sel_done => dqs_tap_sel_done(0),
valid_data_tap_count => valid_tap_count(0),
data_tap_count => data_tap_count0(5 downto 0)
);
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_data_path_0/MIG_data_write_0.vhd
0,0 → 1,168
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_data_write_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Splits the user data into the rise data and the fall data.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_data_write_0 is
port(
clk : in std_logic;
clk90 : in std_logic;
reset90 : in std_logic;
wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
dummy_write_pattern : in std_logic;
ctrl_wren : in std_logic;
ctrl_dqs_rst : in std_logic;
ctrl_dqs_en : in std_logic;
dqs_rst : out std_logic;
dqs_en : out std_logic;
wr_en : out std_logic;
wr_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
);
end MIG_data_write_0;
 
architecture arch of MIG_data_write_0 is
 
signal wr_en_clk270_r1 : std_logic;
signal wr_en_clk90_r3 : std_logic;
signal dqs_rst_r1 : std_logic;
signal dqs_en_r1 : std_logic;
signal dqs_en_r2 : std_logic;
signal dummy_flag : std_logic;
signal dummy_rise_pattern : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal dummy_fall_pattern : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal dummy_write_pattern_270 : std_logic;
signal dummy_write_pattern_90 : std_logic;
signal dummy_flag1 : std_logic;
 
signal patA : std_logic_vector(143 downto 0);
signal pat5 : std_logic_vector(143 downto 0);
signal pat9 : std_logic_vector(143 downto 0);
signal pat6 : std_logic_vector(143 downto 0);
signal rst90_r : std_logic;
begin
 
dqs_rst <= dqs_rst_r1;
dqs_en <= dqs_en_r2;
wr_en <= wr_en_clk90_r3;
 
patA <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
pat5 <= X"555555555555555555555555555555555555";
pat9 <= X"999999999999999999999999999999999999";
pat6 <= X"666666666666666666666666666666666666";
 
process(clk90)
begin
if(clk90'event and clk90 = '1') then
rst90_r <= reset90;
end if;
end process;
 
process(clk90)
begin
if(clk90'event and clk90 = '0') then
wr_en_clk270_r1 <= ctrl_wren;
dqs_rst_r1 <= ctrl_dqs_rst;
dqs_en_r1 <= not ctrl_dqs_en;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '0') then
dqs_en_r2 <= dqs_en_r1;
end if;
end process;
 
process(clk90)
begin
if(clk90'event and clk90 = '1') then
wr_en_clk90_r3 <= wr_en_clk270_r1;
end if;
end process;
 
process(clk90)
begin
if(clk90'event and clk90 = '0') then
dummy_write_pattern_270 <= dummy_write_pattern;
end if;
end process;
 
process(clk90)
begin
if(clk90'event and clk90 = '1') then
dummy_write_pattern_90 <= dummy_write_pattern_270;
end if;
end process;
 
process(clk90)
begin
if(clk90'event and clk90 = '1') then
if(rst90_r = '1') then
dummy_flag <= '0';
elsif(dummy_write_pattern_90 = '1') then
if(dummy_flag = '1') then
dummy_rise_pattern <= patA((DATA_WIDTH - 1) downto 0);
else
dummy_rise_pattern <= pat9((DATA_WIDTH - 1) downto 0);
end if;
dummy_flag <= not dummy_flag;
end if;
end if;
end process;
process(clk90)
begin
if(clk90'event and clk90 = '1') then
if(rst90_r = '1') then
dummy_flag1 <= '0';
elsif(dummy_write_pattern_90 = '1') then
if(dummy_flag1 = '1') then
dummy_fall_pattern <= pat5((DATA_WIDTH - 1) downto 0);
else
dummy_fall_pattern <= pat6((DATA_WIDTH - 1) downto 0);
end if;
dummy_flag1 <= not dummy_flag1;
end if;
end if;
end process;
 
 
wr_data_rise <= dummy_rise_pattern when (dummy_write_pattern_90 = '1')
else wdf_data((DATA_WIDTH*2 - 1) downto data_width);
wr_data_fall <= dummy_fall_pattern when (dummy_write_pattern_90 = '1')
else wdf_data((DATA_WIDTH - 1) downto 0);
mask_data_rise <= (others => '0') when (dummy_write_pattern_90 = '1' or
wr_en_clk90_r3 = '0') else
mask_data((DATA_MASK_WIDTH*2 - 1) downto data_mask_width);
mask_data_fall <= (others => '0') when (dummy_write_pattern_90 = '1' or
wr_en_clk90_r3 = '0') else
mask_data((DATA_MASK_WIDTH - 1) downto 0);
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_iobs_0.vhd
0,0 → 1,176
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: This module instantiates all the iobs modules. It is the
-- interface between the main logic and the memory.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_iobs_0 is
port(
ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0);
clk : in std_logic;
clk90 : in std_logic;
dqs_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
dqs_rst : in std_logic;
dqs_en : in std_logic;
wr_en : in std_logic;
wr_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
rd_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
rd_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
dqs_delayed : out std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
ctrl_ddr_address : in std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : in std_logic;
ctrl_ddr_cas_l : in std_logic;
ctrl_ddr_we_l : in std_logic;
ctrl_ddr_cs_l : in std_logic;
ctrl_ddr_cke : in std_logic;
ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ddr_ras_l : out std_logic;
ddr_cas_l : out std_logic;
ddr_we_l : out std_logic;
ddr_cke : out std_logic;
ddr_cs_l : out std_logic
);
end MIG_iobs_0;
 
architecture arch of MIG_iobs_0 is
 
component MIG_infrastructure_iobs_0
port(
clk : in std_logic;
ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0)
);
end component;
 
component MIG_data_path_iobs_0
port (
clk : in std_logic;
clk90 : in std_logic;
dqs_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
dqs_rst : in std_logic;
dqs_en : in std_logic;
dqs_delayed : out std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
data_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
wr_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_en : in std_logic;
rd_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
rd_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
);
end component;
 
component MIG_controller_iobs_0
port (
ctrl_ddr_address : in std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : in std_logic;
ctrl_ddr_cas_l : in std_logic;
ctrl_ddr_we_l : in std_logic;
ctrl_ddr_cs_l : in std_logic;
ctrl_ddr_cke : in std_logic;
ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ddr_ras_l : out std_logic;
ddr_cas_l : out std_logic;
ddr_we_l : out std_logic;
ddr_cke : out std_logic;
ddr_cs_l : out std_logic
);
end component;
 
begin
 
infrastructure_iobs_00: MIG_infrastructure_iobs_0
port map (
clk => clk,
ddr_ck => ddr_ck,
ddr_ck_n => ddr_ck_n
);
 
data_path_iobs_00: MIG_data_path_iobs_0
port map (
clk => clk,
clk90 => clk90,
dqs_idelay_inc => dqs_idelay_inc,
dqs_idelay_ce => dqs_idelay_ce,
dqs_idelay_rst => dqs_idelay_rst,
dqs_rst => dqs_rst,
dqs_en => dqs_en,
dqs_delayed => dqs_delayed,
data_idelay_inc => data_idelay_inc,
data_idelay_ce => data_idelay_ce,
data_idelay_rst => data_idelay_rst,
wr_data_rise => wr_data_rise,
wr_data_fall => wr_data_fall,
wr_en => wr_en,
rd_data_rise => rd_data_rise,
rd_data_fall => rd_data_fall,
mask_data_rise => mask_data_rise,
mask_data_fall => mask_data_fall,
ddr_dq => ddr_dq,
ddr_dqs => ddr_dqs,
ddr_dm => ddr_dm
);
 
controller_iobs_00: MIG_controller_iobs_0
port map (
ctrl_ddr_address => ctrl_ddr_address,
ctrl_ddr_ba => ctrl_ddr_ba,
ctrl_ddr_ras_l => ctrl_ddr_ras_l,
ctrl_ddr_cas_l => ctrl_ddr_cas_l,
ctrl_ddr_we_l => ctrl_ddr_we_l,
ctrl_ddr_cs_l => ctrl_ddr_cs_l,
ctrl_ddr_cke => ctrl_ddr_cke,
ddr_address => ddr_address,
ddr_ba => ddr_ba,
ddr_ras_l => ddr_ras_l,
ddr_cas_l => ddr_cas_l,
ddr_we_l => ddr_we_l,
ddr_cke => ddr_cke,
ddr_cs_l => ddr_cs_l
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_infrastructure_iobs_0.vhd
0,0 → 1,71
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_infrastructure_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: The DDR memory clocks are generated here using the differential
-- buffers and the ODDR elemnts in the IOBs.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_infrastructure_iobs_0 is
port(
clk : in std_logic;
ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0)
);
end MIG_infrastructure_iobs_0;
 
architecture arch of MIG_infrastructure_iobs_0 is
 
 
signal ddr_ck_q : std_logic_vector((CLK_WIDTH - 1) downto 0);
signal vcc : std_logic;
signal gnd : std_logic;
 
begin
 
vcc <= '1';
gnd <= '0';
 
gen_ck: for ck_i in 0 to CLK_WIDTH-1 generate
u_oddr_ck_i : ODDR
generic map (
srtype => "SYNC",
ddr_clk_edge => "OPPOSITE_EDGE"
)
port map (
q => ddr_ck_q(ck_i),
c => clk,
ce => vcc,
d1 => gnd,
d2 => vcc,
r => gnd,
s => gnd
);
 
u_obuf_ck_i : OBUFDS
port map (
i => ddr_ck_q(ck_i),
o => ddr_ck(ck_i),
ob => ddr_ck_n(ck_i)
);
end generate;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_controller_iobs_0.vhd
0,0 → 1,105
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_controller_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Puts the memory control signals like address, bank address, row
-- address strobe, column address strobe, write enable and clock
-- enable in the IOBs.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_controller_iobs_0 is
port (
ctrl_ddr_address : in std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : in std_logic;
ctrl_ddr_cas_l : in std_logic;
ctrl_ddr_we_l : in std_logic;
ctrl_ddr_cs_l : in std_logic;
ctrl_ddr_cke : in std_logic;
ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ddr_ras_l : out std_logic;
ddr_cas_l : out std_logic;
ddr_we_l : out std_logic;
ddr_cke : out std_logic;
ddr_cs_l : out std_logic
);
end MIG_controller_iobs_0;
 
architecture arch of MIG_controller_iobs_0 is
attribute syn_useioff : boolean ;
 
begin
 
r0 : OBUF
port map(
I => ctrl_ddr_ras_l,
O => ddr_ras_l
);
 
r1 : OBUF
port map(
I => ctrl_ddr_cas_l,
O => ddr_cas_l
);
 
r2 : OBUF
port map(
I => ctrl_ddr_we_l,
O => ddr_we_l
);
 
 
OBUF_cs0 : OBUF
port map(
I => ctrl_ddr_cs_l,
O => ddr_cs_l
);
 
 
OBUF_cke0 : OBUF
port map(
I => ctrl_ddr_cke,
O => ddr_cke
);
 
 
gen_row: for row_i in 0 to ROW_ADDRESS-1 generate
attribute syn_useioff of obuf_r : label is true;
begin
obuf_r: OBUF
port map(
I => ctrl_ddr_address(row_i),
O => ddr_address(row_i)
);
end generate;
 
gen_bank: for bank_i in 0 to BANK_ADDRESS-1 generate
attribute syn_useioff of obuf_bank : label is true;
begin
obuf_bank: OBUF
port map(
I => ctrl_ddr_ba(bank_i),
O => ddr_ba(bank_i)
);
end generate;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_data_path_iobs/MIG_v4_dq_iob.vhd
0,0 → 1,125
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_v4_dq_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:25 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Places the data in the IOBs.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_v4_dq_iob is
port(
clk : in std_logic;
clk90 : in std_logic;
data_dlyinc : in std_logic;
data_dlyce : in std_logic;
data_dlyrst : in std_logic;
write_data_rise : in std_logic;
write_data_fall : in std_logic;
ctrl_wren : in std_logic;
ddr_dq : inout std_logic;
read_data_rise : out std_logic;
read_data_fall : out std_logic
);
end MIG_v4_dq_iob;
 
architecture arch of MIG_v4_dq_iob is
 
signal dq_in : std_logic;
signal dq_out : std_logic;
signal dq_delayed : std_logic;
signal write_en_l : std_logic;
signal write_en_l_r1 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
 
attribute IOB : string;
attribute IOB of tri_state_dq : label is "true";
attribute syn_useioff : boolean;
attribute syn_useioff of tri_state_dq : label is true;
 
begin
 
 
vcc <= '1';
gnd <= '0';
 
write_en_l <= not ctrl_wren;
 
oddr_dq : ODDR
generic map(
SRTYPE => "SYNC",
DDR_CLK_EDGE => "SAME_EDGE"
)
port map(
Q => dq_out,
C => clk90,
CE => vcc,
D1 => write_data_rise,
D2 => write_data_fall,
R => gnd,
S => gnd
);
 
tri_state_dq : FDCE
port map(
Q => write_en_l_r1,
C => clk90,
CE => vcc,
CLR => gnd,
D => write_en_l
);
 
iobuf_dq : IOBUF port map
(
I => dq_out,
T => write_en_l_r1,
IO => ddr_dq,
O => dq_in
);
 
idelay_dq : IDELAY
generic map(
IOBDELAY_TYPE => "VARIABLE",
IOBDELAY_VALUE => 0
)
port map(
O => dq_delayed,
I => dq_in,
C => clk,
CE => data_dlyce,
INC => data_dlyinc,
RST => data_dlyrst
);
 
iddr_dq : IDDR
generic map(
SRTYPE => "SYNC",
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map (
Q1 => read_data_rise,
Q2 => read_data_fall,
C => clk,
CE => vcc,
D => dq_delayed,
R => gnd,
S => gnd
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_data_path_iobs/MIG_v4_dqs_iob.vhd
0,0 → 1,131
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_v4_dqs_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:25 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Places the data stobes in the IOBs.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_v4_dqs_iob is
port(
clk : in std_logic;
dlyinc : in std_logic;
dlyce : in std_logic;
dlyrst : in std_logic;
ctrl_dqs_rst : in std_logic;
ctrl_dqs_en : in std_logic;
ddr_dqs : inout std_logic;
dqs_rise : out std_logic
);
end MIG_v4_dqs_iob;
 
architecture arch of MIG_v4_dqs_iob is
 
signal dqs_in : std_logic;
signal dqs_out : std_logic;
signal dqs_out_l : std_logic;
signal dqs_delayed : std_logic;
signal ctrl_dqs_en_r1 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal clk180 : std_logic;
signal dqs_int : std_logic;
signal data1 : std_logic;
attribute IOB : string;
attribute IOB of tri_state_dqs : label is "true";
attribute syn_useioff : boolean;
attribute syn_useioff of tri_state_dqs : label is true;
 
begin
 
vcc <= '1';
gnd <= '0';
clk180 <= not clk;
 
process(clk180)
begin
if(clk180'event and clk180 = '1') then
if (ctrl_dqs_rst = '1') then
data1 <= '0';
else
data1 <= '1';
end if;
end if;
end process;
 
idelay_dqs : IDELAY
generic map(
IOBDELAY_TYPE => "VARIABLE",
IOBDELAY_VALUE => 0
)
port map(
O => dqs_delayed,
I => dqs_in,
C => clk,
CE => dlyce,
INC => dlyinc,
RST => dlyrst
);
 
dqs_pipe1 : FD
port map(
Q => dqs_int,
C => clk,
D => dqs_delayed
);
 
dqs_pipe2 : FD
port map
(Q => dqs_rise,
C => clk,
D => dqs_int
);
 
oddr_dqs : ODDR
generic map(
SRTYPE => "SYNC",
DDR_CLK_EDGE => "OPPOSITE_EDGE"
)
port map
(Q => dqs_out,
C => clk180,
CE => vcc,
D1 => data1,
D2 => gnd,
R => gnd,
S => gnd
);
 
tri_state_dqs : FD
port map (
Q => ctrl_dqs_en_r1,
C => clk180,
D => ctrl_dqs_en
);
 
iobuf_dqs : IOBUF
port map (
I => dqs_out,
T => ctrl_dqs_en_r1,
IO => ddr_dqs,
O => dqs_in
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_iobs_0/MIG_data_path_iobs/MIG_v4_dm_iob.vhd
0,0 → 1,67
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_v4_dm_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:25 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Places the data mask signals into the IOBs.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_v4_dm_iob is
port(
clk90 : in std_logic;
mask_data_rise : in std_logic;
mask_data_fall : in std_logic;
ddr_dm : out std_logic
);
end MIG_v4_dm_iob;
 
architecture arch of MIG_v4_dm_iob is
 
signal vcc : std_logic;
signal gnd : std_logic;
signal data_mask : std_logic;
 
begin
 
vcc <= '1';
gnd <= '0';
 
oddr_dm : ODDR
generic map(
SRTYPE => "SYNC",
DDR_CLK_EDGE => "SAME_EDGE"
)
port map(
Q => data_mask,
C => clk90,
CE => vcc,
D1 => mask_data_rise,
D2 => mask_data_fall,
R => gnd,
S => gnd
);
 
DM_OBUF : OBUF
port map (
I => data_mask,
O => ddr_dm
);
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_ddr_controller_0.vhd
0,0 → 1,1789
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_ddr_controller_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: This is the main control logic of the memory interface. All
-- commands are issued from here acoording to the burst, CAS
-- Latency and the user commands.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_ddr_controller_0 is
port(
clk_0 : in std_logic;
rst : in std_logic;
-- FIFO signals
af_addr : in std_logic_vector(35 downto 0);
af_empty : in std_logic;
-- signals for the Dummy Reads
comp_done : in std_logic;
phy_dly_slct_done : in std_logic;
ctrl_dummyread_start : out std_logic;
-- FIFO read enable signals
ctrl_af_rden : out std_logic;
ctrl_wdf_rden : out std_logic;
-- Rst and Enable signals for DQS logic
ctrl_dqs_rst : out std_logic;
ctrl_dqs_en : out std_logic;
-- Read and Write Enable signals to the phy interface
ctrl_wren : out std_logic;
ctrl_rden : out std_logic;
--
ctrl_ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : out std_logic;
ctrl_ddr_cas_l : out std_logic;
ctrl_ddr_we_l : out std_logic;
ctrl_ddr_cs_l : out std_logic;
ctrl_ddr_cke : out std_logic;
init_done : out std_logic;
dummy_write_pattern : out std_logic;
burst_length_div2 : out std_logic_vector(2 downto 0)
);
end MIG_ddr_controller_0;
 
architecture arch of MIG_ddr_controller_0 is
 
signal init_count : std_logic_vector(3 downto 0);
signal init_count_cp : std_logic_vector(3 downto 0);
signal init_memory : std_logic;
signal count_200_cycle : std_logic_vector(7 downto 0);
signal ref_flag : std_logic;
signal ref_flag_0 : std_logic;
signal ref_flag_0_r : std_logic;
signal auto_ref : std_logic;
signal next_state : std_logic_vector(4 downto 0);
signal state : std_logic_vector(4 downto 0);
signal state_r2 : std_logic_vector(4 downto 0);
signal row_addr_r : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ddr_address_init_r : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ddr_address_r1 : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ddr_address_bl : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ddr_ba_r1 : std_logic_vector((BANK_ADDRESS - 1) downto 0);
signal mrd_count : std_logic;
signal rp_count : std_logic_vector(2 downto 0);
signal rfc_count : std_logic_vector(5 downto 0);
signal rcd_count : std_logic_vector(2 downto 0);
signal ras_count : std_logic_vector(3 downto 0);
signal wr_to_rd_count : std_logic_vector(3 downto 0);
signal rd_to_wr_count : std_logic_vector(3 downto 0);
signal rtp_count : std_logic_vector(3 downto 0);
signal wtp_count : std_logic_vector(3 downto 0);
signal refi_count : std_logic_vector((MAX_REF_WIDTH - 1) downto 0);
signal cas_count : std_logic_vector(2 downto 0);
signal cas_check_count : std_logic_vector(3 downto 0);
signal wrburst_cnt : std_logic_vector(2 downto 0);
signal read_burst_cnt : std_logic_vector(2 downto 0);
signal ctrl_wren_cnt : std_logic_vector(2 downto 0);
signal rdburst_cnt : std_logic_vector(2 downto 0);
signal af_addr_r : std_logic_vector(35 downto 0);
signal wdf_rden_r : std_logic;
signal wdf_rden_r2 : std_logic;
signal wdf_rden_r3 : std_logic;
signal wdf_rden_r4 : std_logic;
signal af_rden : std_logic;
signal ddr_ras_r2 : std_logic;
signal ddr_cas_r2 : std_logic;
signal ddr_we_r2 : std_logic;
signal ddr_ras_r : std_logic;
signal ddr_cas_r : std_logic;
signal ddr_we_r : std_logic;
signal ddr_ras_r3 : std_logic;
signal ddr_cas_r3 : std_logic;
signal ddr_we_r3 : std_logic;
signal idle_cnt : std_logic_vector(3 downto 0);
signal ctrl_dummyread_start_r1 : std_logic;
signal ctrl_dummyread_start_r2 : std_logic;
signal ctrl_dummyread_start_r3 : std_logic;
signal ctrl_dummyread_start_r4 : std_logic;
signal conflict_resolved_r : std_logic;
signal ddr_cke_r : std_logic;
signal chip_cnt : std_logic_vector(1 downto 0);
signal dummy_read_en : std_logic;
signal ctrl_init_done : std_logic;
signal count_200cycle_done_r : std_logic;
signal init_done_int : std_logic;
signal burst_cnt : std_logic_vector(3 downto 0);
signal burst_cnt_by2 : std_logic_vector(2 downto 0);
signal conflict_detect : std_logic;
signal conflict_detect_r : std_logic;
signal load_mode_reg : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ext_mode_reg : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal cas_latency_value : std_logic_vector(3 downto 0);
signal burst_length_value : std_logic_vector(2 downto 0);
signal registered_dimm : std_logic;
signal wr : std_logic;
signal rd : std_logic;
signal lmr : std_logic;
signal pre : std_logic;
signal ref : std_logic;
signal act : std_logic;
signal wr_r : std_logic;
signal rd_r : std_logic;
signal lmr_r : std_logic;
signal pre_r : std_logic;
signal ref_r : std_logic;
signal act_r : std_logic;
signal af_empty_r : std_logic;
signal lmr_pre_ref_act_cmd_r : std_logic;
signal command_address : std_logic_vector(2 downto 0);
signal cke_200us_cnt : std_logic_vector(4 downto 0);
signal done_200us : std_logic;
signal write_state : std_logic;
signal read_state : std_logic;
signal read_write_state : std_logic;
signal burst_write_state : std_logic;
signal first_write_state : std_logic;
signal burst_read_state : std_logic;
signal first_read_state : std_logic;
signal burst_read_state_r2 : std_logic;
signal burst_read_state_r3 : std_logic;
signal first_read_state_r2 : std_logic;
signal read_write_state_r2 : std_logic;
signal dummy_write_state : std_logic;
signal dummy_write_state_r : std_logic;
signal pattern_read_state : std_logic;
signal pattern_read_state_1 : std_logic;
signal pattern_read_state_r2 : std_logic;
signal pattern_read_state_r3 : std_logic;
signal pattern_read_state_1_r2 : std_logic;
signal dummy_write_flag : std_logic;
signal rst_r : std_logic;
signal ctrl_wdf_rden_r : std_logic;
signal ctrl_wdf_rden_r1 : std_logic;
signal ctrl_dqs_rst_r : std_logic;
signal ctrl_dqs_rst_r1 : std_logic;
signal ctrl_wren_r : std_logic;
signal ctrl_wren_r1 : std_logic;
signal ctrl_rden_r : std_logic;
signal ctrl_rden_r1 : std_logic;
signal ctrl_dqs_en_r : std_logic;
signal ctrl_dqs_en_r1 : std_logic;
signal dummy_write_pattern_1 : std_logic;
signal dummy_write_pattern_2 : std_logic;
signal ddr_address_r2 : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ddr_ba_r2 : std_logic_vector((BANK_ADDRESS - 1) downto 0);
signal init_next_state : std_logic_vector(4 downto 0);
signal init_state : std_logic_vector(4 downto 0);
signal init_state_r2 : std_logic_vector(4 downto 0);
signal count5 : std_logic_vector(4 downto 0);
 
constant IDLE : std_logic_vector(4 downto 0) := "00000"; --5'h00
constant LOAD_MODE_REG_ST : std_logic_vector(4 downto 0) := "00001"; --5'h01
constant MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "00010"; --5'h02
constant PRECHARGE : std_logic_vector(4 downto 0) := "00011"; --5'h03
constant PRECHARGE_WAIT : std_logic_vector(4 downto 0) := "00100"; --5'h04
constant AUTO_REFRESH : std_logic_vector(4 downto 0) := "00101"; --5'h05
constant AUTO_REFRESH_WAIT : std_logic_vector(4 downto 0) := "00110"; --5'h06
constant ACTIVE : std_logic_vector(4 downto 0) := "00111"; --5'h07
constant ACTIVE_WAIT : std_logic_vector(4 downto 0) := "01000"; --5'h08
constant FIRST_WRITE : std_logic_vector(4 downto 0) := "01001"; --5'h09
constant BURST_WRITE : std_logic_vector(4 downto 0) := "01010"; --5'h0A
constant WRITE_WAIT : std_logic_vector(4 downto 0) := "01011"; --5'h0B
constant WRITE_READ : std_logic_vector(4 downto 0) := "01100"; --5'h0C
constant FIRST_READ : std_logic_vector(4 downto 0) := "01101"; --5'h0D
constant BURST_READ : std_logic_vector(4 downto 0) := "01110"; --5'h0E
constant READ_WAIT : std_logic_vector(4 downto 0) := "01111"; --5'h0F
constant READ_WRITE : std_logic_vector(4 downto 0) := "10000"; --5'h10
 
constant INIT_IDLE : std_logic_vector(4 downto 0) := "00000";
constant INIT_DEEP_MEMORY_ST : std_logic_vector(4 downto 0) := "00001";
constant INIT_INITCOUNT_200 : std_logic_vector(4 downto 0) := "00010";
constant INIT_INITCOUNT_200_WAIT : std_logic_vector(4 downto 0) := "00011";
constant INIT_DUMMY_READ_CYCLES : std_logic_vector(4 downto 0) := "00100";
constant INIT_DUMMY_ACTIVE : std_logic_vector(4 downto 0) := "00101";
constant INIT_DUMMY_ACTIVE_WAIT : std_logic_vector(4 downto 0) := "00110";
constant INIT_DUMMY_FIRST_READ : std_logic_vector(4 downto 0) := "00111";
constant INIT_DUMMY_READ : std_logic_vector(4 downto 0) := "01000";
constant INIT_DUMMY_READ_WAIT : std_logic_vector(4 downto 0) := "01001";
constant INIT_DUMMY_WRITE1 : std_logic_vector(4 downto 0) := "01010";
constant INIT_DUMMY_WRITE2 : std_logic_vector(4 downto 0) := "01011";
constant INIT_DUMMY_WRITE_READ : std_logic_vector(4 downto 0) := "01100";
constant INIT_PATTERN_READ1 : std_logic_vector(4 downto 0) := "01101";
constant INIT_PATTERN_READ2 : std_logic_vector(4 downto 0) := "01110";
constant INIT_PATTERN_READ_WAIT : std_logic_vector(4 downto 0) := "01111";
constant INIT_PRECHARGE : std_logic_vector(4 downto 0) := "10000";
constant INIT_PRECHARGE_WAIT : std_logic_vector(4 downto 0) := "10001";
constant INIT_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10010";
constant INIT_AUTO_REFRESH_WAIT : std_logic_vector(4 downto 0) := "10011";
constant INIT_LOAD_MODE_REG_ST : std_logic_vector(4 downto 0) := "10100";
constant INIT_MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "10101";
 
constant cntnext : std_logic_vector(4 downto 0) := "11000";
 
attribute syn_preserve : boolean;
attribute syn_preserve of arch : architecture is true;
 
begin
 
 
 
registered_dimm <= '0';
 
 
cas_latency_value <= "0010" when (load_mode_reg(6 downto 4) = "110") else
'0' & load_mode_reg(6 downto 4);
burst_length_value <= load_mode_reg(2 downto 0);
burst_length_div2 <= burst_cnt(2 downto 0);
command_address <= af_addr(34 downto 32);
 
burst_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
and (state = BURST_READ) and (rd = '1') else '0';
first_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
and (state = FIRST_READ) and (rd = '1') else '0';
read_state <= burst_read_state or first_read_state;
read_write_state <= write_state or read_state;
burst_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
and (state = BURST_WRITE) and (wr = '1') else '0';
first_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
and (state = FIRST_WRITE) and (wr = '1') else '0';
write_state <= burst_write_state or first_write_state;
 
dummy_write_state <= '1' when ((init_state = INIT_DUMMY_WRITE1) or
(init_state = INIT_DUMMY_WRITE2))
else '0';
dummy_write_pattern_1 <= '1' when ((init_state = INIT_DUMMY_WRITE1) or
(init_state = INIT_DUMMY_WRITE2) or
(init_state = INIT_DUMMY_WRITE_READ)) else '0';
pattern_read_state <= '1' when ((init_state = INIT_PATTERN_READ1) or
(init_state = INIT_PATTERN_READ2))
else '0';
pattern_read_state_1 <= '1' when (init_state = INIT_PATTERN_READ1) else '0';
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
rst_r <= rst;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
dummy_write_pattern_2 <= '0';
else
dummy_write_pattern_2 <= dummy_write_pattern_1;
end if;
end if;
end process;
 
dummy_write_pattern <= dummy_write_pattern_2 when (registered_dimm = '1')
else dummy_write_pattern_1;
 
-- fifo control signals
 
ctrl_af_rden <= af_rden;
 
conflict_detect <= af_addr(35) and ctrl_init_done and (not af_empty);
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
pattern_read_state_r2 <= '0';
pattern_read_state_r3 <= '0';
else
pattern_read_state_r2 <= pattern_read_state;
pattern_read_state_r3 <= pattern_read_state_r2;
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
pattern_read_state_1_r2 <= '0';
else
pattern_read_state_1_r2 <= pattern_read_state_1;
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
dummy_write_state_r <= '0';
else
dummy_write_state_r <= dummy_write_state;
end if;
end if;
end process;
 
--commands
 
process(command_address, ctrl_init_done, af_empty)
begin
wr <= '0';
rd <= '0';
lmr <= '0';
pre <= '0';
ref <= '0';
act <= '0';
if((ctrl_init_done = '1') and (af_empty = '0')) then
case command_address is
when "000" => lmr <= '1';
when "001" => ref <= '1';
when "010" => pre <= '1';
when "011" => act <= '1';
when "100" => wr <= '1';
when "101" => rd <= '1';
when others => null;
end case;
end if;
end process;
 
-- register address outputs
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
wr_r <= '0';
rd_r <= '0';
lmr_r <= '0';
pre_r <= '0';
ref_r <= '0';
act_r <= '0';
af_empty_r <= '0';
lmr_pre_ref_act_cmd_r <= '0';
else
wr_r <= wr;
rd_r <= rd;
lmr_r <= lmr;
pre_r <= pre;
ref_r <= ref;
act_r <= act;
lmr_pre_ref_act_cmd_r <= lmr or pre or ref or act;
af_empty_r <= af_empty;
end if;
end if;
end process;
 
 
-- register address outputs
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
af_addr_r <= (others => '0');
conflict_detect_r <= '0';
read_write_state_r2 <= '0';
first_read_state_r2 <= '0';
burst_read_state_r2 <= '0';
burst_read_state_r3 <= '0';
else
af_addr_r <= af_addr;
conflict_detect_r <= conflict_detect;
read_write_state_r2 <= read_write_state;
first_read_state_r2 <= first_read_state;
burst_read_state_r2 <= burst_read_state;
burst_read_state_r3 <= burst_read_state_r2;
end if;
end if;
end process;
 
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
load_mode_reg <= LOAD_MODE_REGISTER((ROW_ADDRESS - 1) downto 0);
elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and
(lmr_r = '1') and (af_addr_r((BANK_ADDRESS+ROW_ADDRESS+COL_AP_WIDTH-1)
downto (COL_AP_WIDTH+ROW_ADDRESS)) = "00")) then
load_mode_reg <= af_addr ((ROW_ADDRESS - 1) downto 0);
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ext_mode_reg <= EXT_LOAD_MODE_REGISTER((ROW_ADDRESS - 1) downto 0);
elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and
(lmr_r = '1') and (af_addr_r((BANK_ADDRESS+ROW_ADDRESS+COL_AP_WIDTH-1)
downto (COL_AP_WIDTH+ROW_ADDRESS)) = "01")) then
ext_mode_reg <= af_addr (ROW_ADDRESS - 1 downto 0);
end if;
end if;
end process;
 
--to initialize memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if ((rst_r = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then
init_memory <= '1';
elsif (init_count_cp = "1010") then
init_memory <= '0';
else
init_memory <= init_memory;
end if;
end if;
end process;
 
-- mrd count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
mrd_count <= '0';
elsif (state = LOAD_MODE_REG_ST) then
mrd_count <= MRD_COUNT_VALUE;
elsif (mrd_count /= '0') then
mrd_count <= '0';
else
mrd_count <= '0';
end if;
end if;
end process;
 
-- rp count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
rp_count(2 downto 0) <= "000";
elsif (state = PRECHARGE) then
rp_count(2 downto 0) <= RP_COUNT_VALUE;
elsif (rp_count(2 downto 0) /= "000") then
rp_count(2 downto 0) <= rp_count(2 downto 0) - 1;
else
rp_count(2 downto 0) <= "000";
end if;
end if;
end process;
 
-- rfc count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
rfc_count(5 downto 0) <= "000000";
elsif (state = AUTO_REFRESH) then
rfc_count(5 downto 0) <= RFC_COUNT_VALUE;
elsif (rfc_count(5 downto 0) /= "000000") then
rfc_count(5 downto 0) <= rfc_count(5 downto 0) - 1;
else
rfc_count(5 downto 0) <= "000000";
end if;
end if;
end process;
 
-- rcd count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
rcd_count(2 downto 0) <= "000";
elsif (state = ACTIVE) then
rcd_count(2 downto 0) <= RCD_COUNT_VALUE;
elsif (rcd_count(2 downto 0) /= "000") then
rcd_count(2 downto 0) <= rcd_count(2 downto 0) - 1;
else
rcd_count(2 downto 0) <= "000";
end if;
end if;
end process;
 
 
-- ras count - active to precharge
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ras_count(3 downto 0) <= "0000";
elsif (state = ACTIVE) then
ras_count(3 downto 0) <= RAS_COUNT_VALUE;
elsif (ras_count(3 downto 1) = "000") then
if (ras_count(0) /= '0') then
ras_count(0) <= '0';
end if;
else
ras_count(3 downto 0) <= ras_count(3 downto 0) - 1;
end if;
end if;
end process;
 
--AL+BL/2+TRTP-2
-- rtp count - read to precharge
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
rtp_count(3 downto 0) <= "0000";
elsif (read_state = '1') then
rtp_count(2 downto 0) <= TRTP_COUNT_VALUE;
elsif (rtp_count(3 downto 1) = "000") then
if (rtp_count(0) /= '0') then
rtp_count(0) <= '0';
end if;
else
rtp_count(3 downto 0) <= rtp_count(3 downto 0) - 1;
end if;
end if;
end process;
 
-- WL+BL/2+TWR
-- wtp count - write to precharge
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
wtp_count(3 downto 0) <= "0000";
elsif (write_state = '1') then
wtp_count(2 downto 0) <= TWR_COUNT_VALUE;
elsif (wtp_count(3 downto 1) = "000") then
if (wtp_count(0) /= '0') then
wtp_count(0) <= '0';
end if;
else
wtp_count(3 downto 0) <= wtp_count(3 downto 0) - 1;
end if;
end if;
end process;
 
-- write to read counter
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
wr_to_rd_count(3 downto 0) <= "0000";
elsif (write_state = '1') then
wr_to_rd_count(2 downto 0) <= TWTR_COUNT_VALUE;
elsif (wr_to_rd_count(3 downto 0) /= "0000") then
wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - 1;
else
wr_to_rd_count(3 downto 0) <= "0000";
end if;
end if;
end process;
 
-- read to write counter
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
rd_to_wr_count(3 downto 0) <= "0000";
elsif (read_state = '1') then
rd_to_wr_count(3 downto 0) <= REGISTERED + burst_cnt + load_mode_reg(6)
+ load_mode_reg(4);
elsif (rd_to_wr_count(3 downto 0) /= "0000") then
rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - 1;
else
rd_to_wr_count(3 downto 0) <= "0000";
end if;
end if;
end process;
 
-- auto refresh interval counter in clk_0 domain
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
refi_count <= (others => '0');
elsif (refi_count = MAX_REF_CNT) then
refi_count <= (others => '0');
else
refi_count <= refi_count + 1;
end if;
end if;
end process;
 
ref_flag <= '1' when ((refi_count = MAX_REF_CNT) and (done_200us = '1')) else
'0';
 
--200us counter for cke
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
cke_200us_cnt <= "11011";
elsif (refi_count(MAX_REF_WIDTH - 1 downto 0) = MAX_REF_CNT) then
cke_200us_cnt <= cke_200us_cnt - 1;
else
cke_200us_cnt <= cke_200us_cnt;
end if;
end if;
end process;
 
-- refresh detect
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ref_flag_0 <= '0';
ref_flag_0_r <= '0';
done_200us <= '0';
else
ref_flag_0 <= ref_flag;
ref_flag_0_r <= ref_flag_0;
if (done_200us = '0' and (cke_200us_cnt = "00000")) then
done_200us <= '1';
end if;
end if;
end if;
end process;
 
--refresh flag detect
--auto_ref high indicates auto_refresh requirement
--auto_ref is held high until auto refresh command is issued.
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
auto_ref <= '0';
elsif (ref_flag_0 = '1' and ref_flag_0_r = '0') then
auto_ref <= '1';
elsif ((state = AUTO_REFRESH) or (init_state = INIT_AUTO_REFRESH)) then
auto_ref <= '0';
else
auto_ref <= auto_ref;
end if;
end if;
end process;
 
-- 200 clocks counter - count value : C8
-- required for initialization
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
count_200_cycle(7 downto 0) <= "00000000";
elsif (init_state = INIT_INITCOUNT_200) then
count_200_cycle(7 downto 0) <= "11001000";
elsif (count_200_cycle(7 downto 0) /= "00000000") then
count_200_cycle(7 downto 0) <= count_200_cycle(7 downto 0) - 1;
else
count_200_cycle(7 downto 0) <= "00000000";
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
count_200cycle_done_r <= '0';
elsif ((init_memory = '1') and (count_200_cycle = "00000000")) then
count_200cycle_done_r <= '1';
else
count_200cycle_done_r <= '0';
end if;
end if;
end process;
 
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
init_done_int <= '0';
elsif ((PHY_MODE = '1') and (comp_done = '1') and (count5 = "10100")) then
init_done_int <= '1';
--synthesis translate_off
report "Calibration completed at time " & time'image(now);
--synthesis translate_on
else
init_done_int <= init_done_int;
end if;
end if;
end process;
 
ctrl_init_done <= init_done_int;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
init_done <= init_done_int;
end if;
end process;
 
burst_cnt <= "0010" when (burst_length_value = "010") else
"0100" when (burst_length_value = "011") else
"0001";
 
burst_cnt_by2 <= "001" when (burst_length_value = "010") else
"010" when (burst_length_value = "011") else
"000";
 
ddr_address_bl <= ADD_CONST7((ROW_ADDRESS - 1) downto 0) when
(burst_length_value = "010") else
ADD_CONST8((ROW_ADDRESS - 1) downto 0) when
(burst_length_value = "011") else
ADD_CONST6((ROW_ADDRESS - 1) downto 0);
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if ((rst_r = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
init_count(3 downto 0) <= "0000";
elsif (init_memory = '1') then
if (init_state=INIT_LOAD_MODE_REG_ST or init_state=INIT_PRECHARGE or
init_state = INIT_AUTO_REFRESH or init_state=INIT_DUMMY_READ_CYCLES
or init_state=INIT_INITCOUNT_200 or init_state=INIT_DEEP_MEMORY_ST) then
init_count(3 downto 0) <= init_count(3 downto 0) + 1;
elsif(init_count = "1010") then
init_count(3 downto 0) <= "0000";
else init_count(3 downto 0) <= init_count(3 downto 0);
end if;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if ((rst_r = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
init_count_cp(3 downto 0) <= "0000";
elsif (init_memory = '1') then
if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or
init_state = INIT_AUTO_REFRESH or
init_state = INIT_DUMMY_READ_CYCLES or init_state=INIT_INITCOUNT_200
or init_state = INIT_DEEP_MEMORY_ST) then
init_count_cp(3 downto 0) <= init_count_cp(3 downto 0) + 1;
elsif(init_count_cp = "1010") then
init_count_cp(3 downto 0) <= "0000";
else init_count_cp(3 downto 0) <= init_count_cp(3 downto 0);
end if;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
chip_cnt <= "00";
elsif (init_state = INIT_DEEP_MEMORY_ST) then
chip_cnt <= chip_cnt + "01";
else
chip_cnt <= chip_cnt;
end if;
end if;
end process;
 
-- write burst count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
wrburst_cnt(2 downto 0) <= "000";
elsif (write_state = '1' or dummy_write_state = '1') then
wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
elsif (wrburst_cnt(2 downto 0) /= "000") then
wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - 1;
else wrburst_cnt(2 downto 0) <= "000";
end if;
end if;
end process;
 
-- read burst count for state machine
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
read_burst_cnt(2 downto 0) <= "000";
elsif (read_state = '1') then
read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
elsif (read_burst_cnt(2 downto 0) /= "000") then
read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - 1;
else read_burst_cnt(2 downto 0) <= "000";
end if;
end if;
end process;
 
-- count to generate write enable to the data path
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_wren_cnt(2 downto 0) <= "000";
elsif ((wdf_rden_r = '1') or (dummy_write_state_r = '1')) then
ctrl_wren_cnt(2 downto 0) <= burst_cnt(2 downto 0);
elsif (ctrl_wren_cnt(2 downto 0) /= "000") then
ctrl_wren_cnt(2 downto 0) <= ctrl_wren_cnt(2 downto 0) -1;
else
ctrl_wren_cnt(2 downto 0) <= "000";
end if;
end if;
end process;
 
--write enable to data path
process (ctrl_wren_cnt)
begin
if (ctrl_wren_cnt(2 downto 0) /= "000") then
ctrl_wren_r <= '1';
else
ctrl_wren_r <= '0';
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_wren_r1 <= '0';
else
ctrl_wren_r1 <= ctrl_wren_r;
end if;
end if;
end process;
 
ctrl_wren <= ctrl_wren_r1 when (registered_dimm = '1') else
ctrl_wren_r;
 
-- DQS reset to data path
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_dqs_rst_r <= '0';
elsif (first_write_state = '1' or init_state = INIT_DUMMY_WRITE1) then
ctrl_dqs_rst_r <= '1';
else
ctrl_dqs_rst_r <= '0';
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_dqs_rst_r1 <= '0';
else
ctrl_dqs_rst_r1 <= ctrl_dqs_rst_r;
end if;
end if;
end process;
 
ctrl_dqs_rst <= ctrl_dqs_rst_r1 when (registered_dimm = '1') else
ctrl_dqs_rst_r;
 
-- DQS enable to data path
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_dqs_en_r <= '0';
elsif ((write_state = '1') or (wrburst_cnt /= "000") or
(dummy_write_state = '1')) then
ctrl_dqs_en_r <= '1';
else
ctrl_dqs_en_r <= '0';
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_dqs_en_r1 <= '0';
else
ctrl_dqs_en_r1 <= ctrl_dqs_en_r;
end if;
end if;
end process;
 
ctrl_dqs_en <= ctrl_dqs_en_r1 when (registered_dimm = '1') else
ctrl_dqs_en_r;
 
-- cas count
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
cas_count(2 downto 0) <= "000";
elsif ((init_state = INIT_DUMMY_FIRST_READ)) then
cas_count(2 downto 0) <= cas_latency_value(2 downto 0) + REGISTERED;
elsif (cas_count(2 downto 0) /= "000") then
cas_count(2 downto 0) <= cas_count(2 downto 0) - 1;
else cas_count(2 downto 0) <= "000";
end if;
end if;
end process;
 
--dummy_read enable
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
dummy_read_en <= '0';
elsif (init_state = INIT_DUMMY_READ) then
dummy_read_en <= '1';
elsif (phy_dly_slct_done = '1') then
dummy_read_en <= '0';
else dummy_read_en <= dummy_read_en;
end if;
end if;
end process;
 
-- ctrl_dummyread_start signal generation to the data path module
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
 
ctrl_dummyread_start_r1 <= '0';
elsif ((dummy_read_en = '1') and (cas_count = "000")) then
ctrl_dummyread_start_r1 <= '1';
elsif (phy_dly_slct_done = '1') then
ctrl_dummyread_start_r1 <= '0';
else ctrl_dummyread_start_r1 <= ctrl_dummyread_start_r1;
end if;
end if;
end process;
 
-- register ctrl_dummyread_start signal
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_dummyread_start_r2 <= '0';
ctrl_dummyread_start_r3 <= '0';
ctrl_dummyread_start_r4 <= '0';
ctrl_dummyread_start <= '0';
else
ctrl_dummyread_start_r2 <= ctrl_dummyread_start_r1;
ctrl_dummyread_start_r3 <= ctrl_dummyread_start_r2;
ctrl_dummyread_start_r4 <= ctrl_dummyread_start_r3;
ctrl_dummyread_start <= ctrl_dummyread_start_r4;
end if;
end if;
end process;
 
-- read_wait/write_wait to idle count
-- the state machine waits for 15 clock cycles in the write wait state for any
-- wr/rd commands to be issued. If no commands are issued in 15 clock cycles,
-- the statemachine issues enters the idle state and stays in the idle state
-- until an auto refresh is required.
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
idle_cnt(3 downto 0) <= "0000";
elsif (read_write_state = '1') then
idle_cnt(3 downto 0) <= "1111";
elsif (idle_cnt(3 downto 0) /= "0000") then
idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - 1;
else idle_cnt(3 downto 0) <= "0000";
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
cas_check_count(3 downto 0) <= "0000";
elsif (first_read_state_r2 = '1' or pattern_read_state_1_r2 = '1') then
cas_check_count(3 downto 0) <= (cas_latency_value - 1);
elsif (cas_check_count(3 downto 0) /= "0000") then
cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - 1;
else
cas_check_count(3 downto 0) <= "0000";
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
rdburst_cnt(2 downto 0) <= "000";
ctrl_rden_r <= '0';
elsif ((cas_check_count = "0001") and (burst_read_state_r3 = '0')) then
rdburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
ctrl_rden_r <= '1';
elsif(burst_read_state_r3 = '1' or pattern_read_state_r3 = '1') then
if(burst_cnt = "0100") then
rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0) +
burst_cnt_by2;
elsif (burst_cnt = "010") then
rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0);
else
rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0) -
burst_cnt(2 downto 0);
end if;
if(burst_read_state_r3 = '1') then
ctrl_rden_r <= '1';
end if;
elsif (rdburst_cnt(2 downto 0) /= "000") then
rdburst_cnt(2 downto 0) <= rdburst_cnt(2 downto 0) - '1';
if(rdburst_cnt = "001") then
ctrl_rden_r <= '0';
end if;
else
rdburst_cnt(2 downto 0) <= "000";
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
ctrl_rden_r1 <= '0';
else
ctrl_rden_r1 <= ctrl_rden_r;
end if;
end if;
end process;
 
ctrl_rden <= ctrl_rden_r1 when (registered_dimm = '1') else
ctrl_rden_r;
 
-- write address FIFO read enable signals
 
af_rden <= '1' when ((read_write_state = '1') or
((state = MODE_REGISTER_WAIT) and lmr_r = '1'
and (mrd_count = '0'))
or ((state = PRECHARGE)and pre_r = '1') or
((state = AUTO_REFRESH) and ref_r = '1')
or ((state = ACTIVE)and act_r = '1')) else '0';
 
-- write data fifo read enable
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
wdf_rden_r <= '0';
elsif (write_state = '1') then
wdf_rden_r <= '1';
else
wdf_rden_r <= '0';
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
wdf_rden_r2 <= '0';
wdf_rden_r3 <= '0';
wdf_rden_r4 <= '0';
else
wdf_rden_r2 <= wdf_rden_r;
wdf_rden_r3 <= wdf_rden_r2;
wdf_rden_r4 <= wdf_rden_r3;
end if;
end if;
end process;
 
-- Read enable to the data fifo
 
process (burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4)
begin
if (burst_cnt = "001") then
ctrl_wdf_rden_r <= (wdf_rden_r);
elsif (burst_cnt = "010") then
ctrl_wdf_rden_r <= (wdf_rden_r or wdf_rden_r2);
elsif (burst_cnt = "100") then
ctrl_wdf_rden_r <= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or
wdf_rden_r4);
else
ctrl_wdf_rden_r <= '0';
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ctrl_wdf_rden_r1 <= '0';
else
ctrl_wdf_rden_r1 <= ctrl_wdf_rden_r;
end if;
end if;
end process;
 
ctrl_wdf_rden <= ctrl_wdf_rden_r1 when (registered_dimm = '1') else
ctrl_wdf_rden_r;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
dummy_write_flag <= '0';
else
dummy_write_flag <= phy_dly_slct_done and not(comp_done);
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
init_state <= INIT_IDLE;
else
init_state <= init_next_state;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
count5 <= (others => '0');
else
case init_state is
when INIT_PRECHARGE_WAIT | INIT_MODE_REGISTER_WAIT |
INIT_AUTO_REFRESH_WAIT | INIT_DUMMY_WRITE_READ |
INIT_PATTERN_READ_WAIT | INIT_DUMMY_READ_WAIT |
INIT_DUMMY_ACTIVE_WAIT =>
count5 <= count5 + '1';
 
when others =>
count5 <= (others => '0');
end case;
end if;
end if;
end process;
 
-- Initialization state machine
process (auto_ref, chip_cnt, count_200cycle_done_r, done_200us,
init_count, init_memory, phy_dly_slct_done, init_state,
burst_cnt, comp_done, dummy_write_flag, count5)
begin
 
init_next_state <= init_state;
case init_state is
when INIT_IDLE =>
if (init_memory = '1' and done_200us = '1') then
case init_count is -- synthesis parallel_case full_case
when "0000" => init_next_state <= INIT_INITCOUNT_200;
when "0001" => init_next_state <= INIT_PRECHARGE;
when "0010" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "0011" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "0100" => init_next_state <= INIT_INITCOUNT_200;
when "0101" => init_next_state <= INIT_PRECHARGE;
when "0110" => init_next_state <= INIT_AUTO_REFRESH;
when "0111" => init_next_state <= INIT_AUTO_REFRESH;
when "1000" => init_next_state <= INIT_LOAD_MODE_REG_ST;
when "1001" =>
if((chip_cnt < NO_OF_CS-1)) then
init_next_state <= INIT_DEEP_MEMORY_ST;
elsif ((PHY_MODE = '1' and count_200cycle_done_r = '1')) then
init_next_state <= INIT_DUMMY_READ_CYCLES;
else
init_next_state <= INIT_IDLE;
end if;
when "1010" =>
if (phy_dly_slct_done = '1') then
init_next_state <= INIT_IDLE;
end if;
when others => init_next_state <= INIT_IDLE;
 
end case; -- case(init_count )
end if;
 
when INIT_DEEP_MEMORY_ST => init_next_state <= INIT_IDLE;
 
when INIT_INITCOUNT_200 => init_next_state <= INIT_INITCOUNT_200_WAIT;
 
when INIT_INITCOUNT_200_WAIT =>
if (count_200cycle_done_r = '1') then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_INITCOUNT_200_WAIT;
end if;
 
when INIT_DUMMY_READ_CYCLES => init_next_state <= INIT_DUMMY_ACTIVE;
 
 
when INIT_DUMMY_ACTIVE => init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
 
 
when INIT_DUMMY_ACTIVE_WAIT =>
if (count5 = cntnext) then
if(dummy_write_flag = '1') then
init_next_state <= INIT_DUMMY_WRITE1;
else
init_next_state <= INIT_DUMMY_FIRST_READ;
end if;
else
init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
end if;
 
when INIT_DUMMY_FIRST_READ =>
init_next_state <= INIT_DUMMY_READ_WAIT;
 
when INIT_DUMMY_READ =>
if((burst_cnt = "001") and (phy_dly_slct_done = '0')) then
init_next_state <= INIT_DUMMY_READ;
else
init_next_state <= INIT_DUMMY_READ_WAIT;
end if;
 
when INIT_DUMMY_READ_WAIT =>
if (phy_dly_slct_done = '1') then
if(count5 = cntnext) then
if(auto_ref = '1') then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_DUMMY_WRITE1;
end if;
else
init_next_state <= INIT_DUMMY_READ_WAIT;
end if;
else
init_next_state <= INIT_DUMMY_READ;
end if;
 
when INIT_DUMMY_WRITE1 =>
if (burst_cnt = "0001") then
init_next_state <= INIT_DUMMY_WRITE2;
else
init_next_state <= INIT_DUMMY_WRITE_READ;
end if;
 
 
when INIT_DUMMY_WRITE2 =>
init_next_state <= INIT_DUMMY_WRITE_READ;
 
when INIT_DUMMY_WRITE_READ =>
if (count5 = cntnext) then
init_next_state <= INIT_PATTERN_READ1;
else
init_next_state <= INIT_DUMMY_WRITE_READ;
end if;
 
when INIT_PATTERN_READ1 =>
if (burst_cnt = "0001") then
init_next_state <= INIT_PATTERN_READ2;
else
init_next_state <= INIT_PATTERN_READ_WAIT;
end if;
 
when INIT_PATTERN_READ2 =>
init_next_state <= INIT_PATTERN_READ_WAIT;
 
when INIT_PATTERN_READ_WAIT =>
if(comp_done = '1') then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_PATTERN_READ_WAIT;
end if;
 
 
when INIT_PRECHARGE => init_next_state <= INIT_PRECHARGE_WAIT;
 
 
when INIT_PRECHARGE_WAIT =>
if (count5 = cntnext) then
if (auto_ref = '1' and dummy_write_flag = '1') then
init_next_state <= INIT_AUTO_REFRESH;
else
init_next_state <= INIT_IDLE;
end if;
else
init_next_state <= INIT_PRECHARGE_WAIT;
end if;
 
when INIT_LOAD_MODE_REG_ST => init_next_state <= INIT_MODE_REGISTER_WAIT;
 
 
when INIT_MODE_REGISTER_WAIT =>
if (count5 = cntnext) then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_MODE_REGISTER_WAIT;
end if;
 
when INIT_AUTO_REFRESH => init_next_state <= INIT_AUTO_REFRESH_WAIT;
 
when INIT_AUTO_REFRESH_WAIT =>
if ((count5 = cntnext) and (phy_dly_slct_done = '1')) then
init_next_state <= INIT_DUMMY_ACTIVE;
elsif (count5 = cntnext) then
init_next_state <= INIT_IDLE;
else
init_next_state <= INIT_AUTO_REFRESH_WAIT;
end if;
 
when others => init_next_state <= INIT_IDLE;
 
end case;
end process;
 
--Main control state machine
process (act_r, lmr_pre_ref_act_cmd_r, lmr_r, rd
, rd_r, ref_r, wr, wr_r, auto_ref
, conflict_detect, conflict_detect_r
, conflict_resolved_r, idle_cnt, mrd_count, ras_count, rcd_count
, rd_to_wr_count, read_burst_cnt, rfc_count, rp_count
, rtp_count, state, wr_to_rd_count, wrburst_cnt
, wtp_count, burst_cnt, init_done_int, af_empty_r)
begin
 
next_state <= state;
case state is
when IDLE =>
if ((conflict_detect_r='1' or lmr_pre_ref_act_cmd_r='1' or auto_ref='1')
and ras_count = "0000" and init_done_int = '1') then
next_state <= PRECHARGE;
elsif ((wr_r = '1' or rd_r = '1') and (ras_count = "0000")) then
next_state <= ACTIVE;
end if;
 
when LOAD_MODE_REG_ST => next_state <= MODE_REGISTER_WAIT;
 
when MODE_REGISTER_WAIT =>
if (mrd_count = '0') then
next_state <= IDLE;
else
next_state <= MODE_REGISTER_WAIT;
end if;
 
when PRECHARGE => next_state <= PRECHARGE_WAIT;
 
 
when PRECHARGE_WAIT =>
if (rp_count = "000") then
if ((auto_ref or ref_r) = '1') then
next_state <= AUTO_REFRESH;
elsif (lmr_r = '1') then
next_state <= LOAD_MODE_REG_ST;
elsif ((conflict_detect_r or act_r) = '1') then
next_state <= ACTIVE;
else
next_state <= IDLE;
end if;
else
next_state <= PRECHARGE_WAIT;
end if;
 
when AUTO_REFRESH => next_state <= AUTO_REFRESH_WAIT;
 
when AUTO_REFRESH_WAIT =>
if ((rfc_count = "00001") and (conflict_detect_r = '1')) then
next_state <= ACTIVE;
elsif (rfc_count = "00001") then
next_state <= IDLE;
else
next_state <= AUTO_REFRESH_WAIT;
end if;
 
when ACTIVE => next_state <= ACTIVE_WAIT;
 
 
when ACTIVE_WAIT =>
if (rcd_count = "000") then
if(wr = '1') then
next_state <= FIRST_WRITE;
elsif (rd = '1') then
next_state <= FIRST_READ;
else
next_state <= IDLE;
end if;
else
next_state <= ACTIVE_WAIT;
end if;
 
when FIRST_WRITE =>
if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
(auto_ref = '1')) or rd = '1') then
next_state <= WRITE_WAIT;
elsif((burst_cnt = "001") and (wr = '1')) then
next_state <= BURST_WRITE;
else
next_state <= WRITE_WAIT;
end if;
 
when BURST_WRITE =>
if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
(auto_ref = '1')) or (rd = '1')) then
next_state <= WRITE_WAIT;
elsif((burst_cnt = "001") and (wr = '1')) then
next_state <= BURST_WRITE;
else
next_state <= WRITE_WAIT;
end if;
 
when WRITE_WAIT =>
if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or
(auto_ref = '1')) then
if ((wtp_count = "0000") and (ras_count = "0000")) then
next_state <= PRECHARGE;
else
next_state <= WRITE_WAIT;
end if;
elsif (rd = '1') then
next_state <= WRITE_READ;
elsif ((wr = '1') and (wrburst_cnt = "010")) then
next_state <= BURST_WRITE;
elsif((wr = '1') and (wrburst_cnt = "000")) then
next_state <= FIRST_WRITE;
elsif (idle_cnt = "0000") then
next_state <= PRECHARGE;
else
next_state <= WRITE_WAIT;
end if;
 
when WRITE_READ =>
if (wr_to_rd_count = "0000") then
next_state <= FIRST_READ;
else
next_state <= WRITE_READ;
end if;
 
when FIRST_READ =>
if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
(auto_ref = '1')) or (wr = '1')) then
next_state <= READ_WAIT;
elsif((burst_cnt = "001") and (rd = '1')) then
next_state <= BURST_READ;
else
next_state <= READ_WAIT;
end if;
 
when BURST_READ =>
if((((conflict_detect = '1') and (conflict_resolved_r = '0'))or
(auto_ref = '1')) or (wr = '1')) then
next_state <= READ_WAIT;
elsif((burst_cnt = "001") and (rd = '1')) then
next_state <= BURST_READ;
else
next_state <= READ_WAIT;
end if;
 
when READ_WAIT =>
if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or
(auto_ref = '1')) then
if(rtp_count = "0000" and ras_count = "0000") then
next_state <= PRECHARGE;
else
next_state <= READ_WAIT;
end if;
elsif (wr = '1') then
next_state <= READ_WRITE;
elsif ((rd = '1') and (read_burst_cnt <= "010")) then
if(af_empty_r = '1') then
next_state <= FIRST_READ;
else
next_state <= BURST_READ;
end if;
elsif (idle_cnt = "0000") then
next_state <= PRECHARGE;
else
next_state <= READ_WAIT;
end if;
 
 
when READ_WRITE =>
if (rd_to_wr_count = "0000") then
next_state <= FIRST_WRITE;
else
next_state <= READ_WRITE;
end if;
 
when others => next_state <= IDLE;
 
end case;
end process;
 
 
 
--register command outputs
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
state_r2 <= "00000";
else
state_r2 <= state;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
init_state_r2 <= "00000";
else
init_state_r2 <= init_state;
end if;
end if;
end process;
 
 
-- commands to the memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_ras_r <= '1';
elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (state = ACTIVE)
or (state = AUTO_REFRESH) or (init_state = INIT_LOAD_MODE_REG_ST)
or (init_state = INIT_PRECHARGE) or (init_state = INIT_AUTO_REFRESH)
or (init_state = INIT_DUMMY_ACTIVE)) then
ddr_ras_r <= '0';
else ddr_ras_r <= '1';
end if;
end if;
end process;
 
-- commands to the memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_cas_r <= '1';
elsif ((state = LOAD_MODE_REG_ST) or (init_state = INIT_LOAD_MODE_REG_ST)
or (read_write_state = '1') or (init_state = INIT_DUMMY_FIRST_READ)
or (dummy_write_state = '1') or (state = AUTO_REFRESH)
or (init_state = INIT_AUTO_REFRESH) or (init_state = INIT_DUMMY_READ)
or (pattern_read_state = '1')) then
ddr_cas_r <= '0';
elsif ((state = ACTIVE_WAIT) or (init_state = INIT_DUMMY_ACTIVE_WAIT)) then
ddr_cas_r <= '1';
else
ddr_cas_r <= '1';
end if;
end if;
end process;
 
-- commands to the memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_we_r <= '1';
elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or
(init_state = INIT_LOAD_MODE_REG_ST) or
(init_state = INIT_PRECHARGE) or (write_state = '1')
or (dummy_write_state = '1')) then
ddr_we_r <= '0';
else ddr_we_r <= '1';
end if;
end if;
end process;
 
--register commands to the memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_ras_r2 <= '1';
ddr_cas_r2 <= '1';
ddr_we_r2 <= '1';
else
ddr_ras_r2 <= ddr_ras_r;
ddr_cas_r2 <= ddr_cas_r;
ddr_we_r2 <= ddr_we_r;
end if;
end if;
end process;
 
--register commands to the memory
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if (rst_r = '1') then
ddr_ras_r3 <= '1';
ddr_cas_r3 <= '1';
ddr_we_r3 <= '1';
else
ddr_ras_r3 <= ddr_ras_r2;
ddr_cas_r3 <= ddr_cas_r2;
ddr_we_r3 <= ddr_we_r2;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
row_addr_r(ROW_ADDRESS - 1 downto 0) <= (others => '0');
else
row_addr_r(ROW_ADDRESS - 1 downto 0) <= af_addr((ROW_ADDRESS + COL_AP_WIDTH)
-1 downto COL_AP_WIDTH);
end if;
end if;
end process;
 
-- address during init
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_address_init_r <= (others => '0');
elsif (init_memory = '1') then
if (init_state_r2 = INIT_PRECHARGE) then
ddr_address_init_r <= ADD_CONST1((ROW_ADDRESS - 1) downto 0);
--A10 = 1 for precharge all
elsif ((init_state_r2=INIT_LOAD_MODE_REG_ST) and
(init_count_cp="0011")) then
ddr_address_init_r <= ext_mode_reg; -- A0 = 0 for DLL enable
elsif ((init_state_r2=INIT_LOAD_MODE_REG_ST) and
(init_count_cp = "0100")) then
ddr_address_init_r <= ADD_CONST2((ROW_ADDRESS - 1) downto 0) or
load_mode_reg; -- A8 = 1 for DLL reset
elsif ((init_state_r2 = INIT_LOAD_MODE_REG_ST) and
(init_count_cp = "1001")) then
ddr_address_init_r <= ADD_CONST5((ROW_ADDRESS - 1) downto 0) and
load_mode_reg; -- A8 = 0 to deactivate DLL reset
else
ddr_address_init_r <= ADD_CONST3((ROW_ADDRESS - 1) downto 0);
end if;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_address_r1 <= (others => '0');
elsif ((init_state_r2=INIT_DUMMY_WRITE1) or
(init_state_r2=INIT_PATTERN_READ1)) then
ddr_address_r1 <= (others => '0');
elsif ((init_state_r2=INIT_DUMMY_WRITE2) or
(init_state_r2 = INIT_PATTERN_READ2)) then
ddr_address_r1 <= ddr_address_bl;
elsif ((state_r2 = ACTIVE)) then
ddr_address_r1 <= row_addr_r;
elsif (read_write_state_r2 = '1') then
ddr_address_r1 <= af_addr_r(ROW_ADDRESS - 1 downto 0) and
ADD_CONST4((ROW_ADDRESS - 1) downto 0);
elsif ((state_r2 = PRECHARGE) or (init_state_r2 = INIT_PRECHARGE)) then
ddr_address_r1 <= ADD_CONST1((ROW_ADDRESS - 1) downto 0); --X"0400";
elsif ((state_r2=LOAD_MODE_REG_ST) or (init_state_r2=INIT_LOAD_MODE_REG_ST))then
ddr_address_r1 <= af_addr_r(ROW_ADDRESS - 1 downto 0);
else
ddr_address_r1 <= ADD_CONST3((ROW_ADDRESS - 1) downto 0); --X"0000";
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_address_r2 <= (others => '0');
elsif(init_memory = '1') then
ddr_address_r2 <= ddr_address_init_r;
else
ddr_address_r2 <= ddr_address_r1;
end if;
end if;
end process;
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= (others => '0');
elsif (init_memory = '1' and (state_r2 = LOAD_MODE_REG_ST or
init_state_r2 = INIT_LOAD_MODE_REG_ST)) then
if (init_count_cp = "0011") then
ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= "01"; --X"1";
else
ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= "00"; --X"0";
end if;
elsif ((state_r2 = ACTIVE) or (init_state_r2 = INIT_DUMMY_ACTIVE) or
(state_r2=LOAD_MODE_REG_ST) or (init_state_r2=INIT_LOAD_MODE_REG_ST)
or (((state_r2 = PRECHARGE) or (init_state_r2=INIT_PRECHARGE))
and pre_r = '1')) then
ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= af_addr((BANK_ADDRESS+ROW_ADDRESS+
COL_AP_WIDTH)-1 downto
(COL_AP_WIDTH+ROW_ADDRESS));
else ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= ddr_ba_r1(BANK_ADDRESS - 1 downto 0);
end if;
end if;
end process;
 
process(clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_ba_r2 <= (others => '0');
else
ddr_ba_r2 <= ddr_ba_r1;
end if;
end if;
end process;
 
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
conflict_resolved_r <= '0';
else
if (((state = PRECHARGE_WAIT) or (init_state = INIT_PRECHARGE_WAIT))
and (conflict_detect_r = '1')) then
conflict_resolved_r <= '1';
elsif(af_rden = '1') then
conflict_resolved_r <= '0';
end if;
end if;
end if;
end process;
 
 
process (clk_0)
begin
if(clk_0'event and clk_0 = '1') then
if(rst_r = '1') then
ddr_cke_r <= '0';
else
if(done_200us = '1') then
ddr_cke_r <= '1';
end if;
end if;
end if;
end process;
 
 
ctrl_ddr_address(ROW_ADDRESS - 1 downto 0) <= ddr_address_r2(ROW_ADDRESS - 1 downto 0);
ctrl_ddr_ba (BANK_ADDRESS - 1 downto 0) <= ddr_ba_r2(BANK_ADDRESS - 1 downto 0);
ctrl_ddr_ras_l <= ddr_ras_r3;
ctrl_ddr_cas_l <= ddr_cas_r3;
ctrl_ddr_we_l <= ddr_we_r3;
ctrl_ddr_cs_l <= '0';
 
ctrl_ddr_cke <= ddr_cke_r;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/MIG_rd_data_0/MIG_pattern_compare8.vhd
0,0 → 1,241
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_pattern_compare8.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Compares the IOB output 8 bit data of one bank that is read
-- data during the intilaization to get the delay for the data
-- with respect to the command issued.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_pattern_compare8 is
port(
clk : in std_logic;
rst : in std_logic;
ctrl_rden : in std_logic;
rd_data_rise : in std_logic_vector(7 downto 0);
rd_data_fall : in std_logic_vector(7 downto 0);
comp_done : out std_logic;
first_rising : out std_logic;
rise_clk_count : out std_logic_vector(2 downto 0);
fall_clk_count : out std_logic_vector(2 downto 0)
);
end MIG_pattern_compare8;
 
architecture arch of MIG_pattern_compare8 is
 
constant IDLE : std_logic_vector(1 downto 0) := "00";
constant FIRST_DATA : std_logic_vector(1 downto 0) := "01";
constant SECOND_DATA : std_logic_vector(1 downto 0) := "10";
constant COMP_OVER : std_logic_vector(1 downto 0) := "11";
 
signal state_rise : std_logic_vector(1 downto 0);
signal state_fall : std_logic_vector(1 downto 0);
signal next_state_rise : std_logic_vector(1 downto 0);
signal next_state_fall : std_logic_vector(1 downto 0);
signal rise_clk_cnt : std_logic_vector(2 downto 0);
signal fall_clk_cnt : std_logic_vector(2 downto 0);
signal ctrl_rden_r : std_logic;
signal pattern_rise1 : std_logic_vector(7 downto 0);
signal pattern_fall1 : std_logic_vector(7 downto 0);
signal pattern_rise2 : std_logic_vector(7 downto 0);
signal pattern_fall2 : std_logic_vector(7 downto 0);
signal rd_data_rise_r2 : std_logic_vector(7 downto 0);
signal rd_data_fall_r2 : std_logic_vector(7 downto 0);
signal rst_r : std_logic;
begin
 
pattern_rise1 <= X"AA";
pattern_fall1 <= X"55";
pattern_rise2 <= X"99";
pattern_fall2 <= X"66";
 
process(clk)
begin
if(clk'event and clk = '1') then
rst_r <= rst;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
state_rise <= IDLE;
else
state_rise <= next_state_rise;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
state_fall <= IDLE;
else
state_fall <= next_state_fall;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
ctrl_rden_r <= '0';
else
ctrl_rden_r <= ctrl_rden;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
rise_clk_cnt <= "000";
elsif((state_rise = FIRST_DATA) or (state_rise = SECOND_DATA)) then
rise_clk_cnt <= rise_clk_cnt + '1';
end if;
end if;
end process;
 
rise_clk_count <= rise_clk_cnt when (state_rise = COMP_OVER) else "000";
 
comp_done <= '1' when ((state_rise = COMP_OVER) and (state_fall = COMP_OVER))
else '0';
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
fall_clk_cnt <= "000";
elsif((state_fall = FIRST_DATA) or (state_fall = SECOND_DATA)) then
fall_clk_cnt <= fall_clk_cnt + '1';
end if;
end if;
end process;
 
fall_clk_count <= fall_clk_cnt when (state_fall = COMP_OVER) else "000";
 
process(clk)
begin
if (clk = '1' and clk'event) then
if (rst_r = '1') then
first_rising <= '0';
elsif(state_rise = SECOND_DATA and rd_data_rise = pattern_fall2
and rd_data_rise_r2 = pattern_fall1) then
first_rising <= '1';
end if;
end if;
end process;
 
process(clk)
begin
if (clk = '1' and clk'event) then
if (rst_r = '1') then
rd_data_rise_r2 <= (others => '0');
rd_data_fall_r2 <= (others => '0');
else
rd_data_rise_r2 <= rd_data_rise;
rd_data_fall_r2 <= rd_data_fall;
end if;
end if;
end process;
 
process(ctrl_rden_r, state_rise, rd_data_rise, rd_data_rise_r2, pattern_rise1,
pattern_fall1, pattern_rise2, pattern_fall2, rst_r)
begin
if(rst_r = '1') then
next_state_rise <= IDLE;
else
case state_rise is
when IDLE =>
if(ctrl_rden_r = '1') then
next_state_rise <= FIRST_DATA;
else
next_state_rise <= IDLE;
end if;
 
when FIRST_DATA =>
if((rd_data_rise = pattern_rise1) or (rd_data_rise = pattern_fall1)) then
next_state_rise <= SECOND_DATA;
else
next_state_rise <= FIRST_DATA;
end if;
 
when SECOND_DATA =>
if(((rd_data_rise=pattern_rise2) and (rd_data_rise_r2=pattern_rise1)) or
((rd_data_rise=pattern_fall2) and (rd_data_rise_r2=pattern_fall1))) then
next_state_rise <= COMP_OVER;
else
next_state_rise <= SECOND_DATA;
end if;
 
when COMP_OVER =>
next_state_rise <= COMP_OVER;
 
when others =>
next_state_rise <= IDLE;
end case;
end if;
end process;
 
process(ctrl_rden_r, state_fall, rd_data_fall, rd_data_fall_r2, pattern_rise1,
pattern_fall1, pattern_rise2, pattern_fall2, rst_r)
begin
if(rst_r = '1') then
next_state_fall <= IDLE;
else
case state_fall is
when IDLE =>
if(ctrl_rden_r = '1') then
next_state_fall <= FIRST_DATA;
else
next_state_fall <= IDLE;
end if;
 
when FIRST_DATA =>
if((rd_data_fall = pattern_rise1) or (rd_data_fall = pattern_fall1)) then
next_state_fall <= SECOND_DATA;
else
next_state_fall <= FIRST_DATA;
end if;
 
when SECOND_DATA =>
if(((rd_data_fall=pattern_rise2) and (rd_data_fall_r2=pattern_rise1)) or
((rd_data_fall=pattern_fall2) and (rd_data_fall_r2=pattern_fall1))) then
next_state_fall <= COMP_OVER;
else
next_state_fall <= SECOND_DATA;
end if;
 
when COMP_OVER =>
next_state_fall <= COMP_OVER;
 
when others =>
next_state_fall <= IDLE;
end case;
end if;
end process;
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/MIG_rd_data_0/MIG_rd_data_0.vhd
0,0 → 1,503
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_rd_data_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: The delay between the read data with respect to the command
-- issued is calculted in terms of no. of clocks. This data is
-- then stored into the FIFOs and then read back and given as
-- the ouput for comparison.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_rd_data_0 is
port(
clk : in std_logic;
reset : in std_logic;
ctrl_rden : in std_logic;
read_data_rise : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fall : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fifo_rise : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fifo_fall : out std_logic_vector(DATA_WIDTH - 1 downto 0);
comp_done : out std_logic;
read_data_valid : out std_logic
);
end MIG_rd_data_0;
 
architecture arch of MIG_rd_data_0 is
 
component MIG_rd_data_fifo_0
port(
clk : in std_logic;
reset : in std_logic;
read_en_delayed_rise : in std_logic;
read_en_delayed_fall : in std_logic;
first_rising : in std_logic;
read_data_rise : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_fall : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
fifo_rd_enable : in std_logic;
read_data_fifo_rise : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_fifo_fall : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_valid : out std_logic
);
end component;
 
component MIG_pattern_compare8
port(
clk : in std_logic;
rst : in std_logic;
ctrl_rden : in std_logic;
rd_data_rise : in std_logic_vector(7 downto 0);
rd_data_fall : in std_logic_vector(7 downto 0);
comp_done : out std_logic;
first_rising : out std_logic;
rise_clk_count : out std_logic_vector(2 downto 0);
fall_clk_count : out std_logic_vector(2 downto 0)
);
end component;
 
component MIG_pattern_compare4
port(
clk : in std_logic;
rst : in std_logic;
ctrl_rden : in std_logic;
rd_data_rise : in std_logic_vector(3 downto 0);
rd_data_fall : in std_logic_vector(3 downto 0);
comp_done : out std_logic;
first_rising : out std_logic;
rise_clk_count : out std_logic_vector(2 downto 0);
fall_clk_count : out std_logic_vector(2 downto 0)
);
end component;
 
signal rd_en_r1 : std_logic_vector(READENABLE - 1 downto 0);
signal rd_en_r2 : std_logic_vector(READENABLE - 1 downto 0);
signal rd_en_r3 : std_logic_vector(READENABLE - 1 downto 0);
signal rd_en_r4 : std_logic_vector(READENABLE - 1 downto 0);
signal rd_en_r5 : std_logic_vector(READENABLE - 1 downto 0);
signal rd_en_r6 : std_logic_vector(READENABLE - 1 downto 0);
signal comp_done_r : std_logic;
signal comp_done_r1 : std_logic;
signal comp_done_r2 : std_logic;
signal rd_en_rise : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);
signal rd_en_fall : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);
signal ctrl_rden1 : std_logic_vector(READENABLE - 1 downto 0);
signal first_rising_rden : std_logic_vector(READENABLE - 1 downto 0);
signal fifo_rd_enable1 : std_logic;
signal fifo_rd_enable : std_logic;
signal rst_r : std_logic;
signal read_data_valid0 : std_logic;
 
 
signal read_data_valid1 : std_logic;
 
 
signal read_data_valid2 : std_logic;
 
 
signal read_data_valid3 : std_logic;
 
signal comp_done_0 : std_logic;
signal rise_clk_count0 : std_logic_vector(2 downto 0);
signal fall_clk_count0 : std_logic_vector(2 downto 0);
 
 
begin
 
ctrl_rden1(0) <= ctrl_rden;
 
read_data_valid <= read_data_valid0;
 
pattern_0 : MIG_pattern_compare8
port map (
clk => clk,
rst => reset,
ctrl_rden => ctrl_rden1(0),
rd_data_rise => read_data_rise(31 downto 24),
rd_data_fall => read_data_fall(31 downto 24),
comp_done => comp_done_0,
first_rising => first_rising_rden(0),
rise_clk_count => rise_clk_count0,
fall_clk_count => fall_clk_count0
);
 
 
process(clk)
begin
if(clk'event and clk = '1') then
rst_r <= reset;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
rd_en_r1 <= (others => '0');
rd_en_r2 <= (others => '0');
rd_en_r3 <= (others => '0');
rd_en_r4 <= (others => '0');
rd_en_r5 <= (others => '0');
rd_en_r6 <= (others => '0');
else
rd_en_r1 <= ctrl_rden1;
rd_en_r2 <= rd_en_r1;
rd_en_r3 <= rd_en_r2;
rd_en_r4 <= rd_en_r3;
rd_en_r5 <= rd_en_r4;
rd_en_r6 <= rd_en_r5;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
comp_done_r <= '0';
comp_done_r1 <= '0';
comp_done_r2 <= '0';
else
comp_done_r <= comp_done_0 ;
comp_done_r1 <= comp_done_r;
comp_done_r2 <= comp_done_r1;
end if;
end if;
end process;
 
comp_done <= '0' when rst_r = '1' else
comp_done_0 ;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_rise(0) <= '0';
elsif(comp_done_r2 = '1') then
case rise_clk_count0 is
when "011" =>
rd_en_rise(0) <= rd_en_r2(0);
 
when "100" =>
rd_en_rise(0) <= rd_en_r3(0);
 
when "101" =>
rd_en_rise(0) <= rd_en_r4(0);
 
when "110" =>
rd_en_rise(0) <= rd_en_r5(0);
 
when "111" =>
rd_en_rise(0) <= rd_en_r6(0);
 
when others =>
rd_en_rise(0) <= '0';
end case;
end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_fall(0) <= '0';
elsif(comp_done_r2 = '1') then
case fall_clk_count0 is
when "011" =>
rd_en_fall(0) <= rd_en_r2(0);
 
when "100" =>
rd_en_fall(0) <= rd_en_r3(0);
 
when "101" =>
rd_en_fall(0) <= rd_en_r4(0);
 
when "110" =>
rd_en_fall(0) <= rd_en_r5(0);
 
when "111" =>
rd_en_fall(0) <= rd_en_r6(0);
 
when others =>
rd_en_fall(0) <= '0';
end case;
end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_rise(1) <= '0';
elsif(comp_done_r2 = '1') then
case rise_clk_count0 is
when "011" =>
rd_en_rise(1) <= rd_en_r2(0);
 
when "100" =>
rd_en_rise(1) <= rd_en_r3(0);
 
when "101" =>
rd_en_rise(1) <= rd_en_r4(0);
 
when "110" =>
rd_en_rise(1) <= rd_en_r5(0);
 
when "111" =>
rd_en_rise(1) <= rd_en_r6(0);
 
when others =>
rd_en_rise(1) <= '0';
end case;
end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_fall(1) <= '0';
elsif(comp_done_r2 = '1') then
case fall_clk_count0 is
when "011" =>
rd_en_fall(1) <= rd_en_r2(0);
 
when "100" =>
rd_en_fall(1) <= rd_en_r3(0);
 
when "101" =>
rd_en_fall(1) <= rd_en_r4(0);
 
when "110" =>
rd_en_fall(1) <= rd_en_r5(0);
 
when "111" =>
rd_en_fall(1) <= rd_en_r6(0);
 
when others =>
rd_en_fall(1) <= '0';
end case;
end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_rise(2) <= '0';
elsif(comp_done_r2 = '1') then
case rise_clk_count0 is
when "011" =>
rd_en_rise(2) <= rd_en_r2(0);
 
when "100" =>
rd_en_rise(2) <= rd_en_r3(0);
 
when "101" =>
rd_en_rise(2) <= rd_en_r4(0);
 
when "110" =>
rd_en_rise(2) <= rd_en_r5(0);
 
when "111" =>
rd_en_rise(2) <= rd_en_r6(0);
 
when others =>
rd_en_rise(2) <= '0';
end case;
end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_fall(2) <= '0';
elsif(comp_done_r2 = '1') then
case fall_clk_count0 is
when "011" =>
rd_en_fall(2) <= rd_en_r2(0);
 
when "100" =>
rd_en_fall(2) <= rd_en_r3(0);
 
when "101" =>
rd_en_fall(2) <= rd_en_r4(0);
 
when "110" =>
rd_en_fall(2) <= rd_en_r5(0);
 
when "111" =>
rd_en_fall(2) <= rd_en_r6(0);
 
when others =>
rd_en_fall(2) <= '0';
end case;
end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_rise(3) <= '0';
elsif(comp_done_r2 = '1') then
case rise_clk_count0 is
when "011" =>
rd_en_rise(3) <= rd_en_r2(0);
 
when "100" =>
rd_en_rise(3) <= rd_en_r3(0);
 
when "101" =>
rd_en_rise(3) <= rd_en_r4(0);
 
when "110" =>
rd_en_rise(3) <= rd_en_r5(0);
 
when "111" =>
rd_en_rise(3) <= rd_en_r6(0);
 
when others =>
rd_en_rise(3) <= '0';
end case;
end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(rst_r = '1') then
rd_en_fall(3) <= '0';
elsif(comp_done_r2 = '1') then
case fall_clk_count0 is
when "011" =>
rd_en_fall(3) <= rd_en_r2(0);
 
when "100" =>
rd_en_fall(3) <= rd_en_r3(0);
 
when "101" =>
rd_en_fall(3) <= rd_en_r4(0);
 
when "110" =>
rd_en_fall(3) <= rd_en_r5(0);
 
when "111" =>
rd_en_fall(3) <= rd_en_r6(0);
 
when others =>
rd_en_fall(3) <= '0';
end case;
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if(rst_r = '1') then
fifo_rd_enable1 <= '0';
fifo_rd_enable <= '0';
else
fifo_rd_enable1 <= rd_en_rise(0);
fifo_rd_enable <= fifo_rd_enable1;
end if;
end if;
end process;
 
rd_data_fifo0: MIG_rd_data_fifo_0
port map (
clk => clk,
reset => reset,
read_en_delayed_rise => rd_en_rise(0),
read_en_delayed_fall => rd_en_fall(0),
first_rising => first_rising_rden(0),
read_data_rise => read_data_rise(7 downto 0),
read_data_fall => read_data_fall(7 downto 0),
fifo_rd_enable => fifo_rd_enable,
read_data_fifo_rise => read_data_fifo_rise(7 downto 0),
read_data_fifo_fall => read_data_fifo_fall(7 downto 0),
read_data_valid => read_data_valid0
);
 
 
rd_data_fifo1: MIG_rd_data_fifo_0
port map (
clk => clk,
reset => reset,
read_en_delayed_rise => rd_en_rise(1),
read_en_delayed_fall => rd_en_fall(1),
first_rising => first_rising_rden(0),
read_data_rise => read_data_rise(15 downto 8),
read_data_fall => read_data_fall(15 downto 8),
fifo_rd_enable => fifo_rd_enable,
read_data_fifo_rise => read_data_fifo_rise(15 downto 8),
read_data_fifo_fall => read_data_fifo_fall(15 downto 8),
read_data_valid => read_data_valid1
);
 
 
rd_data_fifo2: MIG_rd_data_fifo_0
port map (
clk => clk,
reset => reset,
read_en_delayed_rise => rd_en_rise(2),
read_en_delayed_fall => rd_en_fall(2),
first_rising => first_rising_rden(0),
read_data_rise => read_data_rise(23 downto 16),
read_data_fall => read_data_fall(23 downto 16),
fifo_rd_enable => fifo_rd_enable,
read_data_fifo_rise => read_data_fifo_rise(23 downto 16),
read_data_fifo_fall => read_data_fifo_fall(23 downto 16),
read_data_valid => read_data_valid2
);
 
 
rd_data_fifo3: MIG_rd_data_fifo_0
port map (
clk => clk,
reset => reset,
read_en_delayed_rise => rd_en_rise(3),
read_en_delayed_fall => rd_en_fall(3),
first_rising => first_rising_rden(0),
read_data_rise => read_data_rise(31 downto 24),
read_data_fall => read_data_fall(31 downto 24),
fifo_rd_enable => fifo_rd_enable,
read_data_fifo_rise => read_data_fifo_rise(31 downto 24),
read_data_fifo_fall => read_data_fifo_fall(31 downto 24),
read_data_valid => read_data_valid3
);
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/MIG_rd_data_0/MIG_rd_data_fifo_0/MIG_rd_data_fifo_0.vhd
0,0 → 1,205
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_rd_data_fifo_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the distributed RAM which stores the read data
-- from the memory.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_rd_data_fifo_0 is
port(
clk : in std_logic;
reset : in std_logic;
read_en_delayed_rise : in std_logic;
read_en_delayed_fall : in std_logic;
first_rising : in std_logic;
read_data_rise : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_fall : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
fifo_rd_enable : in std_logic;
read_data_fifo_rise : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_fifo_fall : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
read_data_valid : out std_logic
);
end MIG_rd_data_fifo_0;
 
architecture arch of MIG_rd_data_fifo_0 is
 
component MIG_RAM_D_0
port(
dpo : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
dpra0 : in std_logic;
dpra1 : in std_logic;
dpra2 : in std_logic;
dpra3 : in std_logic;
wclk : in std_logic;
we : in std_logic
);
end component;
 
signal fifos_data_out1 : std_logic_vector((MEMORY_WIDTH*2 - 1) downto 0);
signal fifo_rd_addr : std_logic_vector(3 downto 0);
signal rise0_wr_addr : std_logic_vector(3 downto 0);
signal fall0_wr_addr : std_logic_vector(3 downto 0);
signal fifo_rd_en : std_logic;
signal fifo_rd_en_r1 : std_logic;
signal fifo_rd_en_r2 : std_logic;
signal rise_fifo_data : std_logic_vector((MEMORY_WIDTH - 1) downto 0);
signal fall_fifo_data : std_logic_vector((MEMORY_WIDTH - 1) downto 0);
signal rise_fifo_out : std_logic_vector((MEMORY_WIDTH - 1) downto 0);
signal fall_fifo_out : std_logic_vector((MEMORY_WIDTH - 1) downto 0);
signal rst_r : std_logic;
 
begin
 
read_data_valid <= fifo_rd_en_r2;
read_data_fifo_fall <= fifos_data_out1(MEMORY_WIDTH - 1 downto 0);
read_data_fifo_rise <= fifos_data_out1((MEMORY_WIDTH*2 - 1) downto MEMORY_WIDTH);
 
-- Read Pointer and fifo data output sequencing
 
-- Read Enable generation for fifos based on write enable
 
 
process( clk)
begin
if(clk'event and clk = '1') then
rst_r <= reset;
end if;
end process;
 
process ( clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
fifo_rd_en <= '0';
fifo_rd_en_r1 <= '0';
fifo_rd_en_r2 <= '0';
else
fifo_rd_en <= fifo_rd_enable;
fifo_rd_en_r1 <= fifo_rd_en;
fifo_rd_en_r2 <= fifo_rd_en_r1;
end if;
end if;
end process;
 
-- Write Pointer increment for FIFOs
 
process ( clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
rise0_wr_addr <= "0000";
elsif (read_en_delayed_rise = '1') then
rise0_wr_addr <= rise0_wr_addr + '1';
end if;
end if;
end process;
 
process ( clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
fall0_wr_addr <= "0000";
elsif (read_en_delayed_fall = '1') then
fall0_wr_addr <= fall0_wr_addr + '1';
end if;
end if;
end process;
 
--********** FIFO Data Output Sequencing ***********
 
process ( clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
rise_fifo_data <= (others => '0');
fall_fifo_data <= (others => '0');
fifo_rd_addr <= "0000";
elsif (fifo_rd_en = '1') then
rise_fifo_data(MEMORY_WIDTH - 1 downto 0) <= rise_fifo_out(MEMORY_WIDTH - 1 downto 0);
fall_fifo_data(MEMORY_WIDTH - 1 downto 0) <= fall_fifo_out(MEMORY_WIDTH - 1 downto 0);
fifo_rd_addr(3 downto 0) <= fifo_rd_addr(3 downto 0) + '1';
end if;
end if;
end process;
 
process ( clk)
begin
if(clk'event and clk = '1') then
if (rst_r = '1') then
fifos_data_out1((MEMORY_WIDTH*2 - 1) downto 0) <= (others => '0');
elsif (fifo_rd_en_r1 = '1') then
if (first_rising = '1') then
fifos_data_out1((MEMORY_WIDTH*2 - 1) downto 0) <= fall_fifo_data((MEMORY_WIDTH - 1) downto 0)
& rise_fifo_data((MEMORY_WIDTH - 1) downto 0);
else
fifos_data_out1((MEMORY_WIDTH*2 - 1) downto 0) <= rise_fifo_data((MEMORY_WIDTH - 1) downto 0)
& fall_fifo_data((MEMORY_WIDTH - 1) downto 0);
end if;
end if;
end if;
end process;
 
--******************************************************************************
-- Distributed RAM 4 bit wide FIFO instantiations (2 FIFOs per strobe, rising
-- edge data fifo and falling edge data fifo)
--******************************************************************************
-- FIFOs associated with DQS(0)
 
ram_rise0: MIG_RAM_D_0 port map
(
dpo => rise_fifo_out(MEMORY_WIDTH - 1 downto 0),
a0 => rise0_wr_addr(0),
a1 => rise0_wr_addr(1),
a2 => rise0_wr_addr(2),
a3 => rise0_wr_addr(3),
d => read_data_rise(MEMORY_WIDTH - 1 downto 0),
dpra0 => fifo_rd_addr(0),
dpra1 => fifo_rd_addr(1),
dpra2 => fifo_rd_addr(2),
dpra3 => fifo_rd_addr(3),
wclk => clk,
we => read_en_delayed_rise
);
 
ram_fall0: MIG_RAM_D_0 port map
(
dpo => fall_fifo_out(MEMORY_WIDTH - 1 downto 0),
a0 => fall0_wr_addr(0),
a1 => fall0_wr_addr(1),
a2 => fall0_wr_addr(2),
a3 => fall0_wr_addr(3),
d => read_data_fall(MEMORY_WIDTH - 1 downto 0),
dpra0 => fifo_rd_addr(0),
dpra1 => fifo_rd_addr(1),
dpra2 => fifo_rd_addr(2),
dpra3 => fifo_rd_addr(3),
wclk => clk,
we => read_en_delayed_fall
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/MIG_rd_data_0/MIG_rd_data_fifo_0/MIG_ram_d_0.vhd
0,0 → 1,68
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_RAM_D_.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Contains the distributed RAM which stores IOB output data that
-- is read from the memory.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_RAM_D_0 is
port(
dpo : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);
dpra0 : in std_logic;
dpra1 : in std_logic;
dpra2 : in std_logic;
dpra3 : in std_logic;
wclk : in std_logic;
we : in std_logic
);
end MIG_RAM_D_0;
 
architecture arch of MIG_RAM_D_0 is
 
begin
 
gen_ram_d: for ram_d_i in 0 to MEMORY_WIDTH-1 generate
RAM16X1D_inst: RAM16X1D
port map (
DPO => dpo(ram_d_i),
SPO => open,
A0 => a0,
A1 => a1,
A2 => a2,
A3 => a3,
D => d(ram_d_i),
DPRA0 => dpra0,
DPRA1 => dpra1,
DPRA2 => dpra2,
DPRA3 => dpra3,
WCLK => wclk,
WE => we
);
end generate;
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/MIG_user_interface_0.vhd
0,0 → 1,131
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_user_interface_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:25 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Interfaces with the user. The user should provide the data and
-- various commands.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_user_interface_0 is
port(
clk : in std_logic;
clk90 : in std_logic;
reset : in std_logic;
ctrl_rden : in std_logic;
read_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);
read_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);
read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
comp_done : out std_logic;
read_data_valid : out std_logic;
af_empty : out std_logic;
af_almost_full : out std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
wdf_almost_full : out std_logic
);
end MIG_user_interface_0;
 
architecture arch of MIG_user_interface_0 is
 
component MIG_rd_data_0
port(
clk : in std_logic;
reset : in std_logic;
ctrl_rden : in std_logic;
read_data_rise : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fall : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fifo_rise : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read_data_fifo_fall : out std_logic_vector(DATA_WIDTH - 1 downto 0);
comp_done : out std_logic;
read_data_valid : out std_logic
);
end component;
 
component MIG_backend_fifos_0
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
af_empty : out std_logic;
af_almost_full : out std_logic;
app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
wdf_almost_full : out std_logic
);
end component;
 
signal read_data_fifo_rise_i : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal read_data_fifo_fall_i : std_logic_vector((DATA_WIDTH - 1) downto 0);
 
begin
 
read_data_fifo_out <= read_data_fifo_rise_i & read_data_fifo_fall_i;
 
rd_data_00 : MIG_rd_data_0
port map (
clk => clk,
reset => reset,
ctrl_rden => ctrl_rden,
read_data_rise => read_data_rise,
read_data_fall => read_data_fall,
read_data_fifo_rise => read_data_fifo_rise_i,
read_data_fifo_fall => read_data_fifo_fall_i,
comp_done => comp_done,
read_data_valid => read_data_valid
);
 
backend_fifos_00 : MIG_backend_fifos_0
port map (
clk0 => clk,
clk90 => clk90,
rst => reset,
app_af_addr => app_af_addr,
app_af_wren => app_af_wren,
ctrl_af_rden => ctrl_af_rden,
af_addr => af_addr,
af_empty => af_empty,
af_almost_full => af_almost_full,
app_wdf_data => app_wdf_data,
app_mask_data => app_mask_data,
app_wdf_wren => app_wdf_wren,
ctrl_wdf_rden => ctrl_wdf_rden,
wdf_data => wdf_data,
mask_data => mask_data,
wdf_almost_full => wdf_almost_full
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/backend_fifos_0/MIG_rd_wr_addr_fifo_0.vhd
0,0 → 1,165
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_rd_wr_addr_fifo_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the block RAM based FIFO to store the user address
-- and the command information.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_rd_wr_addr_fifo_0 is
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
af_empty : out std_logic;
af_almost_full : out std_logic
);
end MIG_rd_wr_addr_fifo_0;
 
architecture arch of MIG_rd_wr_addr_fifo_0 is
 
signal fifo_input_write_addr : std_logic_vector(35 downto 0);
signal fifo_output_write_addr : std_logic_vector(35 downto 0);
signal compare_value_r : std_logic_vector(35 downto 0);
signal app_af_addr_r : std_logic_vector(35 downto 0);
signal fifo_input_addr_r : std_logic_vector(35 downto 0);
signal af_en_r : std_logic;
signal af_en_2r : std_logic;
signal compare_result : std_logic;
signal clk270 : std_logic;
signal af_al_full_0 : std_logic;
signal af_al_full_180 : std_logic;
signal af_al_full_90 : std_logic;
signal af_en_2r_270 : std_logic;
signal fifo_input_270 : std_logic_vector(35 downto 0);
signal rst_r : std_logic;
 
begin
 
fifo_input_write_addr <= compare_result & app_af_addr_r(34 downto 0);
af_addr <= fifo_output_write_addr;
compare_result <= '0' when (compare_value_r((NO_OF_CS + BANK_ADDRESS +
ROW_ADDRESS + COL_AP_WIDTH- 1)
downto COL_AP_WIDTH)
= fifo_input_write_addr((NO_OF_CS + BANK_ADDRESS +
ROW_ADDRESS + COL_AP_WIDTH- 1)
downto COL_AP_WIDTH))
else '1';
 
clk270 <= not clk90;
 
process(clk0)
begin
if(clk0'event and clk0 = '1') then
rst_r <= rst;
end if;
end process;
 
process(clk0)
begin
if(clk0'event and clk0 = '1') then
if(rst_r = '1') then
compare_value_r <= (others => '0');
app_af_addr_r <= (others => '0');
fifo_input_addr_r <= (others => '0');
af_en_r <= '0';
af_en_2r <= '0';
else
if(af_en_r = '1') then
compare_value_r <= fifo_input_write_addr;
end if;
app_af_addr_r <= app_af_addr;
fifo_input_addr_r <= fifo_input_write_addr;
af_en_r <= app_af_wren;
af_en_2r <= af_en_r;
end if;
end if;
end process;
 
-- A fix for FIFO16 according to answer record #22462
 
process(clk270)
begin
if (clk270'event and clk270 = '1') then
af_en_2r_270 <= af_en_2r;
fifo_input_270 <= fifo_input_addr_r;
end if;
end process;
 
-- 3 Filp-flops logic is implemented at output to avoid the timimg errors
 
process(clk0)
begin
if (clk0'event and clk0 = '0') then
af_al_full_180 <= af_al_full_0;
end if;
end process;
 
process(clk90)
begin
if (clk90'event and clk90 = '1') then
af_al_full_90 <= af_al_full_180;
end if;
end process;
 
process(clk0)
begin
if (clk0'event and clk0 = '1') then
af_almost_full <= af_al_full_90;
end if;
end process;
 
-- Read/Write Address FIFO
 
af_fifo16 : FIFO16
generic map (
ALMOST_FULL_OFFSET => X"00F",
ALMOST_EMPTY_OFFSET => X"007",
DATA_WIDTH => 36,
FIRST_WORD_FALL_THROUGH => true
)
 
port map (
ALMOSTEMPTY => open,
ALMOSTFULL => af_al_full_0,
DO => fifo_output_write_addr(31 downto 0),
DOP => fifo_output_write_addr(35 downto 32),
EMPTY => af_empty,
FULL => open,
RDCOUNT => open,
RDERR => open,
WRCOUNT => open,
WRERR => open,
DI => fifo_input_270(31 downto 0),
DIP => fifo_input_270(35 downto 32),
RDCLK => clk0,
RDEN => ctrl_af_rden,
RST => rst_r,
WRCLK => clk270,
WREN => af_en_2r_270
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/backend_fifos_0/MIG_wr_data_fifo_16.vhd
0,0 → 1,105
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_wr_data_fifo_16.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:25 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the block RAM based FIFO to store the user
-- interface data into it and read after a specified amount is
-- already written. The reading starts when the almost full
-- signal is generated whose offset is programmable.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_wr_data_fifo_16 is
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
--Write data fifo signals
app_wdf_data : in std_logic_vector(31 downto 0);
app_mask_data : in std_logic_vector(3 downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector(31 downto 0);
mask_data : out std_logic_vector(3 downto 0);
wr_df_almost_full : out std_logic
);
end MIG_wr_data_fifo_16;
 
architecture arch of MIG_wr_data_fifo_16 is
 
signal ctrl_wdf_rden_270 : std_logic;
signal ctrl_wdf_rden_90 : std_logic;
signal rst_r : std_logic;
 
 
begin
 
 
process(clk0)
begin
if(clk0'event and clk0 = '1') then
rst_r <= rst;
end if;
end process;
 
process(clk90)
begin
if clk90'event and clk90 = '0' then
ctrl_wdf_rden_270 <= ctrl_wdf_rden;
end if;
end process;
 
 
process(clk90)
begin
if clk90'event and clk90 = '1' then
ctrl_wdf_rden_90 <= ctrl_wdf_rden_270;
end if;
end process;
 
 
Wdf_1 : FIFO16
generic map (
ALMOST_FULL_OFFSET => X"00F",
ALMOST_EMPTY_OFFSET => X"007",
DATA_WIDTH => 36,
FIRST_WORD_FALL_THROUGH => false
)
port map (
ALMOSTEMPTY => open,
ALMOSTFULL => wr_df_almost_full,
DO => wdf_data(31 downto 0),
DOP => mask_data(3 downto 0),
EMPTY => open,
FULL => open,
RDCOUNT => open,
RDERR => open,
WRCOUNT => open,
WRERR => open,
DI => app_wdf_data(31 downto 0),
DIP => app_mask_data(3 downto 0),
RDCLK => clk90,
RDEN => ctrl_wdf_rden_90,
RST => rst_r,
WRCLK => clk0,
WREN => app_wdf_wren
);
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_user_interface_0/backend_fifos_0/MIG_backend_fifos_0.vhd
0,0 → 1,147
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_backend_fifos_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: This module instantiates the modules containing internal FIFOs
-- to store the data and the address.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_backend_fifos_0 is
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
af_empty : out std_logic;
af_almost_full : out std_logic;
app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
wdf_almost_full : out std_logic
);
end MIG_backend_fifos_0;
 
architecture arch of MIG_backend_fifos_0 is
 
component MIG_rd_wr_addr_fifo_0
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
af_empty : out std_logic;
af_almost_full : out std_logic
);
end component;
 
component MIG_wr_data_fifo_16
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_wdf_data : in std_logic_vector(31 downto 0);
app_mask_data : in std_logic_vector(3 downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector(31 downto 0);
mask_data : out std_logic_vector(3 downto 0);
wr_df_almost_full : out std_logic
);
end component;
 
component MIG_wr_data_fifo_8
port(
clk0 : in std_logic;
clk90 : in std_logic;
rst : in std_logic;
app_wdf_data : in std_logic_vector(15 downto 0);
app_mask_data : in std_logic_vector(1 downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector(15 downto 0);
mask_data : out std_logic_vector(1 downto 0);
wr_df_almost_full : out std_logic
);
end component;
 
signal wr_df_almost_full_w : std_logic_vector(FIFO_16-1 downto 0);
 
begin
 
wdf_almost_full <= wr_df_almost_full_w(0);
 
rd_wr_addr_fifo_00 : MIG_rd_wr_addr_fifo_0
port map (
clk0 => clk0,
clk90 => clk90,
rst => rst,
app_af_addr => app_af_addr,
app_af_wren => app_af_wren,
ctrl_af_rden => ctrl_af_rden,
af_addr => af_addr,
af_empty => af_empty,
af_almost_full => af_almost_full
);
 
wr_data_fifo_160 : MIG_wr_data_fifo_16
port map (
clk0 => clk0,
clk90 => clk90,
rst => rst,
app_wdf_data => app_wdf_data(31 downto 0),
app_mask_data => app_mask_data(3 downto 0),
app_wdf_wren => app_Wdf_WrEn,
ctrl_wdf_rden => ctrl_Wdf_RdEn,
wdf_data => wdf_data(31 downto 0),
mask_data => mask_data(3 downto 0),
wr_df_almost_full => wr_df_almost_full_w(0)
);
 
 
 
wr_data_fifo_161 : MIG_wr_data_fifo_16
port map (
clk0 => clk0,
clk90 => clk90,
rst => rst,
app_wdf_data => app_wdf_data(63 downto 32),
app_mask_data => app_mask_data(7 downto 4),
app_wdf_wren => app_Wdf_WrEn,
ctrl_wdf_rden => ctrl_Wdf_RdEn,
wdf_data => wdf_data(63 downto 32),
mask_data => mask_data(7 downto 4),
wr_df_almost_full => wr_df_almost_full_w(1)
);
 
 
 
end arch;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Memory Design/MIG_top_00/MIG_top_0.vhd
0,0 → 1,369
-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : $Name: i+IP+131489 $
-- \ \ Application : MIG
-- / / Filename : MIG_top_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the main design logic of memory interface and
-- interfaces with the user.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_top_0 is
port(
clk_0 : in std_logic;
clk_90 : in std_logic;
idelay_ctrl_rdy : in std_logic;
sys_rst : in std_logic;
sys_rst90 : in std_logic;
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_cke : out std_logic;
ddr_cs_n : out std_logic;
ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 -1) downto 0);
 
ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ddr_a : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
wdf_almost_full : out std_logic;
af_almost_full : out std_logic;
burst_length_div2 : out std_logic_vector(2 downto 0);
read_data_valid : out std_logic;
read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_wdf_wren : in std_logic;
init_done : out std_logic;
clk_tb : out std_logic;
reset_tb : out std_logic
);
end MIG_top_0;
 
architecture arch of MIG_top_0 is
 
component MIG_data_path_0
port(
clk : in std_logic;
clk90 : in std_logic;
reset0 : in std_logic;
reset90 : in std_logic;
idelay_ctrl_rdy : in std_logic;
dummy_write_pattern : in std_logic;
ctrl_dummyread_start : in std_logic;
wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
ctrl_wren : in std_logic;
ctrl_dqs_rst : in std_logic;
ctrl_dqs_en : in std_logic;
dqs_delayed : in std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
data_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);
sel_done : out std_logic;
dqs_rst : out std_logic;
dqs_en : out std_logic;
wr_en : out std_logic;
wr_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
);
end component;
 
component MIG_iobs_0
port(
ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);
ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0);
clk : in std_logic;
clk90 : in std_logic;
dqs_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
dqs_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);
data_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
dqs_rst : in std_logic;
dqs_en : in std_logic;
wr_en : in std_logic;
wr_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);
wr_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);
mask_data_rise : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
mask_data_fall : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
rd_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);
rd_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);
dqs_delayed : out std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
ctrl_ddr_address : in std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : in std_logic;
ctrl_ddr_cas_l : in std_logic;
ctrl_ddr_we_l : in std_logic;
ctrl_ddr_cs_l : in std_logic;
ctrl_ddr_cke : in std_logic;
ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ddr_ras_l : out std_logic;
ddr_cas_l : out std_logic;
ddr_we_l : out std_logic;
ddr_cke : out std_logic;
ddr_cs_l : out std_logic
);
end component;
 
component MIG_user_interface_0
port(
clk : in std_logic;
clk90 : in std_logic;
reset : in std_logic;
ctrl_rden : in std_logic;
read_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);
read_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);
read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
comp_done : out std_logic;
read_data_valid : out std_logic;
af_empty : out std_logic;
af_almost_full : out std_logic;
app_af_addr : in std_logic_vector(35 downto 0);
app_af_wren : in std_logic;
ctrl_af_rden : in std_logic;
af_addr : out std_logic_vector(35 downto 0);
app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
app_wdf_wren : in std_logic;
ctrl_wdf_rden : in std_logic;
wdf_data : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
mask_data : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
wdf_almost_full : out std_logic
);
end component;
 
component MIG_ddr_controller_0
port(
clk_0 : in std_logic;
rst : in std_logic;
af_addr : in std_logic_vector(35 downto 0);
af_empty : in std_logic;
comp_done : in std_logic;
phy_dly_slct_done : in std_logic;
ctrl_dummyread_start : out std_logic;
ctrl_af_rden : out std_logic;
ctrl_wdf_rden : out std_logic;
ctrl_dqs_rst : out std_logic;
ctrl_dqs_en : out std_logic;
ctrl_wren : out std_logic;
ctrl_rden : out std_logic;
ctrl_ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
ctrl_ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
ctrl_ddr_ras_l : out std_logic;
ctrl_ddr_cas_l : out std_logic;
ctrl_ddr_we_l : out std_logic;
ctrl_ddr_cs_l : out std_logic;
ctrl_ddr_cke : out std_logic;
init_done : out std_logic;
dummy_write_pattern : out std_logic;
burst_length_div2 : out std_logic_vector(2 downto 0)
);
end component;
 
 
 
signal wr_df_data : std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
signal mask_df_data : std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
signal rd_data_rise : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal rd_data_fall : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal af_empty_w : std_logic;
signal dq_tap_sel_done : std_logic;
signal af_addr : std_logic_vector(35 downto 0);
signal ctrl_af_rden : std_logic;
signal ctrl_wr_df_rden : std_logic;
signal ctrl_dummy_rden : std_logic;
signal ctrl_dqs_enable : std_logic;
signal ctrl_dqs_reset : std_logic;
signal ctrl_wr_en : std_logic;
signal ctrl_rden : std_logic;
signal dqs_idelay_inc : std_logic_vector((READENABLE - 1) downto 0);
signal dqs_idelay_ce : std_logic_vector((READENABLE - 1) downto 0);
signal dqs_idelay_rst : std_logic_vector((READENABLE - 1) downto 0);
signal data_idelay_inc : std_logic_vector((READENABLE - 1) downto 0);
signal data_idelay_ce : std_logic_vector((READENABLE - 1) downto 0);
signal data_idelay_rst : std_logic_vector((READENABLE - 1) downto 0);
signal wr_en : std_logic;
signal dqs_rst : std_logic;
signal dqs_en : std_logic;
signal wr_data_rise : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal wr_data_fall : std_logic_vector((DATA_WIDTH - 1) downto 0);
signal dqs_delayed : std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
signal mask_data_fall : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
signal mask_data_rise : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
signal ctrl_ddr_address : std_logic_vector((ROW_ADDRESS - 1) downto 0);
signal ctrl_ddr_ba : std_logic_vector((BANK_ADDRESS - 1) downto 0);
signal ctrl_ddr_ras_l : std_logic;
signal ctrl_ddr_cas_l : std_logic;
signal ctrl_ddr_we_l : std_logic;
signal ctrl_ddr_cs_l : std_logic;
signal ctrl_ddr_cke : std_logic;
signal duMmy_write_pattern : std_logic;
signal comp_done : std_logic;
 
 
 
begin
 
clk_tb <= clk_0;
reset_tb <= sys_rst;
 
 
 
data_path_00 : MIG_data_path_0
port map (
clk => clk_0,
clk90 => clk_90,
reset0 => sys_rst,
reset90 => sys_rst90,
idelay_ctrl_rdy => idelay_ctrl_rdy,
dummy_write_pattern => dummy_write_pattern,
ctrl_dummyread_start => ctrl_dummy_rden,
wdf_data => wr_df_data,
mask_data => mask_df_data,
ctrl_wren => ctrl_wr_en,
ctrl_dqs_rst => ctrl_dqs_reset,
ctrl_dqs_en => ctrl_dqs_enable,
dqs_delayed => dqs_delayed,
data_idelay_inc => data_idelay_inc,
data_idelay_ce => data_idelay_ce,
data_idelay_rst => data_idelay_rst,
dqs_idelay_inc => dqs_idelay_inc,
dqs_idelay_ce => dqs_idelay_ce,
dqs_idelay_rst => dqs_idelay_rst,
sel_done => dq_tap_sel_done,
dqs_rst => dqs_rst,
dqs_en => dqs_en,
wr_en => wr_en,
wr_data_rise => wr_data_rise,
wr_data_fall => wr_data_fall,
mask_data_rise => mask_data_rise,
mask_data_fall => mask_data_fall
);
 
iobs_00 : MIG_iobs_0
port map (
ddr_ck => ddr_ck,
ddr_ck_n => ddr_ck_n,
clk => clk_0,
clk90 => clk_90,
dqs_idelay_inc => dqs_idelay_inc,
dqs_idelay_ce => dqs_idelay_ce,
dqs_idelay_rst => dqs_idelay_rst,
data_idelay_inc => data_idelay_inc,
data_idelay_ce => data_idelay_ce,
data_idelay_rst => data_idelay_rst,
dqs_rst => dqs_rst,
dqs_en => dqs_en,
wr_en => wr_en,
wr_data_rise => wr_data_rise,
wr_data_fall => wr_data_fall,
mask_data_rise => mask_data_rise,
mask_data_fall => mask_data_fall,
rd_data_rise => rd_data_rise,
rd_data_fall => rd_data_fall,
dqs_delayed => dqs_delayed,
ddr_dq => ddr_dq,
ddr_dqs => ddr_dqs,
ddr_dm => ddr_dm,
ctrl_ddr_address => ctrl_ddr_address,
ctrl_ddr_ba => ctrl_ddr_ba,
ctrl_ddr_ras_l => ctrl_ddr_ras_l,
ctrl_ddr_cas_l => ctrl_ddr_cas_l,
ctrl_ddr_we_l => ctrl_ddr_we_l,
ctrl_ddr_cs_l => ctrl_ddr_cs_l,
ctrl_ddr_cke => ctrl_ddr_cke,
ddr_address => ddr_a,
ddr_ba => ddr_ba,
ddr_ras_l => ddr_ras_n,
ddr_cas_l => ddr_cas_n,
ddr_we_l => ddr_we_n,
ddr_cke => ddr_cke,
ddr_cs_l => ddr_cs_n
);
 
user_interface_00 : MIG_user_interface_0
port map (
clk => clk_0,
clk90 => clk_90,
reset => sys_rst,
ctrl_rden => ctrl_rden,
read_data_rise => rd_data_rise,
read_data_fall => rd_data_fall,
read_data_fifo_out => read_data_fifo_out,
comp_done => comp_done,
read_data_valid => read_data_valid,
af_empty => af_empty_w,
af_almost_full => af_almost_full,
app_af_addr => app_af_addr,
app_af_wren => app_af_wren,
ctrl_af_rden => ctrl_af_rden,
af_addr => af_addr,
app_wdf_data => app_wdf_data,
app_mask_data => app_mask_data,
app_wdf_wren => app_wdf_wren,
ctrl_wdf_rden => ctrl_wr_df_rden,
wdf_data => wr_df_data,
mask_data => mask_df_data,
wdf_almost_full => wdf_almost_full
);
 
ddr_controller_00 : MIG_ddr_controller_0
port map (
clk_0 => clk_0,
rst => sys_rst,
af_addr => af_addr,
af_empty => af_empty_w,
phy_dly_slct_done => dq_tap_sel_done,
comp_done => comp_done,
ctrl_dummyread_start => ctrl_dummy_rden,
ctrl_af_rden => ctrl_af_rden,
ctrl_wdf_rden => ctrl_wr_df_rden,
ctrl_dqs_rst => ctrl_dqs_reset,
ctrl_dqs_en => ctrl_dqs_enable,
ctrl_wren => ctrl_wr_en,
ctrl_rden => ctrl_rden,
ctrl_ddr_address => ctrl_ddr_address,
ctrl_ddr_ba => ctrl_ddr_ba,
ctrl_ddr_ras_l => ctrl_ddr_ras_l,
ctrl_ddr_cas_l => ctrl_ddr_cas_l,
ctrl_ddr_we_l => ctrl_ddr_we_l,
ctrl_ddr_cs_l => ctrl_ddr_cs_l,
ctrl_ddr_cke => ctrl_ddr_cke,
init_done => init_done,
dummy_write_pattern => dummy_write_pattern,
burst_length_div2 => burst_length_div2
);
 
 
end arch;

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