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/trunk/rtl-model/rotate.v
0,0 → 1,140
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <zeus@opencores.org>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
 
`timescale 1ns/10ps
 
module rotate (
input [15:0] x,
input [15:0] y,
input [ 1:0] func, // 00: ror, 01: rol, 10: rcr, 11: rcl
input cfi,
input word_op,
output [15:0] out,
output cfo,
input ofi,
output ofo
);
 
// Net declarations
wire [4:0] ror16, rol16, rcr16, rcl16, rot16;
wire [3:0] ror8, rol8, rcr8, rcl8, rot8;
wire [7:0] out8;
wire [15:0] out16;
wire co8, co16;
wire unchanged;
 
// Module instantiation
rxr8 rxr8_0 (
.x (x[7:0]),
.ci (cfi),
.y (rot8),
.e (func[1]),
.w (out8),
.co (co8)
);
 
rxr16 rxr16_0 (
.x (x),
.ci (cfi),
.y (rot16),
.e (func[1]),
.w (out16),
.co (co16)
);
 
// Continuous assignments
assign unchanged = word_op ? (y[4:0]==5'b0) : (y[3:0]==4'b0);
assign ror16 = { 1'b0, y[3:0] };
assign rol16 = { 1'b0, -y[3:0] };
assign ror8 = { 1'b0, y[2:0] };
assign rol8 = { 1'b0, -y[2:0] };
 
assign rcr16 = y[4:0] <= 5'd16 ? y[4:0] : { 1'b0, y[3:0] - 4'b1 };
assign rcl16 = y[4:0] <= 5'd17 ? 5'd17 - y[4:0] : 6'd34 - y[4:0];
assign rcr8 = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
assign rcl8 = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 5'd18 - y[3:0];
 
assign rot8 = func[1] ? (func[0] ? rcl8 : rcr8 )
: (func[0] ? rol8 : ror8 );
assign rot16 = func[1] ? (func[0] ? rcl16 : rcr16 )
: (func[0] ? rol16 : ror16 );
 
assign out = word_op ? out16 : { x[15:8], out8 };
assign cfo = unchanged ? cfi : (func[1] ? (word_op ? co16 : co8)
: (func[0] ? out[0]
: (word_op ? out[15] : out[7])));
// Overflow
assign ofo = unchanged ? ofi : (func[0] ? // left
(word_op ? cfo^out[15] : cfo^out[7])
: // right
(word_op ? out[15]^out[14] : out[7]^out[6]));
endmodule
 
module rxr16 (
input [15:0] x,
input ci,
input [ 4:0] y,
input e,
output reg [15:0] w,
output reg co
);
 
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
5'd16: {co,w} <= {x,ci};
endcase
endmodule
 
module rxr8 (
input [7:0] x,
input ci,
input [3:0] y,
input e,
output reg [7:0] w,
output reg co
);
 
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[7:1]} : {ci, x[0], x[7:1]};
5'd02: {co,w} <= e ? {x[1:0], ci, x[7:2]} : {ci, x[1:0], x[7:2]};
5'd03: {co,w} <= e ? {x[2:0], ci, x[7:3]} : {ci, x[2:0], x[7:3]};
5'd04: {co,w} <= e ? {x[3:0], ci, x[7:4]} : {ci, x[3:0], x[7:4]};
5'd05: {co,w} <= e ? {x[4:0], ci, x[7:5]} : {ci, x[4:0], x[7:5]};
5'd06: {co,w} <= e ? {x[5:0], ci, x[7:6]} : {ci, x[5:0], x[7:6]};
5'd07: {co,w} <= e ? {x[6:0], ci, x[7]} : {ci, x[6:0], x[7]};
5'd08: {co,w} <= {x,ci};
endcase
endmodule
/trunk/rtl-model/alu.v
48,7 → 48,7
// muldiv mul0(x, y, mul, func[1:0], word_op, cf_mul, of_mul);
bitlog lo0(x[15:0], y, log, func, cf_log, of_log);
shifts sh0(x[15:0], y, shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
// rotat rot0(x[15:0], y, rot, func[1:0], word_op, cfi, cf_rot, of_rot);
rotate rot0(x[15:0], y, func[1:0], cfi, word_op, rot, cf_rot, ofi, of_rot);
othop oth0(x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
 
mux8_16 m0(t, /* adj */ {8'd0, y[7:0]}, add, cnv[15:0],
74,9 → 74,9
assign pfi = iflags[2];
assign cfi = iflags[0];
 
assign flags_unchanged = (t == 4'd6 || t == 4'd2
|| t == 4'd4 && func == 4'd2
|| t == 4'd5 && y[7:0] == 8'd0);
assign flags_unchanged = (t == 3'd6 || t == 3'd2
|| t == 3'd4 && func == 4'd2
|| t == 3'd5 && y[7:0] == 8'd0);
endmodule
 
module addsub(x, y, out, func, word_op, cfi, cfo, afo, ofo);
335,65 → 335,7
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
endmodule
/*
module rotat(x, y, out, func, word_op, cfi, cfo, ofo);
// IO ports
input [15:0] x, y;
input [1:0] func;
input cfi, word_op;
output [15:0] out;
output cfo;
output ofo;
 
// Net declarations
wire [15:0] rcl16, rcr16, rol16, ror16, rcl, rcr, rol, ror;
wire [7:0] yce16, ye16, yce8, ye8, rcl8, rcr8, rol8, ror8, yc16, yc8;
wire cfo_rcl, cfo_rcr, cfo_rol, cfo_ror;
 
// Module instantiations
mux4_16 m0(func, rcl, rcr, rol, ror, out);
mux4_1 m1(func, cfo_rcl, cfo_rcr, cfo_rol, cfo_ror, cfo);
 
// Assignments
assign yce16 = 8'd0; //y[7:0] % 8'd17;
assign ye16 = y[7:0] % 8'd16;
assign rcl16 = yce16 ? (x << yce16 | cfi << (yce16-8'd1) | x >> (8'd17-yce16)) : x;
assign rcr16 = yce16 ? (x >> yce16 | cfi << (8'd16-yce16) | x << (8'd17-yce16)) : x;
assign rol16 = (x << ye16 | x >> (8'd16-ye16));
assign ror16 = (x >> ye16 | x << (8'd16-ye16));
 
assign yce8 = 8'd0; //y[7:0] % 8'd9;
assign ye8 = y[7:0] % 8'd8;
assign rcl8 = yce8 ? (x[7:0] << yce8 | cfi << (yce8-8'd1) | x[7:0] >> (8'd9-yce8)) : x[7:0];
assign rcr8 = yce8 ? (x[7:0] >> yce8 | cfi << (8'd8-yce8) | x[7:0] << (9'd9-yce8)) : x[7:0];
assign rol8 = (x[7:0] << ye8 | x[7:0] >> (8'd8-ye8));
assign ror8 = (x[7:0] >> ye8 | x[7:0] << (8'd8-ye8));
 
assign rcl = word_op ? rcl16 : { 8'd0, rcl8 };
assign rcr = word_op ? rcr16 : { 8'd0, rcr8 };
assign rol = word_op ? rol16 : { 8'd0, rol8 };
assign ror = word_op ? ror16 : { 8'd0, ror8 };
 
// Carry
assign yc16 = (y[7:0]-8'd1)%8'd16;
assign yc8 = (y[7:0]-8'd1)%8'd8;
assign cfo_rcl = word_op ? (yce16==8'd0 ? cfi : x[16-yce16])
: (yce8==8'd0 ? cfi : x[8-yce8]);
assign cfo_rcr = word_op ? (yce16==8'd0 ? cfi : x[yce16-1])
: (yce8==8'd0 ? cfi : x[yce8-1]);
assign cfo_rol = word_op ? (y[7:0]==8'd0 ? cfi : x[15-yc16])
: (y[7:0]==8'd0 ? cfi : x[7-yc8]);
assign cfo_ror = word_op ? (y[7:0]==8'd0 ? cfi : x[yc16])
: (y[7:0]==8'd0 ? cfi : x[yc8]);
 
// Overflow
assign ofo = func[0] ? // right
(word_op ? out[15]^out[14] : out[7]^out[6])
: // left
(word_op ? cfo^out[15] : cfo^out[7]);
endmodule
*/
 
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
/trunk/rtl-model/fetch.v
964,7 → 964,27
 
8'b1101_00xx: // sal/shl
begin
seq_addr <= (regm==3'b100) ? ((mod==2'b11) ?
seq_addr <= (regm==3'b010) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `RCLCRW : `RCLCRB )
: (opcode[0] ? `RCL1RW : `RCL1RB ))
: (opcode[1] ? (opcode[0] ? `RCLCMW : `RCLCMB )
: (opcode[0] ? `RCL1MW : `RCL1MB )))
: ((regm==3'b011) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `RCRCRW : `RCRCRB )
: (opcode[0] ? `RCR1RW : `RCR1RB ))
: (opcode[1] ? (opcode[0] ? `RCRCMW : `RCRCMB )
: (opcode[0] ? `RCR1MW : `RCR1MB )))
: ((regm==3'b001) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `RORCRW : `RORCRB )
: (opcode[0] ? `ROR1RW : `ROR1RB ))
: (opcode[1] ? (opcode[0] ? `RORCMW : `RORCMB )
: (opcode[0] ? `ROR1MW : `ROR1MB )))
: ((regm==3'b000) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `ROLCRW : `ROLCRB )
: (opcode[0] ? `ROL1RW : `ROL1RB ))
: (opcode[1] ? (opcode[0] ? `ROLCMW : `ROLCMB )
: (opcode[0] ? `ROL1MW : `ROL1MB )))
: ( (regm==3'b100) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `SALCRW : `SALCRB )
: (opcode[0] ? `SAL1RW : `SAL1RB ))
: (opcode[1] ? (opcode[0] ? `SALCMW : `SALCMB )
978,7 → 998,7
(opcode[1] ? (opcode[0] ? `SHRCRW : `SHRCRB )
: (opcode[0] ? `SHR1RW : `SHR1RB ))
: (opcode[1] ? (opcode[0] ? `SHRCMW : `SHRCMB )
: (opcode[0] ? `SHR1MW : `SHR1MB ))));
: (opcode[0] ? `SHR1MW : `SHR1MB ))))))));
 
need_modrm <= 1'b1;
need_off <= need_off_mod;
/trunk/tests/i86/.bochsrc
1,4 → 1,4
romimage: file=12_rotate.out
romimage: file=rot.out
cpu: count=1, ips=10000000, reset_on_triple_fault=1
megs: 2
vgaromimage: file=$BXSHARE/VGABIOS-lgpl-latest
/trunk/tests/i86/12_rotate.s
32,10 → 32,10
# 0x20: 0x76bc 0xc8a7 0xd914 0xa7e4 0x7d7c 0x5941 0x0aeb 0x8307
# 0x30: 0x183e 0x7418 0x1d8d 0x7ea9 0x041a 0x8d5a 0x46ad 0xd5a8
# 0x40: 0x9348 0x9d84 0x792f 0x2eb5 0x5d6a 0x52eb 0xc5ab 0x4211
# 0x50: 0x1003 0x1002 0x1803 0x1003 0x1802 0x1802 0x1802 0x1803
# 0x60: 0x1803 0x1802 0x1002 0x1802 0x1002 0x1003 0x1803 0x1802
# 0x70: 0x1803 0x1002 0x1002 0x1002 0x1002 0x1802 0x1802 0x1002
# 0x80: 0x1002 0x0802 0x0002 0x0803 0x0803 0x0002 0x0002 0x0002
# 0x50: 0x0003 0x0002 0x0803 0x0003 0x0802 0x0802 0x0802 0x0803
# 0x60: 0x0803 0x0802 0x0002 0x0802 0x0002 0x0003 0x0803 0x0802
# 0x70: 0x0803 0x0002 0x0002 0x0002 0x0002 0x0802 0x0802 0x0002
# 0x80: 0x0002 0x0802 0x0002 0x0803 0x0803 0x0002 0x0002 0x0002
# 0x90: 0x0003 0x0803 0x0003 0x0802 0x0003 0x0002 0x0002 0x0002
 
.code16
/trunk/sim/modelsim/tb.do
1,6 → 1,6
vdel -all -lib work
vlib work
vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/rotate.v
vlog -work work +incdir+.. ../memory.v ../testbench.v
vsim -novopt -t ns work.testbench
add wave -label clk /testbench/clk
22,6 → 22,8
add wave -divider alu
add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
add wave -label addr -radix hexadecimal /testbench/addr
/trunk/sim/memory.v
24,5 → 24,5
if (we) if (byte_m) ram[addr] <= wr_data[7:0];
else { ram[addr1], ram[addr] } <= wr_data;
 
initial $readmemh("/home/zeus/zet/sim/11_shifts.rtlrom", ram, 20'hf0000);
initial $readmemh("/home/zeus/zet/sim/12_rotate.rtlrom", ram, 20'hf0000);
endmodule

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