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Rev 24 → Rev 25

/trunk/bench/verilog/can_testbench.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2003/01/31 01:13:31 mohor
// backup.
//
// Revision 1.16 2003/01/16 13:36:14 mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
214,8 → 217,8
begin
// Set Acceptance Code and Acceptance Mask registers
// write_register(8'd4, 8'ha6); // acceptance code
write_register(8'd4, 8'h08); // acceptance code
write_register(8'd5, 8'h00); // acceptance mask
write_register(8'd4, 8'he8); // acceptance code
write_register(8'd5, 8'h0f); // acceptance mask
end
#10;
249,7 → 252,6
end
 
 
 
$display("CAN Testbench finished !");
$stop;
end
279,8 → 281,8
end
else
begin
write_register(8'd10, 8'h12); // Writing ID[10:3] = 0x12
write_register(8'd11, 8'h04); // Writing ID[3:0] = 0x0, rtr = 0, length = 4
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
write_register(8'd11, 8'h18); // Writing ID[3:0] = 0x0, rtr = 1, length = 8
write_register(8'd12, 8'h56); // data byte 1
write_register(8'd13, 8'h78); // data byte 2
write_register(8'd14, 8'h9a); // data byte 3
291,6 → 293,47
write_register(8'd19, 8'hed); // data byte 8
end
 
fork
begin
$display("\n\nStart receiving data from CAN bus");
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
end
 
begin
tx_request;
end
 
begin
// Transmitting acknowledge
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
rx = 0;
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
rx = 1;
end
 
join
 
read_receive_buffer;
release_rx_buffer;
release_rx_buffer;
read_receive_buffer;
release_rx_buffer;
read_receive_buffer;
release_rx_buffer;
read_receive_buffer;
release_rx_buffer;
read_receive_buffer;
 
#200000;
 
read_receive_buffer;
 
end
endtask
 
667,6 → 710,15
endtask
 
 
task tx_request;
begin
write_register(8'd1, 8'h1);
$display("(%0t) Tx requested.", $time);
repeat (2) @ (posedge clk); // Time to decrement all the counters, etc.
end
endtask
 
 
task test_synchronization;
begin
// Hard synchronization
715,13 → 767,16
input [28:0] id;
input [3:0] length;
input [14:0] crc;
integer pointer;
integer cnt;
integer total_bits;
integer stuff_cnt;
 
reg [117:0] data;
reg previous_bit;
reg stuff;
reg stuff;
reg tmp;
reg arbitration_lost;
integer pointer;
integer cnt;
integer total_bits;
integer stuff_cnt;
 
begin
 
766,37 → 821,79
total_bits = pointer;
 
// Waiting until previous msg is finished before sending another one
wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter);
wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter & ~can_testbench.i_can_top.i_can_bsp.tx_state);
arbitration_lost = 0;
send_bit(0); // SOF
previous_bit = 0;
 
for (cnt=0; cnt<=total_bits; cnt=cnt+1)
begin
if (stuff_cnt == 5)
begin
stuff_cnt = 1;
total_bits = total_bits + 1;
stuff = 1;
send_bit(~data[pointer+1]);
previous_bit = ~data[pointer+1];
end
else
begin
if (data[pointer] == previous_bit)
stuff_cnt <= stuff_cnt + 1;
else
stuff_cnt <= 1;
stuff = 0;
send_bit(data[pointer]);
previous_bit = data[pointer];
pointer = pointer - 1;
end
end
fork
 
// Nothing send after the data (just recessive bit)
repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
begin
while (~arbitration_lost)
begin
for (cnt=0; cnt<=total_bits; cnt=cnt+1)
begin
if (stuff_cnt == 5)
begin
stuff_cnt = 1;
total_bits = total_bits + 1;
stuff = 1;
tmp = ~data[pointer+1];
send_bit(~data[pointer+1]);
previous_bit = ~data[pointer+1];
end
else
begin
if (data[pointer] == previous_bit)
stuff_cnt <= stuff_cnt + 1;
else
stuff_cnt <= 1;
stuff = 0;
tmp = data[pointer];
send_bit(data[pointer]);
previous_bit = data[pointer];
pointer = pointer - 1;
end
if (arbitration_lost)
cnt=total_bits+1; // Exit the for loop
end
arbitration_lost = 1; // At the end we exit the while loop
 
// Nothing send after the data (just recessive bit)
repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
end
end
 
begin
while (~arbitration_lost)
begin
#1 wait (can_testbench.i_can_top.sample_point);
// $display("(%0t)", $time);
if (mode)
begin
if (cnt<32 & tmp & (~rx_and_tx))
begin
arbitration_lost = 1;
rx = 1; // Only recessive is send from now on.
end
end
else
begin
if (cnt<12 & tmp & (~rx_and_tx))
begin
arbitration_lost = 1;
rx = 1; // Only recessive is send from now on.
end
end
end
end
 
join
 
// // Nothing send after the data (just recessive bit)
// repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
end
endtask
 
/trunk/rtl/verilog/can_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/01/31 01:13:38 mohor
// backup.
//
// Revision 1.9 2003/01/15 13:16:48 mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
102,7 → 105,7
input rx;
output tx;
 
reg data_out_fifo_selected;
reg data_out_fifo_selected;
 
wire [7:0] data_out_fifo;
wire [7:0] data_out_regs;
115,58 → 118,59
wire sleep_mode;
 
/* Command register */
wire release_buffer;
wire release_buffer;
wire tx_request;
 
/* Bus Timing 0 register */
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
 
/* Clock Divider register */
wire extended_mode;
wire rx_int_enable;
wire clock_off;
wire [2:0] cd;
wire extended_mode;
wire rx_int_enable;
wire clock_off;
wire [2:0] cd;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
wire [7:0] acceptance_code_0;
wire [7:0] acceptance_code_0;
 
/* Acceptance mask register */
wire [7:0] acceptance_mask_0;
wire [7:0] acceptance_mask_0;
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
/* Acceptance code register */
wire [7:0] acceptance_code_1;
wire [7:0] acceptance_code_2;
wire [7:0] acceptance_code_3;
wire [7:0] acceptance_code_1;
wire [7:0] acceptance_code_2;
wire [7:0] acceptance_code_3;
 
/* Acceptance mask register */
wire [7:0] acceptance_mask_1;
wire [7:0] acceptance_mask_2;
wire [7:0] acceptance_mask_3;
wire [7:0] acceptance_mask_1;
wire [7:0] acceptance_mask_2;
wire [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
 
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
/* End: Tx data registers */
 
 
191,7 → 195,7
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(),
.tx_request(),
.tx_request(tx_request),
.self_rx_request(),
 
/* Bus Timing 0 register */
329,6 → 333,7
/* Command register */
.release_buffer(release_buffer),
.tx_request(tx_request),
 
/* Clock Divider register */
.extended_mode(extended_mode),
/trunk/rtl/verilog/can_bsp.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2003/01/31 01:13:37 mohor
// backup.
//
// Revision 1.14 2003/01/16 13:36:19 mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
118,6 → 121,7
 
/* Command register */
release_buffer,
tx_request,
 
/* Clock Divider register */
extended_mode,
185,6 → 189,7
 
/* Command register */
input release_buffer;
input tx_request;
 
output rx_idle;
output transmitting;
236,9 → 241,12
reg [3:0] data_len;
reg [28:0] id;
reg [2:0] bit_stuff_cnt;
reg [2:0] bit_stuff_cnt_tx;
reg stuff_error;
reg tx_point_q;
 
wire bit_de_stuff;
wire bit_de_stuff_tx;
 
 
/* Rx state machine */
267,6 → 275,9
wire bit_de_stuff_set;
wire bit_de_stuff_reset;
 
wire go_early_tx;
wire go_tx;
 
reg rx_idle;
reg rx_id1;
reg rx_rtr1;
298,9 → 309,9
 
reg [2:0] eof_cnt;
wire [14:0] calculated_crc;
wire [15:0] r_calculated_crc;
wire remote_rq;
wire [3:0] limited_data_len;
//reg form_error;
wire form_error;
wire set_form_error;
reg transmitting;
312,14 → 323,37
reg tx;
reg crc_error;
 
reg priority_lost;
reg tx_q;
 
wire error_frame_ended;
wire bit_error = 0; // FIX ME !!!
wire acknowledge_error = 0; // FIX ME !!!
wire need_to_tx = 0; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
// of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!
wire acknowledge_error;
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
// of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
// be send in a row. Counter? FIX ME
 
wire id_ok; // If received ID matches ID set in registers
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
reg [2:0] header_cnt; // Counting header length
reg wr_fifo; // Write data and header to 64-byte fifo
reg [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
 
reg [5:0] tx_pointer;
reg tx_bit;
reg tx_state;
reg finish_msg;
 
wire [2:0] header_len;
wire storing_header;
wire [3:0] limited_data_len_minus1;
wire reset_wr_fifo;
wire no_error;
 
 
assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); // Look the following line for TX
//assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2) & need_to_tx);
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
347,7 → 381,8
sample_point & (~sampled_bit) & (error_cnt2 == 7)
;
 
assign go_crc_enable = hard_sync;
 
assign go_crc_enable = hard_sync | go_tx;
assign rst_crc_enable = go_rx_crc;
 
assign bit_de_stuff_set = go_rx_id1;
356,7 → 391,10
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
assign acknowledge_error = rx_ack & sample_point & sampled_bit & tx_state;
 
 
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
709,7 → 747,27
end
 
 
// bit_stuff_cnt_tx
always @ (posedge clk or posedge rst)
begin
if (rst)
bit_stuff_cnt_tx <= 1;
else if (bit_de_stuff_reset)
bit_stuff_cnt_tx <=#Tp 1;
else if (tx_point_q & bit_stuff_cnt_en)
begin
if (bit_stuff_cnt_tx == 5)
bit_stuff_cnt_tx <=#Tp 1;
else if (tx == tx_q)
bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
else
bit_stuff_cnt_tx <=#Tp 1;
end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
assign bit_de_stuff_tx = bit_stuff_cnt_tx == 5;
 
 
 
751,13 → 809,12
crc_error <= 0;
else if (go_rx_ack)
crc_error <=#Tp crc_in != calculated_crc;
else if (reset_mode | go_rx_idle | error_frame) // CRC error might reset itself
else if (reset_mode | go_rx_idle | error_frame)
crc_error <=#Tp 0;
end
 
 
// Conditions for form error
//assign set_form_error = sample_point & ( (~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) |
assign form_error = sample_point & ( (~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) |
rx_crc_lim & (~sampled_bit) |
rx_ack_lim & (~sampled_bit) |
764,25 → 821,12
rx_eof & (~sampled_bit)
);
 
/*
// Form error
always @ (posedge clk or posedge rst)
begin
if (rst)
form_error <= 1'b0;
else if (reset_mode | go_rx_idle | error_frame)
form_error <=#Tp 1'b0;
else if (set_form_error)
form_error <=#Tp 1'b1;
end
*/
 
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
.clk(clk),
// .data(sampled_bit & (~rx_crc)), // Zeros are shifted in for calculation when we are in crc stage
.data(sampled_bit ), // Zeros are shifted in for calculation when we are in crc stage
.data(sampled_bit),
.enable(crc_enable & sample_point & (~bit_de_stuff)),
.initialize(rx_eof),
.crc(calculated_crc)
790,9 → 834,6
 
 
 
wire id_ok; // If received ID matches ID set in registers
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
 
assign no_byte0 = rtr1 | (data_len<1);
assign no_byte1 = rtr1 | (data_len<2);
848,22 → 889,11
 
 
 
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
reg [2:0] header_cnt; // Counting header length
reg wr_fifo; // Write data and header to 64-byte fifo
reg [7:0] data_for_fifo; // Multiplexed data that is stored to 64-byte fifo
 
 
wire [2:0] header_len;
wire storing_header;
wire [3:0] limited_data_len_minus1;
wire reset_wr_fifo;
wire no_error;
 
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
assign storing_header = header_cnt < header_len;
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + header_len)) | reset_mode;
assign no_error = (~crc_error) & (~form_error) & (~stuff_error);
 
 
875,7 → 905,8
wr_fifo <= 1'b0;
else if (reset_wr_fifo)
wr_fifo <=#Tp 1'b0;
else if (go_rx_inter & id_ok & (~error_frame_ended))
else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
// else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) FIX ME !!! This line is the correct one. The above line is for easier debugging only.
wr_fifo <=#Tp 1'b1;
end
 
977,9 → 1008,9
begin
if (rst)
transmitting <= 1'b0;
else if (go_rx_idle | reset_mode)
else if (go_rx_idle | reset_mode | priority_lost)
transmitting <=#Tp 1'b0;
else if (~no_error)
else if (~no_error | go_tx)
transmitting <=#Tp 1'b1;
end
 
1031,34 → 1062,208
end
 
 
wire node_error_passive = 1;
wire node_error_passive = 1; // FIX ME
 
wire [18:0] basic_chain;
wire [63:0] basic_chain_data;
wire [18:0] extended_chain_std;
wire [38:0] extended_chain_ext;
wire [63:0] extended_chain_data;
 
wire rst_tx_pointer;
 
wire [7:0] r_tx_data_0;
wire [7:0] r_tx_data_1;
wire [7:0] r_tx_data_2;
wire [7:0] r_tx_data_3;
wire [7:0] r_tx_data_4;
wire [7:0] r_tx_data_5;
wire [7:0] r_tx_data_6;
wire [7:0] r_tx_data_7;
wire [7:0] r_tx_data_8;
wire [7:0] r_tx_data_9;
wire [7:0] r_tx_data_10;
wire [7:0] r_tx_data_11;
wire [7:0] r_tx_data_12;
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
tx <= 1'b1;
else if (reset_mode | error_frame_ended)
else if (reset_mode | error_frame_ended) // Reset
tx <=#Tp 1'b1;
else if (tx_point & error_frame)
else if (tx_point)
begin
if (error_cnt1 < 6)
if (tx_state) // Transmitting message
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
else if ((~tx_state) & rx_ack & no_error) // Acknowledge
tx <=#Tp 1'b0;
else if (error_frame) // Transmitting error frame
begin
if (node_error_passive)
if (error_cnt1 < 6)
begin
if (node_error_passive)
tx <=#Tp 1'b1;
else
tx <=#Tp 1'b0;
end
else if (error_cnt2 < 7)
tx <=#Tp 1'b1;
else
tx <=#Tp 1'b0;
end
else if (error_cnt2 < 7)
else
tx <=#Tp 1'b1;
end
end
 
 
always @ (posedge clk)
begin
if (tx_point)
tx_q <=#Tp tx;
end
 
 
/* Delayed tx point */
always @ (posedge clk)
begin
tx_point_q <=#Tp tx_point;
end
 
 
/* Changing bit order from [7:0] to [0:7] */
can_ibo i_ibo_tx_data_0 (.di(tx_data_0), .do(r_tx_data_0));
can_ibo i_ibo_tx_data_1 (.di(tx_data_1), .do(r_tx_data_1));
can_ibo i_ibo_tx_data_2 (.di(tx_data_2), .do(r_tx_data_2));
can_ibo i_ibo_tx_data_3 (.di(tx_data_3), .do(r_tx_data_3));
can_ibo i_ibo_tx_data_4 (.di(tx_data_4), .do(r_tx_data_4));
can_ibo i_ibo_tx_data_5 (.di(tx_data_5), .do(r_tx_data_5));
can_ibo i_ibo_tx_data_6 (.di(tx_data_6), .do(r_tx_data_6));
can_ibo i_ibo_tx_data_7 (.di(tx_data_7), .do(r_tx_data_7));
can_ibo i_ibo_tx_data_8 (.di(tx_data_8), .do(r_tx_data_8));
can_ibo i_ibo_tx_data_9 (.di(tx_data_9), .do(r_tx_data_9));
can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
 
/* Changing bit order from [14:0] to [0:14] */
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
 
 
assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
assign extended_chain_data = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
 
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data or rx_crc or r_calculated_crc or
r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
finish_msg)
begin
if (extended_mode)
begin
if (rx_data) // data stage
tx_bit = extended_chain_data[tx_pointer];
else if (rx_crc)
tx_bit = r_calculated_crc[tx_pointer];
else if (finish_msg)
tx_bit = 1'b1;
else
begin
if (r_tx_data_0[0]) // Extended frame
tx_bit = extended_chain_ext[tx_pointer];
else
tx_bit = extended_chain_std[tx_pointer];
end
end
else // Basic mode
begin
if (rx_data) // data stage
tx_bit = basic_chain_data[tx_pointer];
else if (rx_crc)
tx_bit = r_calculated_crc[tx_pointer];
else if (finish_msg)
tx_bit = 1'b1;
else
tx_bit = basic_chain[tx_pointer];
end
end
 
 
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & tx_pointer == 38 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
( tx_point & rx_crc_lim ) | // crc
(go_rx_idle ) | // at the end
(reset_mode ) |
(error_frame ) ; // FIX ME (not sure this is ok)
 
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_pointer <= 'h0;
else if (rst_tx_pointer)
tx_pointer <=#Tp 'h0;
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
tx_pointer <=#Tp tx_pointer + 1'b1;
end
 
 
wire rst_need_to_tx = go_rx_inter & (~error_frame & (~priority_lost)); // FIX ME !!! When there is no error until the end-of-frame, tx is ok (finished).
always @ (posedge clk or posedge rst)
begin
if (rst)
need_to_tx <= 1'b0;
else if (rst_need_to_tx)
need_to_tx <=#Tp 'h0;
else if (tx_request)
need_to_tx <=#Tp 1'b1;
end
 
 
 
assign go_early_tx = need_to_tx & (~tx_state) & sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
assign go_tx = need_to_tx & (~tx_state) & sample_point & (go_early_tx | sampled_bit & rx_idle);
 
 
// Tx state
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_state <= 1'b0;
else if (go_rx_inter | error_frame | priority_lost)
tx_state <=#Tp 1'b0;
else if (go_tx)
tx_state <=#Tp 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
finish_msg <= 1'b0;
else if (go_rx_idle | error_frame | reset_mode)
finish_msg <=#Tp 1'b0;
else if (go_rx_crc_lim)
finish_msg <=#Tp 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
priority_lost <= 1'b0;
else if (go_rx_idle | error_frame | reset_mode)
priority_lost <=#Tp 1'b0;
else if (tx_state & sample_point & tx & (rx_id1 | rx_rtr1 | rx_id2 | rx_ide | rx_id2 | rx_rtr2))
priority_lost <=#Tp (~sampled_bit);
end
 
 
 
endmodule
/trunk/rtl/verilog/can_ibo.v
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// can_ibo.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
 
 
// This module only inverts bit order
module can_ibo
(
di,
do
);
 
input [7:0] di;
output [7:0] do;
 
assign do[0] = di[7];
assign do[1] = di[6];
assign do[2] = di[5];
assign do[3] = di[4];
assign do[4] = di[3];
assign do[5] = di[2];
assign do[6] = di[1];
assign do[7] = di[0];
 
endmodule
/trunk/sim/rtl_sim/run/wave.do
116,8 → 116,8
define variable nofullpathfilenames
include bookmark with filenames
include scope history without filenames
define waveform window listpane 8
define waveform window namepane 12
define waveform window listpane 6.99
define waveform window namepane 12.96
define multivalueindication
define pattern curpos dot
define pattern cursor1 dot
217,9 → 217,16
 
add group \
testbench \
can_testbench.receive_frame.arbitration_lost \
can_testbench.receive_frame.tmp \
can_testbench.receive_frame.cnt's \
can_testbench.receive_frame.mode \
can_testbench.receive_frame.pointer's \
can_testbench.receive_frame.total_bits's \
 
add group \
can_bsp \
can_testbench.receive_frame.arbitration_lost \
can_testbench.i_can_top.i_can_bsp.acknowledge_error \
can_testbench.i_can_top.i_can_bsp.bit_error \
can_testbench.i_can_top.i_can_bsp.crc_error \
229,10 → 236,19
can_testbench.i_can_top.i_can_bsp.stuff_error \
can_testbench.i_can_top.i_can_btl.hard_sync \
can_testbench.i_can_top.i_can_btl.resync \
can_testbench.rx \
can_testbench.i_can_top.rx \
can_testbench.i_can_top.tx \
can_testbench.i_can_top.i_can_bsp.sample_point \
can_testbench.i_can_top.i_can_bsp.tx_point \
can_testbench.i_can_top.i_can_bsp.basic_chain[18:0]'h \
can_testbench.i_can_top.i_can_bsp.basic_chain_data[63:0]'h \
can_testbench.i_can_top.i_can_bsp.extended_chain_std[18:0]'h \
can_testbench.i_can_top.i_can_bsp.extended_chain_ext[38:0]'h \
can_testbench.i_can_top.i_can_bsp.extended_chain_data[63:0]'h \
can_testbench.i_can_top.i_can_bsp.extended_mode \
can_testbench.i_can_top.i_can_bsp.tx_pointer[5:0]'h \
can_testbench.i_can_top.i_can_bsp.rst_tx_pointer \
can_testbench.i_can_top.i_can_bsp.acknowledge_error \
can_testbench.i_can_top.i_can_bsp.addr[7:0]'h \
can_testbench.i_can_top.i_can_bsp.bit_cnt[5:0]'h \
244,6 → 260,7
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_en \
can_testbench.i_can_top.i_can_bsp.byte_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.calculated_crc[14:0]'h \
can_testbench.i_can_top.i_can_bsp.r_calculated_crc[15:0]'h \
can_testbench.i_can_top.i_can_bsp.crc_in[14:0]'h \
can_testbench.i_can_top.i_can_bsp.clk \
can_testbench.i_can_top.i_can_bsp.crc_enable \
260,6 → 277,21
can_testbench.i_can_top.i_can_bsp.error_frame_ended \
can_testbench.i_can_top.i_can_bsp.rtr1 \
can_testbench.i_can_top.i_can_bsp.rtr2 \
can_testbench.i_can_top.i_can_bsp.priority_lost \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_tx \
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_tx[2:0]'h \
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_en \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_set \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_reset \
can_testbench.i_can_top.i_can_btl.hard_sync \
can_testbench.i_can_top.i_can_btl.resync \
can_testbench.i_can_top.rx \
can_testbench.i_can_top.i_can_bsp.tx_pointer[5:0]'h \
can_testbench.i_can_top.tx \
can_testbench.i_can_top.i_can_bsp.tx_q \
can_testbench.i_can_top.i_can_bsp.tx_bit \
can_testbench.i_can_top.i_can_bsp.sample_point \
can_testbench.i_can_top.i_can_bsp.tx_point \
can_testbench.i_can_top.i_can_bsp.rx_ack \
can_testbench.i_can_top.i_can_bsp.rx_ack_lim \
can_testbench.i_can_top.i_can_bsp.rx_crc \
266,6 → 298,8
can_testbench.i_can_top.i_can_bsp.rx_crc_lim \
can_testbench.i_can_top.i_can_bsp.rx_data \
can_testbench.i_can_top.i_can_bsp.rx_dlc \
can_testbench.i_can_top.i_can_bsp.finish_msg \
can_testbench.i_can_top.i_can_bsp.tx_state \
can_testbench.i_can_top.i_can_bsp.rx_eof \
can_testbench.i_can_top.i_can_bsp.rx_id1 \
can_testbench.i_can_top.i_can_bsp.rx_id2 \
278,6 → 312,11
can_testbench.i_can_top.i_can_bsp.rx_rtr2 \
can_testbench.i_can_top.i_can_bsp.extended_mode \
can_testbench.i_can_top.i_can_bsp.form_error \
can_testbench.i_can_top.i_can_bsp.go_early_tx \
can_testbench.i_can_top.i_can_bsp.go_tx \
can_testbench.i_can_top.i_can_bsp.need_to_tx \
can_testbench.i_can_top.i_can_bsp.tx_request \
can_testbench.i_can_top.i_can_bsp.tx_state \
can_testbench.i_can_top.i_can_bsp.go_crc_enable \
can_testbench.i_can_top.i_can_bsp.go_error_frame \
can_testbench.i_can_top.i_can_bsp.go_rx_ack \
456,4 → 495,5
fontsize 12 \
 
 
open window designbrowser 1 geometry 370 210 855 550
open window waveform 1 geometry 10 59 1592 1140
zoom at 0(0)ns 0.00001477 0.00000000
/trunk/sim/rtl_sim/bin/rtl_file_list
8,4 → 8,5
can_bsp.v
can_crc.v
can_acf.v
can_fifo.v
can_fifo.v
can_ibo.v

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