URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
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- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/trunk/rtl/verilog/dbg_top.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2001/11/28 09:36:15 mohor |
// Register length fixed. |
// |
// Revision 1.13 2001/11/27 13:37:43 mohor |
// CRC is returned when chain selection data is transmitted. |
// |
230,11 → 233,11
reg wb_AccessTck; // Indicates access to the WISHBONE |
reg [31:0] WBReadLatch; // Data latched during WISHBONE read |
reg WBErrorLatch; // Error latched during WISHBONE read |
reg trst; // trst is active high while trst_pad_i is active low |
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wire TCK = tck_pad_i; |
wire TMS = tms_pad_i; |
wire TDI = tdi_pad_i; |
wire trst = ~trst_pad_i; // trst_pad_i is active low |
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wire [31:0] RegDataIn; // Data from registers (read data) |
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO. |
327,6 → 330,17
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/********************************************************************************** |
* * |
* Synchronizing TRST to clock signal * |
* * |
**********************************************************************************/ |
always @ (posedge wb_clk_i) |
begin |
trst <=#Tp ~trst_pad_i; // trst_pad_i is active low |
end |
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/********************************************************************************** |
* * |
* TAP State Machine: Fully JTAG compliant * |
* * |
**********************************************************************************/ |