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URL https://opencores.org/ocsvn/gpio/gpio/trunk

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Rev 24 → Rev 25

/trunk/rtl/verilog/gpio_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/03/09 03:43:27 lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
// Revision 1.8 2002/01/14 19:06:28 lampret
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
//
94,7 → 97,7
aux_i,
 
// External GPIO Interface
in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
);
 
parameter dw = 32;
123,10 → 126,10
//
// External GPIO Interface
//
input [gw-1:0] in_pad_i; // GPIO Inputs
input ext_clk_pad_i; // GPIO Eclk
output [gw-1:0] out_pad_o; // GPIO Outputs
output [gw-1:0] oen_padoen_o; // GPIO output drivers enables
input [gw-1:0] ext_pad_i; // GPIO Inputs
input clk_pad_i; // GPIO Eclk
output [gw-1:0] ext_pad_o; // GPIO Outputs
output [gw-1:0] ext_padoen_o; // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
227,7 → 230,7
`endif
wire [gw-1:0] out_pad; // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg [gw-1:0] out_pad_o; // GPIO Outputs
reg [gw-1:0] ext_pad_o; // GPIO Outputs
`endif
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
wire pext_clk; // External clock for posedge flops
409,7 → 412,7
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
416,9 → 419,9
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
`else
assign pext_clk = ext_clk_pad_i;
assign pext_clk = clk_pad_i;
`endif
 
//
437,7 → 440,7
if (wb_rst_i)
pextc_sampled <= #1 {gw{1'b0}};
else
pextc_sampled <= #1 in_pad_i;
pextc_sampled <= #1 ext_pad_i;
 
//
// Latch using negedge external clock
444,11 → 447,11
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
always @(negedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i)
nextc_sampled <= #1 {gw{1'b0}};
else
nextc_sampled <= #1 in_pad_i;
nextc_sampled <= #1 ext_pad_i;
`endif
 
//
508,10 → 511,10
rgpio_ints <= #1 {gw{1'b0}};
else if (rgpio_ints_sel && wb_we_i)
rgpio_ints <= #1 wb_dat_i[gw-1:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != in_pad_i)
rgpio_ints <= #1 (rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != ext_pad_i)
rgpio_ints <= #1 (rgpio_ints | (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
`else
assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
assign rgpio_ints = (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
535,7 → 538,7
//
// Output enables are RGPIO_OE bits
//
assign oen_padoen_o = rgpio_oe;
assign ext_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
548,11 → 551,11
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
out_pad_o <= #1 {gw{1'b0}};
ext_pad_o <= #1 {gw{1'b0}};
else
out_pad_o <= #1 out_pad;
ext_pad_o <= #1 out_pad;
`else
assign out_pad_o = out_pad;
assign ext_pad_o = out_pad;
`endif
 
`else
564,8 → 567,8
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign oen_padoen_o = {gw{1'b1}};
assign out_pad_o = {gw{1'b0}};
assign ext_padoen_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers

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