OpenCores

memory_cores/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: memory_cores/web_uploads =================================================================== --- memory_cores/web_uploads (nonexistent) +++ memory_cores/web_uploads (revision 25)

memory_cores/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: memory_cores/branches =================================================================== --- memory_cores/branches (nonexistent) +++ memory_cores/branches (revision 25)

memory_cores/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: memory_cores/tags/Beta/dpmem/dpmem.vhd =================================================================== --- memory_cores/tags/Beta/dpmem/dpmem.vhd (nonexistent) +++ memory_cores/tags/Beta/dpmem/dpmem.vhd (revision 25) @@ -0,0 +1,231 @@ +------------------------------------------------------------------------------- +-- +-- Copyright Jamil Khatib 1999 +-- +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it under the terms of the Openip General Public +-- License as it is going to be published by the OpenIP Organization and any +-- coming versions of this license. +-- You can check the draft license at +-- http://www.openip.org/oc/license.html +-- +-- +-- Creator : Jamil Khatib +-- Date 14/5/99 +-- +-- version 0.19990710 +-- +-- This file was tested on the ModelSim 5.2EE +-- The test vecors for model sim is included in vectors.do file +-- This VHDL design file is proved through simulation but not verified on Silicon +-- +-- +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +USE ieee.std_logic_signed.ALL; + + + +-- Dual port Memory core + + + +ENTITY dpmem IS +generic ( ADD_WIDTH: integer := 8 ; + WIDTH : integer := 8); + PORT ( + clk : IN std_logic; -- write clock + reset : IN std_logic; -- System Reset + W_add : IN std_logic_vector(add_width -1 downto 0); -- Write Address + R_add : IN std_logic_vector(add_width -1 downto 0); -- Read Address + Data_In : IN std_logic_vector(WIDTH - 1 DOWNTO 0); -- input data + Data_Out : OUT std_logic_vector(WIDTH -1 DOWNTO 0); -- output Data + WR : IN std_logic; -- Write Enable + RE : IN std_logic); -- Read Enable +END dpmem; + + +------------------------------------------------------------------------------- + +ARCHITECTURE dpmem_v1 OF dpmem IS + + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + + + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + + +BEGIN -- dpmem_v1 + + PROCESS (clk, reset) + + BEGIN -- PROCESS + + + -- activities triggered by asynchronous reset (active low) + IF reset = '0' THEN + data_out <= (OTHERS => 'Z'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF RE = '1' THEN + data_out <= data(conv_integer(R_add)); + else + data_out <= (OTHERS => 'Z'); -- Defualt value + END IF; + + IF WR = '1' THEN + data(conv_integeR(W_add)) <= Data_In; + END IF; + END IF; + + + + END PROCESS; + + +END dpmem_v1; + + + +------------------------------------------------------------------------------- + +-- +-- The variable result_data is used as an intermediate variable in the process +-- + +ARCHITECTURE dpmem_v2 OF dpmem IS + + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + +-- Initialize the memory to zeros + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + + +BEGIN -- dpmem_v2 + + PROCESS (clk, reset) + + variable result_data : std_logic_vector(WIDTH -1 downto 0); + + BEGIN -- PROCESS + +-- init data_out + + + -- activities triggered by asynchronous reset (active low) + IF reset = '0' THEN + result_data := (OTHERS => 'Z'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF RE = '1' THEN + result_data := data(conv_integer(R_add)); + else + result_data := (OTHERS => 'Z'); -- Defualt value + END IF; + + IF WR = '1' THEN + data(conv_integeR(W_add)) <= Data_In; + END IF; + END IF; + +data_out <= result_data; + + +END PROCESS; + + +END dpmem_v2; + + + +------------------------------------------------------------------------------- +-- This is the same as dpmem_v1 but without the Z state +-- instead the output goes to all 1's during reset and +-- when RE = 0 + +ARCHITECTURE dpmem_v3 OF dpmem IS + + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + + + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + + +BEGIN -- dpmem_v3 + + PROCESS (clk, reset) + + BEGIN -- PROCESS + + + -- activities triggered by asynchronous reset (active low) + IF reset = '0' THEN + data_out <= (OTHERS => '1'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF RE = '1' THEN + data_out <= data(conv_integer(R_add)); + else + data_out <= (OTHERS => '1'); -- Defualt value + END IF; + + IF WR = '1' THEN + data(conv_integeR(W_add)) <= Data_In; + END IF; + END IF; + + + + END PROCESS; + + +END dpmem_v3; + + + +------------------------------------------------------------------------------- Index: memory_cores/tags/Beta/spmem/spmem.vhd =================================================================== --- memory_cores/tags/Beta/spmem/spmem.vhd (nonexistent) +++ memory_cores/tags/Beta/spmem/spmem.vhd (revision 25) @@ -0,0 +1,169 @@ +------------------------------------------------------------------------------- +-- +-- Copyright Jamil Khatib 1999 +-- +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it under the terms of the Openip Hardware +-- General Public License as publilshed by the OpenIP organization and any +-- coming versions of this license. +-- You can check the current license at +-- http://www.openip.org/oc/license.html +-- +-- +-- Creator : Jamil Khatib +-- Date 14/5/99 +-- +-- Conntact me at khatib@ieee.org +-- +-- version 1.01-19991218 +-- +-- +-- This VHDL design file is proved through simulation and synthesis but not +-- verified on Silicon +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_signed.All; +------------------------------------------------------------------------------- +-- Single port Memory core + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + + +ENTITY Spmem IS +generic ( add_width : integer := 3 ; + WIDTH : integer := 8); + + PORT ( + clk : IN std_logic; -- write clock + reset : IN std_logic; -- System Reset + add : IN std_logic_vector(add_width -1 downto 0); -- Address + Data_In : IN std_logic_vector(WIDTH -1 DOWNTO 0); -- input data + Data_Out : OUT std_logic_vector(WIDTH -1 DOWNTO 0); -- Output Data + WR : IN std_logic); -- Read Write Enable +END Spmem; + + + +------------------------------------------------------------------------------- +-- This Architecture was tested on the ModelSim 5.2EE +-- The test vectors for model sim is included in vectors.do file + + +ARCHITECTURE spmem_v1 OF Spmem IS + + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(7 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + + + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + +BEGIN -- spmem_v1 + + +PROCESS (clk, reset) +-- VARIABLE result_data : std_logic_vector(WIDTH -1 DOWNTO 0); + + +BEGIN -- PROCESS + -- activities triggered by asynchronous reset (active low) +-- Data_Out <= (OTHERS => 'Z'); + + IF reset = '0' THEN + data_out <= (OTHERS => 'Z'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF WR = '0' THEN + + data(conv_integer(add)) <= data_in; + -- ELSE + -- data_out <= data(conv_integer(add)); + END IF; +data_out <= data(conv_integer(add)); + END IF; + +END PROCESS; + + +END spmem_v1; + + + + +------------------------------------------------------------------------------- +-- This Architecture was tested on the ModelSim 5.2EE +-- The test vectors for model sim is included in vectors.do file +-- It is Synthesized using Xilinx Webpack +-- +-- This is the same as spmem_v1 but without the Z state +-- instead the output goes to all 1's during reset + + + + +ARCHITECTURE spmem_v2 OF Spmem IS + + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + +BEGIN -- spmem_v2 + + +PROCESS (clk, reset) +-- VARIABLE result_data : std_logic_vector(WIDTH -1 DOWNTO 0); + + +BEGIN -- PROCESS + -- activities triggered by asynchronous reset (active low) + + IF reset = '0' THEN + data_out <= (OTHERS => '1'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF WR = '0' THEN + + data(conv_integer(add)) <= data_in; + -- ELSE + -- data_out <= data(conv_integer(add)); + END IF; +data_out <= data(conv_integer(add)); + END IF; + +END PROCESS; + + +END spmem_v2; Index: memory_cores/tags/first/FIFO2/FIFO.VHD =================================================================== --- memory_cores/tags/first/FIFO2/FIFO.VHD (nonexistent) +++ memory_cores/tags/first/FIFO2/FIFO.VHD (revision 25) @@ -0,0 +1,158 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E FIFO controller C O R E +-- +-- www.OpenCores.Org - May 2000 +-- This core adheres to the GNU public license +-- +-- Design units : FIFO Memory Controller Unit +-- +-- File name : Fifo.vhd +-- +-- Purpose : Implements the memory controller device. +-- +-- Library : FIFO_Lib +-- +-- Dependencies : IEEE.Std_Logic_1164 +-- +-- Author : Ovidiu Lupas +-- http://www.opencores.org/people/olupas +-- olupas@opencores.org +-- +-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Revision list +-- Version Author Date Changes +-- +-- 0.1 Ovidiu Lupas 20 April 1999 New model +-- olupas@opencores.org +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Entity for FIFO Unit - 16 bit Data Bus width -- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +library work; +use work.FIFO_Def.all; +------------------------------------------------------------------------------- +entity FIFO is + port ( + DataIn : in Std_Logic_Vector(15 downto 0); + DataOut : out Std_Logic_Vector(15 downto 0); + WrClk : in Std_Logic; -- Clock signal + Push_N : in Std_Logic; -- Write to FIFO signal + RdClk : in Std_Logic; -- Clock signal + Pop_N : in Std_Logic; -- Read from FIFO signal + AlmFull : out Std_Logic; -- Status signal + AlmEmpty : out Std_Logic; -- Status signal + Full : out Std_Logic; -- Status signal + Empty : out Std_Logic; -- Status signal + Reset : in Std_Logic); -- Reset input +end entity; --================== End of entity ==============================-- +------------------------------------------------------------------------------- +-- Architecture for Sensor Control Unit +------------------------------------------------------------------------------- +architecture Structural of FIFO is + ------------------------------------------------------------------- + -- Global declarations + ------------------------------------------------------------------- + type MEMORY is array(0 to 15) of Std_Logic_Vector(15 downto 0); + signal MEM : Memory; + ------------------------------------------------------------------- + -- Signals + ------------------------------------------------------------------- + signal Rst : Std_Logic; -- Reset signal + signal RdEn : Std_Logic; -- Read Enable + signal WrEn : Std_Logic; -- Write Enable + signal Clk : Std_Logic; -- + signal UpDn : Std_Logic; -- + signal En : Std_Logic; -- + signal WrAddr : Std_Logic_Vector(3 downto 0); -- Write address + signal RdAddr : Std_Logic_Vector(3 downto 0); -- Read address + ------------------------------------------------------------------- + -- Address counter for read and write operations + ------------------------------------------------------------------- + component FIFOcnt is + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Enable : in Std_Logic; + CntOut : out Std_Logic_Vector(3 downto 0)); + end component; + ------------------------------------------------------------------- + -- Status counter + ------------------------------------------------------------------- + component StatCnt is + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Enable : in Std_Logic; + UpDown : in Std_Logic; + Full : out Std_Logic; + Empty : out Std_Logic; + AlmFull : out Std_Logic; + AlmEmpty : out Std_Logic); + end component; +begin + --------------------------------------------------------------------- + -- Instantiation of internal components + --------------------------------------------------------------------- + WrCnt : FIFOCnt port map (WrClk,Rst,WrEn,WrAddr); + RdCnt : FIFOCnt port map (RdClk,Rst,RdEn,RdAddr); + Status : StatCnt port map (Clk,Rst,En,UpDn,Full,Empty,AlmFull,AlmEmpty); + --------------------------------------------------------------------- + -- Latching the Reset command + --------------------------------------------------------------------- + RstEn : process(Reset) + begin + Rst <= not Reset; + end process; + --------------------------------------------------------------------- + -- Latching the Push command + --------------------------------------------------------------------- + PushEn : process(Push_N) + begin + WrEn <= not Push_N; + end process; + --------------------------------------------------------------------- + -- Latching the Pop command + --------------------------------------------------------------------- + PopEn : process(Pop_N) + begin + RdEn <= not Pop_N; + end process; + --------------------------------------------------------------------- + -- write to memory process + --------------------------------------------------------------------- + WrCycle : process(WrClk,WrEn) + begin + if (Rising_Edge(WrClk) and WrEn = '1') then + MEM(BV2Integer(WrAddr)) <= DataIn; + end if; + end process; + --------------------------------------------------------------------- + -- read from memory process + --------------------------------------------------------------------- + RdCycle : process(Reset,RdClk,RdEn) + begin + if Reset = '1' then + DataOut <= "ZZZZZZZZZZZZZZZZ"; + elsif (Rising_Edge(RdClk) and RdEn = '1') then + DataOut <= MEM(BV2Integer(RdAddr)); + end if; + end process; + --------------------------------------------------------------------- + -- generating the signals for status counter + --------------------------------------------------------------------- + StatCycle : process(WrClk,RdClk,RdEn,WrEn) + variable RdC : Std_Logic; -- + variable WrC : Std_Logic; -- + begin + RdC := RdClk and RdEn; + WrC := WrClk and WrEn; + En <= RdEn xor WrEn; + UpDn <= WrEn; + Clk <= WrC xor RdC; + end process; +end Structural; --==================== End of architecture ====================-- \ No newline at end of file Index: memory_cores/tags/first/FIFO2/FIFOTEST.VHD =================================================================== --- memory_cores/tags/first/FIFO2/FIFOTEST.VHD (nonexistent) +++ memory_cores/tags/first/FIFO2/FIFOTEST.VHD (revision 25) @@ -0,0 +1,196 @@ +--============================================================================-- +-- Design units : TestBench for FIFO memory device. +-- +-- File name : FIFOTest.vhd +-- +-- Purpose : Implements the test bench for FIFO memory device. +-- +-- Library : ECO_Lib.vhd +-- +-- Dependencies : None +-- +-- Author : Ovidiu Lupas +-- http://www.opencores.org/people/olupas +-- olupas@opencores.org +-- +-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- Revision list +-- Version Author Date Changes +-- +-- 0.1 Ovidiu Lupas 18 April 99 New model +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Clock generator +------------------------------------------------------------------------------- +library IEEE,work; +use IEEE.Std_Logic_1164.all; +-- +entity ClkGen is + port ( + WrClk : out Std_Logic; + RdClk : out Std_Logic); -- Oscillator clock +end ClkGen;--==================== End of entity ==============================-- +-------------------------------------------------------------------------------- +-- Architecture for clock and reset signals generator +-------------------------------------------------------------------------------- +architecture Behaviour of ClkGen is +begin --========================== Architecture ==============================-- + ------------------------------------------------------------------------------ + -- Provide the external clock signal + ------------------------------------------------------------------------------ + WrClkDriver : process + variable clktmp : Std_Logic := '1'; + variable tpw_CI_posedge : Time := 31 ns; -- 16 MHz + begin + WrClk <= clktmp; + clktmp := not clktmp; + wait for tpw_CI_posedge; + end process; + ------------------------------------------------------------------------------ + -- Provide the external clock signal + ------------------------------------------------------------------------------ + RdClkDriver : process + variable clktmp : Std_Logic := '1'; + variable tpw_CI_posedge : Time := 51 ns; -- 16 MHz + begin + RdClk <= clktmp; + clktmp := not clktmp; + wait for tpw_CI_posedge; + end process; +end Behaviour; --=================== End of architecure =====================-- +-------------------------------------------------------------------------------- +-- Testbench for FIFO memory +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; +use work.ECO_Def.all; + +entity FIFOTEST is +end FIFOTEST; + +architecture stimulus of FIFOTEST is + ------------------------------------------------------------------- + -- Global declarations + ------------------------------------------------------------------- + type MEMORY is array(0 to 15) of Std_Logic_Vector(15 downto 0); + constant Data : MEMORY := ("0101010101010101", "1010101010101010", + "1111101010100000", "1111010101010000", + "1111101010100000", "1111010101010000", + "0101010101010101", "1010101010101010", + "1111111111111111", "0000000000000000", + "1111101010100000", "1111010101010000", + "0101010101010101", "1010101010101010", + "1111111111111111", "0000000000000000"); + ------------------------------------------------------------------- + -- Signals + ------------------------------------------------------------------- + signal Reset : Std_Logic; -- Synchro signal + signal RdClk : Std_Logic; -- Clock signal + signal WrClk : Std_Logic; -- Clock signal + signal DataIn : Std_Logic_Vector(15 downto 0); + signal DataOut : Std_Logic_Vector(15 downto 0); + signal Push_N : Std_Logic; + signal Pop_N : Std_Logic; + signal AlmFull : Std_Logic; + signal AlmEmpty : Std_Logic; + signal Full : Std_Logic; + signal Empty : Std_Logic; + ------------------------------------------------------------------- + -- Clock Generator + ------------------------------------------------------------------- + component ClkGen is + port ( + WrClk : out Std_Logic; -- Oscillator clock + RdClk : out Std_Logic); -- Oscillator clock + end component; + ------------------------------------------------------------------- + -- Sensor Control Unit + ------------------------------------------------------------------- + component FIFO is + port ( + DataIn : in Std_Logic_Vector(15 downto 0); + DataOut : out Std_Logic_Vector(15 downto 0); + WrClk : in Std_Logic; -- Clock signal + Push_N : in Std_Logic; -- Clock signal + RdClk : in Std_Logic; -- Clock signal + Pop_N : in Std_Logic; -- Clock signal + AlmFull : out Std_Logic; -- Status signal + AlmEmpty : out Std_Logic; -- Status signal + Full : out Std_Logic; -- Status signal + Empty : out Std_Logic; -- Status signal + Reset : in Std_Logic); -- Reset input + end component; +begin --======================== Architecture ========================-- + --------------------------------------------------------------------- + -- Instantiation of components + --------------------------------------------------------------------- + Clock : ClkGen port map (WrClk,RdClk); + Mem : FIFO port map (DataIn,DataOut,WrClk,Push_N,RdClk,Pop_N, + AlmFull,AlmEmpty,Full,Empty,Reset); + --------------------------------------------------------------------- + -- Reset cycle + --------------------------------------------------------------------- + RstCyc : process + begin + Reset <= '1'; + wait for 5 ns; + Reset <= '0'; + wait for 50 ns; + Reset <= '1'; + wait; + end process; + --------------------------------------------------------------------- + -- Read cycle + --------------------------------------------------------------------- + RdCyc : process(RdClk,Reset) + variable temp : Std_Logic := '0'; + variable i : Integer := 0; + begin + if Falling_Edge(Reset) then + temp := '0'; + i := 0; + Pop_N <= '1'; + elsif (Rising_Edge(RdClk) and Empty = '0') then + temp := not temp; + i := i + 1; + if i = 15 then + i := 0; + end if; + if temp = '0' then + Pop_N <= '0'; + else + Pop_N <= '1'; + end if; + end if; + end process; + --------------------------------------------------------------------- + -- Write cycle + --------------------------------------------------------------------- + WrCyc : process(WrClk,Reset) + variable temp : Std_Logic := '1'; + variable i : Integer := 0; + begin + if Falling_Edge(Reset) then + temp := '0'; + i := 0; + Push_N <= '1'; + elsif (Rising_Edge(WrClk) and Full = '0') then + temp := not temp; + i := i + 1; + if i = 15 then + i := 0; + end if; + if temp = '0' then + Push_N <= '0'; + DataIn <= Data(i); + else + Push_N <= '1'; + DataIn <= "ZZZZZZZZZZZZZZZZ"; + end if; + end if; + end process; +end stimulus; --================== End of TestBench ==================-- + Index: memory_cores/tags/first/FIFO2/FIFO_LIB.VHD =================================================================== --- memory_cores/tags/first/FIFO2/FIFO_LIB.VHD (nonexistent) +++ memory_cores/tags/first/FIFO2/FIFO_LIB.VHD (revision 25) @@ -0,0 +1,306 @@ +--============================================================================-- +-- +-- S Y N T H E Z I A B L E FIFO controller C O R E +-- +-- www.OpenCores.Org - May 2001 +-- This core adheres to the GNU public license +-- +-- Design units : FIFO-Def (Package declaration and body) +-- +-- File name : FIFO_Lib.vhd +-- +-- Purpose : This packages defines all the types used for +-- the FIFO design which are not contained +-- in the IEEE Std_Logic_1164 package. +-- +-- Errors : None known +-- +-- Library : FIFO_Lib +-- +-- Dependencies : None +-- +-- Author : Ovidiu Lupas +-- http://www.opencores.org/people/olupas +-- olupas@opencores.org +-- +-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC +-------------------------------------------------------------------------------- +-- Revision list +-- Version Author Date Changes +-- +-- 0.1 OL 15 April 99 New model +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- package FIFO_Def +-------------------------------------------------------------------------------- +library IEEE,STD; +use IEEE.Std_Logic_1164.all; +use IEEE.Numeric_Std.all; +--**-- +package FIFO_Def is + ----------------------------------------------------------------------------- + -- function definition + ----------------------------------------------------------------------------- + function "+"(left, right : bit_vector) + return bit_vector; + ----------------------------------------------------------------------------- + -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB + -- Error message for unknowns (U, X, W, Z, -), converted to 0 + -- Verifies whether vector is too long (> 16 bits) + ----------------------------------------------------------------------------- + function BV2Integer ( + Invector : in Std_Logic_Vector(3 downto 0)) + return Integer; + ----------------------------------------------------------------------------- + -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB + -- Error message for unknowns (U, X, W, Z, -), converted to 0 + -- Verifies whether vector is too long (> 16 bits) + ----------------------------------------------------------------------------- + function ToInteger ( + Invector : in Unsigned(3 downto 0)) + return Integer; + ------------------------------------------------------------------------- + -- internal GRAY counter 16 bits - count up + ------------------------------------------------------------------------- + component FIFOcnt + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Load : in Std_Logic; + Data16 : in Bit_Vector(15 downto 0); + CntOut : out Std_Logic); + end component; + --------------------------------------------------------------------- + -- Status counter for FIFO memory + --------------------------------------------------------------------- + component StatCnt + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Enable : in Std_Logic; + UpDown : in Std_Logic; + Full : out Std_Logic; + Empty : out Std_Logic; + AlmFull : out Std_Logic; + AlmEmpty : out Std_Logic); + end component; +end FIFO_Def; --================= End of package header ===================-- +package body FIFO_Def is + ------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------- + function "+"(left, right : bit_vector) + return bit_vector is + -- normalize the indexing + alias left_val : bit_vector(left'length downto 1) is left; + alias right_val : bit_vector(right'length downto 1) is right; + -- arbitrarily make the result the same size as the left input + variable result : bit_vector(left_val'RANGE); + -- temps + variable carry : bit := '0'; + variable right_bit : bit; + variable left_bit : bit; + begin + for i in result'reverse_range loop + left_bit := left_val(i); + if (i <= right_val'high) then + right_bit := right_val(i); + else + -- zero extend the right input + right_bit := '0'; + end if; + result(i) := (left_bit xor right_bit) xor carry; + carry := (left_bit and right_bit) + or (left_bit and carry) + or (right_bit and carry); + end loop; + return result; + end "+"; + ------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------- + --function "+"(left, right : Std_Logic_Vector) + -- return Std_Logic_Vector is + -- -- normalize the indexing + -- alias left_val : Std_Logic_Vector(left'length downto 1) is left; + -- alias right_val : Std_Logic_Vector(right'length downto 1) is right; + -- -- arbitrarily make the result the same size as the left input + -- variable result : Std_Logic_Vector(left_val'RANGE); + -- -- temps + -- variable carry : Std_Logic := '0'; + -- variable right_bit : Std_Logic; + -- variable left_bit : Std_Logic; + --begin + -- for i in result'reverse_range loop + -- left_bit := left_val(i); + -- if (i <= right_val'high) then + -- right_bit := right_val(i); + -- else + -- -- zero extend the right input + -- right_bit := '0'; + -- end if; + -- result(i) := (left_bit xor right_bit) xor carry; + -- carry := (left_bit and right_bit) + -- or (left_bit and carry) + -- or (right_bit and carry); + -- end loop; + -- return result; + --end "+"; + ------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------- + function BV2Integer ( + InVector : in Std_Logic_Vector(3 downto 0)) + return Integer is + constant HeaderMsg : String := "To_Integer:"; + constant MsgSeverity : Severity_Level := Warning; + variable Value : Integer := 0; + begin + for i in 0 to 3 loop + if (InVector(i) = '1') then + Value := Value + (2**I); + end if; + end loop; + return Value; + end BV2Integer; + ------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------- + function ToInteger ( + InVector : in Unsigned(3 downto 0)) + return Integer is + constant HeaderMsg : String := "To_Integer:"; + constant MsgSeverity : Severity_Level := Warning; + variable Value : Integer := 0; + begin + for i in 0 to 3 loop + if (InVector(i) = '1') then + Value := Value + (2**I); + end if; + end loop; + return Value; + end ToInteger; +end FIFO_Def; --================ End of package body ================-- +library ieee; +use ieee.Std_Logic_1164.all; +use ieee.Numeric_STD.all; +library work; +use work.FIFO_Def.all; +--------------------------------------------------------------------- +-- 16-bit GRAY counter +--------------------------------------------------------------------- +entity FIFOcnt is + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Enable : in Std_Logic; + CntOut : out Std_Logic_Vector(3 downto 0)); +end FIFOcnt; +----------------------------------------------------------------------- +-- Architecture for 16-bit GRAY counter - generates the internal clock +----------------------------------------------------------------------- +architecture Behaviour of FIFOcnt is + --------------------------------------------------------------------- + -- Signals + --------------------------------------------------------------------- + type CNT_Array is array(0 to 15) of Std_Logic_Vector(3 downto 0); + constant Cnt_Code : CNT_Array := ("0000","0010","0011","0001", + "1000","1010","1011","1001", + "1100","1110","1111","1101", + "0100","0110","0111","0101"); + signal binidx : Unsigned(3 downto 0); +begin --======================== Architecture =======================-- + process(ClkIn,Reset,Enable) + begin + if Reset = '1' then + binidx <= (others => '0'); + elsif ClkIn'Event and ClkIn = '1' then + if Enable = '1' then + binidx <= binidx + "1"; + end if; + end if; + end process; + CntOut <= Cnt_Code(ToInteger(binidx)); +end Behaviour; --================ End of architecture ================-- + +library ieee; +use ieee.Std_Logic_1164.all; +use ieee.Numeric_STD.all; +library work; +use work.FIFO_Def.all; +--------------------------------------------------------------------- +-- Up-Down counter for FIFO status +--------------------------------------------------------------------- +entity StatCnt is + port ( + ClkIn : in Std_Logic; + Reset : in Std_Logic; + Enable : in Std_Logic; + UpDown : in Std_Logic; + Full : out Std_Logic; + Empty : out Std_Logic; + AlmFull : out Std_Logic; + AlmEmpty : out Std_Logic); +end StatCnt; +----------------------------------------------------------------------- +-- Architecture for 16-bit GRAY counter - generates the internal clock +----------------------------------------------------------------------- +architecture Behaviour of StatCnt is + --------------------------------------------------------------------- + -- Signals + --------------------------------------------------------------------- + type CNT_Array is array(0 to 15) of Std_Logic_Vector(3 downto 0); + constant Cnt_Code : CNT_Array := ("0000","0001","0010","0011", + "0100","0101","0110","0111", + "1000","1001","1010","1011", + "1100","1101","1110","1111"); + signal binidx : Unsigned(3 downto 0); + signal CntOut : Integer; +begin --======================== Architecture =======================-- + process(ClkIn,Reset,Enable) + begin + if Reset = '1' then + binidx <= (others => '0'); + elsif (Rising_Edge(ClkIn) and Enable = '1') then + if UpDown = '1' then + binidx <= binidx + "1"; + else + binidx <= binidx - "1"; + end if; + end if; + CntOut <= ToInteger(binidx); + case CntOut is + when 0 => + Empty <= '1'; + AlmEmpty <= '0'; + AlmFull <= '0'; + Full <= '0'; + when 1 => + Empty <= '0'; + AlmEmpty <= '1'; + AlmFull <= '0'; + Full <= '0'; + when 2 => + Empty <= '0'; + AlmEmpty <= '1'; + AlmFull <= '0'; + Full <= '0'; + when 13 => + Empty <= '0'; + AlmEmpty <= '0'; + AlmFull <= '1'; + Full <= '0'; + when 14 => + Empty <= '0'; + AlmEmpty <= '0'; + AlmFull <= '1'; + Full <= '0'; + when 15 => + Empty <= '0'; + AlmEmpty <= '0'; + AlmFull <= '0'; + Full <= '1'; + when others => + Empty <= '0'; + AlmEmpty <= '0'; + AlmFull <= '0'; + Full <= '0'; + end case; + end process; +end Behaviour; --================ End of architecture ================-- Index: memory_cores/tags/sim/Vectors.do =================================================================== --- memory_cores/tags/sim/Vectors.do (nonexistent) +++ memory_cores/tags/sim/Vectors.do (revision 25) @@ -0,0 +1,105 @@ + +echo Copyright Jamil Khatib 1999 +echo +echo This test vector file is an open design, you can redistribute it and/or +echo modify it under the terms of the Openip Hardware General Public +echo License as as published by the OpenIP organization and any +echo coming versions of this license. +echo You can check the draft license at +echo http://www.openip.org/oc/license.html +echo +echo contact me at khatib@ieee.org +echo +echo +echo Creator : Jamil Khatib +echo Date 16/11/99 +echo +echo version 0.19991219 +echo ============================= + + +view source +view signals +view wave +add wave * + +#init clk +force clk 1 10, 0 20 -r 20 + +# init reset +force reset 0 0 +run 40 + +force reset 1 0 +run 40 + +#No read nor write +force data_in 00000000 0 +force we 0 0 +force re 0 0 +run 40 + +# write only cycles +force data_in 00001111 0 +force we 1 0 +run 20 + +force data_in 00000001 0 +force we 1 0 +run 20 + +force data_in 00000011 0 +force we 1 0 +run 20 + +# Read only cycles +force data_in 00000000 0 +force we 0 0 +force re 1 0 +run 20 + +force re 1 0 +run 20 + +force re 1 0 +run 20 + + +# Read and write from different addresses +force data_in 00000111 0 +force we 1 0 +force re 1 0 +run 20 + +# Read and write from different addresses +force data_in 00001111 0 +force we 1 0 +force re 1 0 +run 20 + + +# Read and Write from the same address +force data_in 00000000 0 +force we 1 0 +force re 1 0 +run 20 + +force data_in 00000000 0 +force we 1 0 +force re 1 0 +run 20 + +# reset system during Operation +run 10 +force reset 0 0 +force data_in 00000000 0 +force we 1 0 +force re 1 0 +run 20 + +force reset 1 0 +force data_in 11111111 0 +force we 1 0 +force re 1 0 +run 20 +run 20 \ No newline at end of file Index: memory_cores/tags/sim/fifo.vhdl =================================================================== --- memory_cores/tags/sim/fifo.vhdl (nonexistent) +++ memory_cores/tags/sim/fifo.vhdl (revision 25) @@ -0,0 +1,836 @@ +------------------------------------------------------------------------------- +-- +-- Copyright Jamil Khatib 1999 +-- +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it under the terms of the Openip General Public +-- License as it is going to be published by the OpenIP Organization and any +-- coming versions of this license. +-- You can check the draft license at +-- http://www.openip.org/oc/license.html +-- +-- +-- Creator : Jamil Khatib +-- Date 10/10/99 +-- +-- version 0.19991226 +-- +-- This file was tested on the ModelSim 5.2EE +-- The test vecors for model sim is included in vectors.do file +-- This VHDL design file is proved through simulation but not verified on Silicon +-- +-- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +USE ieee.std_logic_signed.ALL; + + + +-- Dual port Memory core + + + +ENTITY dpmem IS +generic ( ADD_WIDTH: integer := 8 ; + WIDTH : integer := 8); + PORT ( + clk : IN std_logic; -- write clock + reset : IN std_logic; -- System Reset + W_add : IN std_logic_vector(add_width -1 downto 0); -- Write Address + R_add : IN std_logic_vector(add_width -1 downto 0); -- Read Address + Data_In : IN std_logic_vector(WIDTH - 1 DOWNTO 0); -- input data + Data_Out : OUT std_logic_vector(WIDTH -1 DOWNTO 0); -- output Data + WR : IN std_logic; -- Write Enable + RE : IN std_logic); -- Read Enable +END dpmem; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +ARCHITECTURE dpmem_v3 OF dpmem IS + + + TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0); + -- Memory Type + SIGNAL data : data_array(0 to (2** add_width) ); -- Local data + + + + procedure init_mem(signal memory_cell : inout data_array ) is + begin + + for i in 0 to (2** add_width) loop + memory_cell(i) <= (others => '0'); + end loop; + + end init_mem; + + +BEGIN -- dpmem_v3 + + PROCESS (clk, reset) + + BEGIN -- PROCESS + + + -- activities triggered by asynchronous reset (active low) + IF reset = '0' THEN + data_out <= (OTHERS => '1'); + init_mem ( data); + + -- activities triggered by rising edge of clock + ELSIF clk'event AND clk = '1' THEN + IF RE = '1' THEN + data_out <= data(conv_integer(R_add)); + else + data_out <= (OTHERS => '1'); -- Defualt value + END IF; + + IF WR = '1' THEN + data(conv_integeR(W_add)) <= Data_In; + END IF; + END IF; + + + + END PROCESS; + + +END dpmem_v3; + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE ieee.std_logic_arith.ALL; + + +entity FIFO is + + generic (WIDTH : integer := 8; -- FIFO word width + ADD_WIDTH : integer := 8); -- Address Width + + port (Data_in : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + Data_out : out std_logic_vector(WIDTH - 1 downto 0); -- Out put data + clk : in std_logic; -- System Clock + Reset : in std_logic; -- System global Reset + RE : in std_logic; -- Read Enable + WE : in std_logic; -- Write Enable + Full : buffer std_logic; -- Full Flag + Half_full : out std_logic; -- Half Full Flag + Empty : buffer std_logic); -- Empty Flag + +end FIFO; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +-- Input data _is_ latched + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--USE ieee.std_logic_signed.ALL; +--USE ieee.std_logic_arith.ALL; + +------------------------------------------------------------------------------- +-- purpose: FIFO Architecture +architecture FIFO_v1 of FIFO is + +-- constant values + constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); + constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); + constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1'); + + signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in + + + signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address + signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address + signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address + + signal REN_INT : std_logic; -- Internal Read Enable + signal WEN_INT : std_logic; -- Internal Write Enable + + component dpmem + generic (ADD_WIDTH : integer := 8; + WIDTH : integer := 8 ); + + port (clk : in std_logic; + reset : in std_logic; + w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0 ); + WR : in std_logic; + RE : in std_logic); + end component; + + + +begin -- FIFO_v1 +------------------------------------------------------------------------------- + +memcore: dpmem +generic map (WIDTH => 8, + ADD_WIDTH =>8) + port map (clk => clk, + reset => reset, + w_add => w_add, + r_add => r_add, + Data_in => data_in_del, + data_out => data_out, + wr => wen_int, + re => ren_int); + +------------------------------------------------------------------------------- + +Sync_data: process(clk,reset) + begin -- process Sync_data + if reset ='0' then + data_in_del <= (others =>'0'); + + elsif clk'event and clk = '1' then + data_in_del <= data_in; + else + data_in_del <= data_in_del; + end if; + + + end process Sync_data; + +------------------------------------------------------------------------------- + +wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0'; + +ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0'; + +--w_r_gen: process(we,re,FULL,EMPTY) + +--begin + +-- if WE = '1' and (FULL = '0') then +-- wen_int <= '1'; +-- else +-- wen_int <= '0'; + +-- end if; + +-- if RE = '1' and ( EMPTY = '0') then +-- ren_int <= '1'; +-- else +-- ren_int <= '0'; +-- end if; + +--end process w_r_gen; + +------------------------------------------------------------------------------- + + +Add_gen: process(clk,reset) + variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + + begin -- process ADD_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + q1 := (others =>'0'); + q2 := (others =>'0'); + q3 := (others =>'0'); +-- wen_int <= '0'; +-- ren_int <= '0'; + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and ( FULL = '0') then + q1 := q1 + 1; + q3 := q3 +1; + -- wen_int <= '1'; + else + q1 := q1; + q3 := q3; + --wen_int <= '0'; + + end if; + + if RE = '1' and ( EMPTY = '0') then + q2 := q2 + 1; + q3 := q3 -1; + --ren_int <= '1'; + else + q2 := q2; + q3 := q3; + --ren_int <= '0'; + end if; + + end if; + + R_ADD <= q2; + W_ADD <= q1; + D_ADD <= q3; + + end process ADD_gen; + +------------------------------------------------------------------------------- + + FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; + EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; + HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; + + +------------------------------------------------------------------------------- + + + +end FIFO_v1; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Ren_int & Wen_int are synchronized with the clock + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--USE ieee.std_logic_signed.ALL; +--USE ieee.std_logic_arith.ALL; + +------------------------------------------------------------------------------- +-- purpose: FIFO Architecture +architecture FIFO_v2 of FIFO is + +-- constant values + constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); + constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); + constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := "01111111";--(ADD_WIDTH -1 => '0', others => '1'); + + + signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address + signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address + signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address + + signal REN_INT : std_logic; -- Internal Read Enable + signal WEN_INT : std_logic; -- Internal Write Enable + + component dpmem + generic (ADD_WIDTH : integer := 8; + WIDTH : integer := 8 ); + + port (clk : in std_logic; + reset : in std_logic; + w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0 ); + WR : in std_logic; + RE : in std_logic); + end component; + + + +begin -- FIFO_v2 + +------------------------------------------------------------------------------- + +memcore: dpmem + generic map (WIDTH => 8, + ADD_WIDTH =>8) + + port map (clk => clk, + reset => reset, + w_add => w_add, + r_add => r_add, + Data_in => data_in, + data_out => data_out, + wr => wen_int, + re => ren_int); + +------------------------------------------------------------------------------- + +cont_gen: process(clk,reset) + begin -- process cont_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + wen_int <= '0'; + ren_int <= '0'; + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and (not FULL = '1') then + wen_int <= '1'; + else + wen_int <= '0'; + + end if; + + if RE = '1' and (not EMPTY = '1') then + ren_int <= '1'; + else + ren_int <= '0'; + end if; + + end if; + + end process cont_gen; + + +------------------------------------------------------------------------------- + +Add_gen: process(clk,reset) + variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + + begin -- process ADD_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + q1 := (others =>'0'); + q2 := (others =>'0'); + q3 := (others =>'0'); + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and ( FULL = '0') then + q1 := q1 + 1; + q3 := q3 +1; + else + q1 := q1; + q3 := q3; + + end if; + + if RE = '1' and ( EMPTY = '0') then + q2 := q2 + 1; + q3 := q3 -1; + else + q2 := q2; + q3 := q3; + end if; + + end if; + + R_ADD <= q2; + W_ADD <= q1; + D_ADD <= q3; + + end process ADD_gen; + +------------------------------------------------------------------------------- + + FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; + EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; + HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; + +------------------------------------------------------------------------------- + +end FIFO_v2; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +-- Input data is _NOT_ latched + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--USE ieee.std_logic_signed.ALL; +--USE ieee.std_logic_arith.ALL; + +------------------------------------------------------------------------------- +-- purpose: FIFO Architecture +architecture FIFO_v3 of FIFO is + +-- constant values + constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); + constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); + constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1'); + + + signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address + signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address + signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address + + signal REN_INT : std_logic; -- Internal Read Enable + signal WEN_INT : std_logic; -- Internal Write Enable + + component dpmem + generic (ADD_WIDTH : integer := 8; + WIDTH : integer := 8 ); + + port (clk : in std_logic; + reset : in std_logic; + w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0 ); + WR : in std_logic; + RE : in std_logic); + end component; + + + +begin -- FIFO_v3 + +------------------------------------------------------------------------------- + +memcore: dpmem +generic map (WIDTH => 8, + ADD_WIDTH =>8) + port map (clk => clk, + reset => reset, + w_add => w_add, + r_add => r_add, + Data_in => data_in, + data_out => data_out, + wr => wen_int, + re => ren_int); + +------------------------------------------------------------------------------- + +wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0'; + +ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0'; + + +------------------------------------------------------------------------------- + +Add_gen: process(clk,reset) + variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state + + begin -- process ADD_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + q1 := (others =>'0'); + q2 := (others =>'0'); + q3 := (others =>'0'); + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and ( FULL = '0') then + q1 := q1 + 1; + q3 := q3 +1; + else + q1 := q1; + q3 := q3; + + end if; + + if RE = '1' and ( EMPTY = '0') then + q2 := q2 + 1; + q3 := q3 -1; + else + q2 := q2; + q3 := q3; + end if; + + end if; + + R_ADD <= q2; + W_ADD <= q1; + D_ADD <= q3; + + end process ADD_gen; + +------------------------------------------------------------------------------- + + FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; + EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; + HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; + + +------------------------------------------------------------------------------- + + +end FIFO_v3; + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +-- This arch was synthesized by webfitter +-- It is the same as fifo_v1 but +-- 1. address variables was changed to signals +-- 2. else statement was removed from process sync_data +-- 3. address-width was changed to 3 instead of 8 +-- Input data _is_ latched + +library ieee; +-- numeric package genertes compile error by webfitter compiler +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE ieee.std_logic_arith.ALL; + +------------------------------------------------------------------------------- +-- purpose: FIFO Architecture +architecture FIFO_v4 of FIFO is + +-- constant values + constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); + constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); + constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1'); + + signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in + + + signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address + signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address + signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address + + signal REN_INT : std_logic; -- Internal Read Enable + signal WEN_INT : std_logic; -- Internal Write Enable + + component dpmem + generic (ADD_WIDTH : integer := 8; + WIDTH : integer := 8 ); + + port (clk : in std_logic; + reset : in std_logic; + w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0 ); + WR : in std_logic; + RE : in std_logic); + end component; + + + +begin -- FIFO_v4 +------------------------------------------------------------------------------- + +memcore: dpmem +generic map (WIDTH => 8, + ADD_WIDTH =>8) + port map (clk => clk, + reset => reset, + w_add => w_add, + r_add => r_add, + Data_in => data_in_del, + data_out => data_out, + wr => wen_int, + re => ren_int); + +------------------------------------------------------------------------------- + +Sync_data: process(clk,reset) + begin -- process Sync_data + if reset ='0' then + data_in_del <= (others =>'0'); + + elsif clk'event and clk = '1' then + data_in_del <= data_in; + +-- else statemnet was removed due to error (hdl +-- + end if; + + + end process Sync_data; + +------------------------------------------------------------------------------- + +wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0'; + +ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0'; + +------------------------------------------------------------------------------- + + +Add_gen: process(clk,reset) +-- The variables was replaced by add signals + + begin -- process ADD_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + W_ADD <= (others =>'0'); + R_ADD <= (others =>'0'); + D_ADD <= (others =>'0'); + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and ( FULL = '0') then + W_ADD <= W_ADD + 1; + D_ADD <= D_ADD +1; +-- else +-- W_ADD <= W_ADD; +-- D_ADD <= D_ADD; + + end if; + + if RE = '1' and ( EMPTY = '0') then + R_ADD <= R_ADD + 1; + D_ADD <= D_ADD -1; +-- else +-- R_ADD <= R_ADD; +-- D_ADD <= D_ADD; + end if; + + end if; + + + end process ADD_gen; + +------------------------------------------------------------------------------- + + FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; + EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; + HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; + + +------------------------------------------------------------------------------- + + + +end FIFO_v4; + +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +-- synthesized using webfitter +-- Input data is _NOT_ latched +-- The same as fifo_v3 but without the use of the variables in add_gen process +-- else case in add_gen "RE and WE" was removed + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +USE ieee.std_logic_signed.ALL; +USE ieee.std_logic_arith.ALL; + +------------------------------------------------------------------------------- +-- purpose: FIFO Architecture +architecture FIFO_v5 of FIFO is + +-- constant values + constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); + constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); + constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1'); + + signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address + signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address + signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address + + signal REN_INT : std_logic; -- Internal Read Enable + signal WEN_INT : std_logic; -- Internal Write Enable + + component dpmem + generic (ADD_WIDTH : integer := 8; + WIDTH : integer := 8 ); + + port (clk : in std_logic; + reset : in std_logic; + w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); + data_in : in std_logic_vector(WIDTH - 1 downto 0); + data_out : out std_logic_vector(WIDTH - 1 downto 0 ); + WR : in std_logic; + RE : in std_logic); + end component; + + + +begin -- FIFO_v5 + +------------------------------------------------------------------------------- + +memcore: dpmem +generic map (WIDTH => 8, + ADD_WIDTH =>8) + port map (clk => clk, + reset => reset, + w_add => w_add, + r_add => r_add, + Data_in => data_in, + data_out => data_out, + wr => wen_int, + re => ren_int); + +------------------------------------------------------------------------------- + +wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0'; + +ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0'; + + +------------------------------------------------------------------------------- + +Add_gen: process(clk,reset) + + begin -- process ADD_gen + + -- activities triggered by asynchronous reset (active low) + if reset = '0' then + W_ADD <= (others =>'0'); + R_ADD <= (others =>'0'); + D_ADD <= (others =>'0'); + -- activities triggered by rising edge of clock + elsif clk'event and clk = '1' then + + if WE = '1' and ( FULL = '0') then + W_ADD <= W_ADD + 1; + D_ADD <= D_ADD +1; +-- else +-- W_ADD <= W_ADD; +-- D_ADD <= D_ADD; + + end if; + + if RE = '1' and ( EMPTY = '0') then + R_ADD <= R_ADD + 1; + D_ADD <= D_ADD -1; +-- else +-- R_ADD <= R_ADD; +-- D_ADD <= D_ADD; + end if; + + end if; + +-- R_ADD <= q2; +-- W_ADD <= q1; +-- D_ADD <= q3; + + end process ADD_gen; + +------------------------------------------------------------------------------- + + FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; + EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; + HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; + + +------------------------------------------------------------------------------- + + +end FIFO_v5; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +configuration fifo_conf of fifo is + for fifo_v1 + for memcore:dpmem + use entity work.dpmem(dpmem_v3); + end for; + end for; + +end fifo_conf; + + Index: memory_cores/tags =================================================================== --- memory_cores/tags (nonexistent) +++ memory_cores/tags (revision 25)

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