URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat
0,0 → 1,47
::############################################################################### |
::# # |
::# Xilinx RAM update script for WINDOWS # |
::# # |
::############################################################################### |
|
::############################################################################### |
::# Specify Program to be loaded # |
::############################################################################### |
|
set MSP430_PROGRAM=leds |
::set MSP430_PROGRAM=ta_uart |
|
|
::############################################################################### |
::# Check if the required files exist # |
::############################################################################### |
set softdir=..\..\software\%MSP430_PROGRAM% |
set elffile=..\..\software\%MSP430_PROGRAM%\%MSP430_PROGRAM%.elf |
|
IF EXIST %softdir% GOTO :DIR_OKAY |
ECHO ERROR: Software directory doesn't exist: %softdir% |
PAUSE |
EXIT |
:DIR_OKAY |
|
IF EXIST %elffile% GOTO :ELF_OKAY |
ECHO ERROR: ELF file doesn't exist: %elffile% |
PAUSE |
EXIT |
:ELF_OKAY |
|
|
::############################################################################### |
::# Update FPGA Bitstream # |
::############################################################################### |
|
|
DEL /f .\WORK\%MSP430_PROGRAM%.elf |
DEL /f .\WORK\%MSP430_PROGRAM%.bit |
|
XCOPY %elffile% .\WORK\ |
|
cd .\WORK |
data2mem -bm ..\memory.bmm -bd %MSP430_PROGRAM%.elf -bt openMSP430_fpga_top.bit -o b %MSP430_PROGRAM%.bit |
cd ..\ |
PAUSE |
openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat
===================================================================
--- openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat (nonexistent)
+++ openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat (revision 25)
@@ -0,0 +1,52 @@
+::######################################################
+::# #
+::# Xilinx Synthesis, Place & Route script for WINDOWS #
+::# #
+::######################################################
+
+:: Cleanup
+RMDIR /S /Q .\WORK
+MKDIR WORK
+cd ./WORK
+
+:: Copy the RAM & ROM ngc files
+XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_hi.ngc .
+XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_lo.ngc .
+XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_hi.ngc .
+XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_lo.ngc .
+
+:: Copy the timescale and the openMSP430 configuration files
+XCOPY ..\..\..\rtl\verilog\timescale.v .
+XCOPY ..\..\..\rtl\verilog\openMSP430_defines.v .
+
+:: Copy the Xilinx constraints file
+XCOPY ..\openMSP430_fpga_top.ucf .
+
+
+:: XFLOW
+::---------------
+
+xflow -p 3S200FT256-4 -implement high_effort.opt ^
+ -config bitgen.opt ^
+ -synth xst_verilog.opt ^
+ ..\openMSP430_fpga_top.v
+
+:: MANUAL FLOW
+::---------------
+
+::xst -intstyle xflow -ifn ..\openMSP430_fpga.xst
+
+::ngdbuild -p xc3s200-4-ft256 -uc ..\openMSP430_fpga.ucf openMSP430_fpga
+
+::map -k 6 -detail -pr b openMSP430_fpga
+
+::par -ol med -w openMSP430_fpga.ncd openMSP430_fpga
+
+::trce -e -o openMSP430_fpga_err.twr openMSP430_fpga
+::trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga
+
+::bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga
+
+
+cd ..
+PAUSE
\ No newline at end of file
openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property