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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

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Rev 24 → Rev 25

/raytrac/trunk/arithpack.vhd
47,6 → 47,10
 
component opcoder
generic (
width : integer := 18;
structuralDescription : string:= "NO"
)
port (
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
/raytrac/trunk/opcoder.vhd
33,12 → 33,13
--! \n\n
--! Las entradas a esta descripción son: los vectores A,B,C,D, las entradas opcode y addcode. Las salidas del decodificador, estarán conectadas a las entradas de los 6 multiplicadores de una entidad uf. Los operandos de los multiplicadores, también conocidos como factores, son las salida m0f0, m0f1 para el multiplicador 1 y así hasta el multiplicador 5. Básicamente lo que opera aquí en esta descripción es un multiplexor, el cual selecciona a través de opcode y addcode qué componentes de los vectores se conectaran a los operandos de los multiplicadores.
entity opcoder is
generic (
fastmux : string:= "NO"
generic (
width : integer := 18;
structuralDescription : string:= "NO"
)
port (
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (width-1 downto 0);
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (width-1 downto 0);
opcode,addcode : in std_logic
);
57,7 → 58,7
 
architecture opcoder_arch of opcoder is
signal aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(17 downto 0);
signal aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(width-1 downto 0);
begin
--! Proceso que describe las 2 etapas de multiplexores.
64,40 → 65,42
 
 
originalMuxGen:
if fastmux="NO" generate
if behavioralDescription="NO" generate
procOpcoder:
process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
variable scoder : std_logic_vector (1 downto 0);
begin
scoder := opcode & addcode;
case (scoder) is
when "10" =>
m0f0 <= Ay;
m0f1 <= Bz;
m1f0 <= Az;
m1f1 <= By;
m2f0 <= Az;
m2f1 <= Bx;
m3f0 <= Ax;
m3f1 <= Bz;
m4f0 <= Ax;
m4f1 <= By;
m5f0 <= Ay;
m5f1 <= Bx;
when "11" =>
m0f0 <= Cy;
m0f1 <= Dz;
m1f0 <= Cz;
m1f1 <= Dy;
m2f0 <= Cz;
m2f1 <= Dx;
m3f0 <= Cx;
m3f1 <= Dz;
m4f0 <= Cx;
m4f1 <= Dy;
m5f0 <= Cy;
m5f1 <= Dx;
begin
case (addcode) is
when "1" =>
aycy <= Cy;
bzdz <= Dz;
azcz <= Cz;
bydy <= Dy;
axcx <= Cx;
bxdx <= Dx;
when others =>
aycy <= Ay;
bzdz <= Bz;
azcz <= Az;
bydy <= By;
axcx <= Ax;
bxdx <= Bx;
end case;
case (opcode) is
when "1" =>
m0f0 <= aycy;
m0f1 <= bzdz;
m1f0 <= azcz;
m1f1 <= bydy;
m2f0 <= axcx;
m2f1 <= bzdz;
m3f0 <= azcz;
m3f1 <= bxdx;
m4f0 <= axcx;
m4f1 <= bydy;
m5f0 <= aycy;
m5f1 <= bxdx;
when others =>
m0f0 <= Ax;
m0f1 <= Bx;
111,17 → 114,11
m4f1 <= Dy;
m5f0 <= Cz;
m5f1 <= Dz;
 
end case;
end process procOpcoder;
end generate originalMuxGen;
fastMuxGen:
if fastmux="YES" generate
if structuralDescription="YES" generate
mux0 : fastmux (ay,cy,addcode,aycy);
mux1 : fastmux (bz,dz,addcode,bzdz);
mux2 : fastmux (az,cz,addcode,azcz);

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