URL
https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
Subversion Repositories rtf65002
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- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/rtf65002/trunk/rtl/verilog/decode.v
25,30 → 25,57
first_ifetch <= `TRUE; |
Rt <= 4'h0; // Default |
state <= IFETCH; |
pc <= pcp1; |
case(ir[7:0]) |
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end |
`NOP: begin pc <= pc + 32'd1; end |
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end |
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end |
`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end |
`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end |
`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end |
`SED: begin df <= 1'b1; pc <= pc + 32'd1; end |
`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end |
`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end |
`EMM: begin em <= 1'b1; pc <= pc + 32'd1; end |
`DEX: begin res <= x - 32'd1; pc <= pc + 32'd1; end |
`INX: begin res <= x + 32'd1; pc <= pc + 32'd1; end |
`DEY: begin res <= y - 32'd1; pc <= pc + 32'd1; end |
`INY: begin res <= y + 32'd1; pc <= pc + 32'd1; end |
`DEA: begin res <= acc - 32'd1; pc <= pc + 32'd1; end |
`INA: begin res <= acc + 32'd1; pc <= pc + 32'd1; end |
`TSX,`TSA: begin res <= isp; pc <= pc + 32'd1; end |
`TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end |
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end |
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end |
`STP: begin clk_en <= 1'b0; end |
`NOP: casex(ir[63:0]) |
{`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8; |
{8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7; |
{16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6; |
{24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5; |
{32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4; |
{40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3; |
{48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2; |
{56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1; |
endcase |
`CLC: begin cf <= 1'b0; end |
`SEC: begin cf <= 1'b1; end |
`CLV: begin vf <= 1'b0; end |
`CLI: begin im <= 1'b0; end |
`CLD: begin df <= 1'b0; end |
`SED: begin df <= 1'b1; end |
`SEI: begin im <= 1'b1; end |
`WAI: begin wai <= 1'b1; end |
`EMM: begin em <= 1'b1; end |
`DEX: begin |
res <= x - 32'd1; |
// DEX/BNE accelerator |
// if (ir[15:8]==`BNE) begin |
// if (x!=32'd1) begin |
// if (ir[23:16]==8'h01) |
// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1; |
// else |
// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1; |
// end |
// else begin |
// if (ir[23:16]==8'h01) |
// pc <= pcp5; |
// else |
// pc <= pcp3; |
// end |
// end |
end |
`INX: begin res <= x + 32'd1; end |
`DEY: begin res <= y - 32'd1; end |
`INY: begin res <= y + 32'd1; end |
`DEA: begin res <= acc - 32'd1; end |
`INA: begin res <= acc + 32'd1; end |
`TSX,`TSA: begin res <= isp; end |
`TXS,`TXA,`TXY: begin res <= x; end |
`TAX,`TAY,`TAS: begin res <= acc; end |
`TYA,`TYX: begin res <= y; end |
`TRS: begin |
res <= rfoa; pc <= pc + 32'd2; end |
res <= rfoa; pc <= pcp2; end |
`TSR: begin |
Rt <= ir[15:12]; |
case(ir[11:8]) |
65,12 → 92,12
4'hE: res <= {spage[31:8],sp}; |
4'hF: res <= isp; |
endcase |
pc <= pc + 32'd2; |
pc <= pcp2; |
end |
`ASL_ACC: begin res <= {acc,1'b0}; pc <= pc + 32'd1; end |
`ROL_ACC: begin res <= {acc,cf}; pc <= pc + 32'd1; end |
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; pc <= pc + 32'd1; end |
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; pc <= pc + 32'd1; end |
`ASL_ACC: begin res <= {acc,1'b0}; end |
`ROL_ACC: begin res <= {acc,cf};end |
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; end |
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; end |
|
`RR: |
begin |
91,47 → 118,49
`LSR_RRR: begin a <= rfoa; b <= rfob; state <= CALC; end |
endcase |
Rt <= ir[19:16]; |
pc <= pc + 32'd3; |
pc <= pcp3; |
end |
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; pc <= pc + 32'd2; end |
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`ROL_RR: begin res <= {rfoa,cf}; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`DEC_RR: begin res <= rfoa - 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`INC_RR: begin res <= rfoa + 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end |
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; pc <= pcp2; end |
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pcp2; Rt <= ir[15:12]; end |
`ROL_RR: begin res <= {rfoa,cf}; pc <= pcp2; Rt <= ir[15:12]; end |
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pcp2; Rt <= ir[15:12]; end |
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pcp2; Rt <= ir[15:12]; end |
`DEC_RR: begin res <= rfoa - 32'd1; pc <= pcp2; Rt <= ir[15:12]; end |
`INC_RR: begin res <= rfoa + 32'd1; pc <= pcp2; Rt <= ir[15:12]; end |
|
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end |
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end |
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end |
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end |
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end |
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; Rt <= 4'h0; pc <= pc + 32'd2; b <= {{24{ir[15]}},ir[15:8]}; end |
`ASL_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end |
`LSR_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end |
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pcp3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end |
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pcp3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end |
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end |
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end |
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end |
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; Rt <= 4'h0; pc <= pcp2; b <= {{24{ir[15]}},ir[15:8]}; end |
`ASL_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pcp3; state <= CALC; end |
`LSR_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pcp3; state <= CALC; end |
|
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end |
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end |
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end |
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end |
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end |
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pcp4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end |
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pcp4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end |
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end |
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end |
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end |
|
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12] + {31'b0,df&cf}; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end |
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12] - {31'b0,df&~cf&|ir[15:12]}; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end |
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end |
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end |
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end |
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12] + {31'b0,df&cf}; pc <= pcp6; a <= rfoa; b <= ir[47:16]; end |
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12] - {31'b0,df&~cf&|ir[15:12]}; pc <= pcp6; a <= rfoa; b <= ir[47:16]; end |
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end |
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end |
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end |
|
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pc + 32'd5; end |
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end |
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end |
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pcp5; end |
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pcp3; end |
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pcp2; end |
|
`SUB_SP: begin res <= isp - {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end |
`SUB_SP8: begin res <= isp - {{24{ir[15]}},ir[15:8]}; pc <= pcp2; end |
`SUB_SP16: begin res <= isp - {{16{ir[23]}},ir[23:8]}; pc <= pcp3; end |
`SUB_SP32: begin res <= isp - ir[39:8]; pc <= pcp5; end |
|
`LDX_ZPX,`LDY_ZPX: |
begin |
radr <= zpx32xy_address; |
pc <= pc + 32'd3; |
pc <= pcp3; |
load_what <= `WORD_311; |
state <= LOAD_MAC1; |
end |
141,7 → 170,7
Rt <= ir[19:16]; |
radr <= zpx32_address[31:2]; |
radr2LSB <= zpx32_address[1:0]; |
pc <= pc + 32'd4; |
pc <= pcp4; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
148,7 → 177,7
`LDX_ABS,`LDY_ABS: |
begin |
radr <= ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
load_what <= `WORD_311; |
state <= LOAD_MAC1; |
end |
158,7 → 187,7
Rt <= ir[15:12]; |
radr <= ir[47:18]; |
radr2LSB <= ir[17:16]; |
pc <= pc + 32'd6; |
pc <= pcp6; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
165,7 → 194,7
`LDX_ABSY,`LDY_ABSX: |
begin |
radr <= absx32xy_address; |
pc <= pc + 32'd6; |
pc <= pcp6; |
load_what <= `WORD_311; |
state <= LOAD_MAC1; |
end |
175,7 → 204,7
Rt <= ir[19:16]; |
radr <= absx32_address[31:2]; |
radr2LSB <= absx32_address[1:0]; |
pc <= pc + 32'd7; |
pc <= pcp7; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
183,7 → 212,7
begin |
wadr <= zpx32_address; |
wdat <= rfoa; |
pc <= pc + 32'd4; |
pc <= pcp4; |
state <= STORE1; |
end |
`STB_ZPX: |
190,7 → 219,8
begin |
wadr <= zpx32_address[31:2]; |
wadr2LSB <= zpx32_address[1:0]; |
pc <= pc + 32'd4; |
wdat <= {4{rfoa[7:0]}}; |
pc <= pcp4; |
state <= STORE1; |
end |
`ST_DSP: |
197,7 → 227,7
begin |
wadr <= {{24{ir[23]}},ir[23:16]} + isp; |
wdat <= rfoa; |
pc <= pc + 32'd3; |
pc <= pcp3; |
state <= STORE1; |
end |
`ST_ABS: |
204,7 → 234,7
begin |
wadr <= ir[47:16]; |
wdat <= rfoa; |
pc <= pc + 32'd6; |
pc <= pcp6; |
state <= STORE1; |
end |
`STB_ABS: |
212,7 → 242,7
wadr <= ir[47:18]; |
wadr2LSB <= ir[17:16]; |
wdat <= {4{rfoa[7:0]}}; |
pc <= pc + 32'd6; |
pc <= pcp6; |
state <= STORE1; |
end |
`ST_ABSX: |
219,7 → 249,7
begin |
wadr <= absx32_address; |
wdat <= rfoa; |
pc <= pc + 32'd7; |
pc <= pcp7; |
state <= STORE1; |
end |
`STB_ABSX: |
227,7 → 257,7
wadr <= absx32_address[31:2]; |
wadr2LSB <= absx32_address[1:0]; |
wdat <= {4{rfoa[7:0]}}; |
pc <= pc + 32'd7; |
pc <= pcp7; |
state <= STORE1; |
end |
`STX_ZPX: |
234,7 → 264,7
begin |
wadr <= dp + ir[23:12] + rfoa; |
wdat <= x; |
pc <= pc + 32'd3; |
pc <= pcp3; |
state <= STORE1; |
end |
`STX_ABS: |
241,7 → 271,7
begin |
wadr <= ir[39:8]; |
wdat <= x; |
pc <= pc + 32'd5; |
pc <= pcp5; |
state <= STORE1; |
end |
`STY_ZPX: |
248,7 → 278,7
begin |
wadr <= dp + ir[23:12] + rfoa; |
wdat <= y; |
pc <= pc + 32'd3; |
pc <= pcp3; |
state <= STORE1; |
end |
`STY_ABS: |
255,7 → 285,7
begin |
wadr <= ir[39:8]; |
wdat <= y; |
pc <= pc + 32'd5; |
pc <= pcp5; |
state <= STORE1; |
end |
`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX: |
263,7 → 293,7
a <= rfoa; |
Rt <= ir[19:16]; |
radr <= zpx32_address; |
pc <= pc + 32'd4; |
pc <= pcp4; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
270,7 → 300,7
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX: |
begin |
radr <= dp + rfoa + ir[23:12]; |
pc <= pc + 32'd3; |
pc <= pcp3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
279,7 → 309,7
a <= rfoa; |
Rt <= ir[15:12]; |
radr <= {{24{ir[23]}},ir[23:16]} + isp; |
pc <= pc + 32'd3; |
pc <= pcp3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
286,41 → 316,35
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX: |
begin |
a <= rfoa; |
if (ir[7:0]==`ST_IX) |
res <= rfoa; // for ST_IX, Rt=0 |
else |
if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0 |
Rt <= ir[19:16]; |
pc <= pc + 32'd4; |
pc <= pcp4; |
radr <= dp + ir[31:20] + rfob; |
load_what <= `IA_310; |
state <= LOAD_MAC1; |
end |
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND: |
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND: |
begin |
radr <= rfob; |
wadr <= rfob; // for store |
wdat <= rfoa; |
a <= rfoa; |
if (ir[7:0]==`ST_RIND) begin |
res <= rfoa; // for ST_IX, Rt=0 |
pc <= pc + 32'd2; |
state <= STORE1; |
end |
else begin |
Rt <= ir[19:16]; |
pc <= pc + 32'd3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
Rt <= ir[19:16]; |
pc <= pcp3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
`ST_RIND: |
begin |
wadr <= rfob; |
wdat <= rfoa; |
pc <= pcp2; |
state <= STORE1; |
end |
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY: |
begin |
a <= rfoa; |
if (ir[7:0]==`ST_IY) |
res <= rfoa; // for ST_IY, Rt=0 |
else |
if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0 |
Rt <= ir[19:16]; |
pc <= pc + 32'd4; |
pc <= pcp4; |
isIY <= 1'b1; |
radr <= dp + ir[31:20]; |
load_what <= `IA_310; |
331,7 → 355,7
a <= rfoa; |
radr <= ir[47:16]; |
Rt <= ir[15:12]; |
pc <= pc + 32'd6; |
pc <= pcp6; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
338,7 → 362,7
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS: |
begin |
radr <= ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
347,7 → 371,7
a <= rfoa; |
radr <= ir[55:24] + rfob; |
Rt <= ir[19:16]; |
pc <= pc + 32'd7; |
pc <= pcp7; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
354,7 → 378,7
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX: |
begin |
radr <= ir[47:16] + rfob; |
pc <= pc + 32'd6; |
pc <= pcp6; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
361,19 → 385,19
`CPX_IMM32: |
begin |
res <= x - ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
state <= IFETCH; |
end |
`CPY_IMM32: |
begin |
res <= y - ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
state <= IFETCH; |
end |
`CPX_ZPX: |
begin |
radr <= dp + ir[23:12] + rfoa; |
pc <= pc + 32'd3; |
pc <= pcp3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
380,7 → 404,7
`CPY_ZPX: |
begin |
radr <= dp + ir[23:12] + rfoa; |
pc <= pc + 32'd3; |
pc <= pcp3; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
387,7 → 411,7
`CPX_ABS: |
begin |
radr <= ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
394,7 → 418,7
`CPY_ABS: |
begin |
radr <= ir[39:8]; |
pc <= pc + 32'd5; |
pc <= pcp5; |
load_what <= `WORD_310; |
state <= LOAD_MAC1; |
end |
403,13 → 427,13
bf <= 1'b1; |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd1; |
wdat <= pc+2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd1; |
dat_o <= pc+2; |
vect <= {vbr[31:9],`BRK_VECTNO,2'b00}; |
state <= IRQ1; |
end |
460,13 → 484,13
begin |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd3; |
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd3; |
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
vect <= {pc[31:16],ir[23:8]}; |
state <= JSR1; |
end |
489,13 → 513,13
begin |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd5; |
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd5; |
dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2; |
vect <= ir[39:8]; |
state <= JSR1; |
end |
503,13 → 527,13
begin |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd3; |
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd3; |
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
vect <= pc + {{16{ir[23]}},ir[23:8]}; |
state <= JSR1; |
end |
517,13 → 541,13
begin |
radr <= isp - 32'd1; |
wadr <= isp - 32'd1; |
wdat <= pc + 32'd5; |
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp-32'd1,2'b00}; |
dat_o <= pc + 32'd5; |
dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2; |
state <= JSR_INDX1; |
end |
// `JSR16: |
570,13 → 594,13
if (takb) |
pc <= pc + {{16{ir[31]}},ir[31:16]}; |
else |
pc <= pc + 32'd4; |
pc <= pcp4; |
end |
else begin |
if (takb) |
pc <= pc + {{24{ir[15]}},ir[15:8]}; |
else |
pc <= pc + 32'd2; |
pc <= pcp2; |
end |
end |
/* `BEQ_RR: |
613,13 → 637,13
if (ir[23:8]==16'h0000) begin |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd3; |
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd3; |
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2; |
vect <= {vbr[31:9],`SLP_VECTNO,2'b00}; |
state <= IRQ1; |
end |
628,6 → 652,13
state <= IFETCH; |
end |
end |
`EXEC,`ATNI: |
begin |
exbuf[31:0] <= rfoa; |
exbuf[63:32] <= rfob; |
pc <= pc + 32'd2; |
state <= IFETCH; |
end |
`PHP: |
begin |
cyc_o <= 1'b1; |
640,7 → 671,7
adr_o <= {isp_dec,2'b00}; |
dat_o <= sr; |
isp <= isp_dec; |
state <= PHP1; |
state <= STORE2; |
end |
`PHA: |
begin |
654,7 → 685,7
adr_o <= {isp_dec,2'b00}; |
dat_o <= acc; |
isp <= isp_dec; |
state <= PHP1; |
state <= STORE2; |
end |
`PHX: |
begin |
668,7 → 699,7
adr_o <= {isp_dec,2'b00}; |
dat_o <= x; |
isp <= isp_dec; |
state <= PHP1; |
state <= STORE2; |
end |
`PHY: |
begin |
682,7 → 713,7
adr_o <= {isp_dec,2'b00}; |
dat_o <= y; |
isp <= isp_dec; |
state <= PHP1; |
state <= STORE2; |
end |
`PUSH: |
begin |
695,14 → 726,13
wdat <= rfoa; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= rfoa; |
state <= PHP1; |
state <= STORE2; |
isp <= isp_dec; |
pc <= pc + 32'd1; |
pc <= pcp2; |
end |
`PLP: |
begin |
radr <= isp; |
pc <= pc + 32'd1; |
load_what <= `SR_310; |
state <= LOAD_MAC1; |
end |
712,7 → 742,6
isp <= isp_inc; |
load_what <= `WORD_311; |
state <= LOAD_MAC1; |
pc <= pc + 32'd1; |
end |
`POP: |
begin |
721,21 → 750,21
isp <= isp_inc; |
load_what <= `WORD_311; |
state <= LOAD_MAC1; |
pc <= pc + 32'd2; |
pc <= pcp2; |
end |
`MVN: state <= MVN1; |
`MVP: state <= MVP1; |
// `MVN: state <= MVN1; |
// `MVP: state <= MVP1; |
default: // unimplemented opcode |
begin |
radr <= isp_dec; |
wadr <= isp_dec; |
wdat <= pc + 32'd1; |
wdat <= suppress_pcinc[0] ? pc + 32'd1 : pc + 32'd2; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 4'hF; |
adr_o <= {isp_dec,2'b00}; |
dat_o <= pc + 32'd1; |
dat_o <= suppress_pcinc[0] ? pc + 32'd1 : pc + 32'd2; |
vect <= {vbr[31:9],9'd495,2'b00}; |
state <= IRQ1; |
end |
/rtf65002/trunk/rtl/verilog/php.v
31,7 → 31,7
sel_o <= 4'h0; |
adr_o <= 34'd0; |
dat_o <= 32'd0; |
pc <= pc + 32'd1; // <= this is different from STORE2 |
// pc <= pc + 32'd1; // <= this is different from STORE2 |
if (dhit) begin |
wr <= 1'b1; |
wrsel <= sel_o; |
/rtf65002/trunk/rtl/verilog/rtf65002d.v
382,9 → 382,13
`define BEQ_RR 8'hE2 |
`define INT0 8'hDC |
`define INT1 8'hDD |
`define SUB_SP 8'h4B |
`define SUB_SP8 8'h85 |
`define SUB_SP16 8'h99 |
`define SUB_SP32 8'h89 |
`define MVP 8'h44 |
`define MVN 8'h54 |
`define EXEC 8'hEB |
`define ATNI 8'h4B |
|
`define NOTHING 4'd0 |
`define SR_70 4'd1 |
640,8 → 644,51
assign v = (op ^ s ^ b) & (~op ^ a ^ b); |
|
endmodule |
/* |
// This table being setup to set the pc increment. It should synthesize to a ROM. |
module m_pcinc(opcode,inc); |
input [7:0] opcode; |
output [3:0] inc; |
|
always @(opcode) |
if (em) |
else |
case(opcode) |
`BRK: inc <= 4'd1; |
`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA: inc <= 4'd2; |
`BRL: inc <= 4'd3; |
`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1; |
`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1; |
`TRS,`TSR: inc <= 4'd2; |
`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1; |
`EMM: inc <= 4'd1; |
`PHA,`PHX,`PHY,`PHP: inc <= 4'd1; |
`PLA,`PLX,`PLY,`PLP: inc <= 4'd1; |
`PUSH,`POP: inc <= 4'd2; |
`STP,`WAI: inc <= 4'd1; |
`JMP,`JSR: inc <= 4'd3; |
`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5; |
`JMP_RIND,`JSR_RIND: inc <= 4'd2; |
`RTS,`RTI,`RTL: inc <= 4'd1; |
`NOP: inc <= 4'd1; |
`BSR: inc <= 4'd3; |
`RR: inc <= 4'd3; |
`LD_RR: inc <= 4'd2; |
`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8: inc <= 4'd2; |
`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd3; |
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd5; |
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4; |
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4; |
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4; |
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6; |
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7; |
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd2; |
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3; |
endcase |
endmodule*/ |
|
|
|
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o); |
parameter IDLE = 3'd0; |
parameter LOAD_DCACHE = 3'd1; |
666,7 → 713,6
parameter JSR_INDX1 = 7'd14; |
parameter JSR161 = 7'd15; |
parameter RTS1 = 7'd16; |
parameter RTS2 = 7'd17; |
parameter IX1 = 7'd18; |
parameter IX2 = 7'd19; |
parameter IX3 = 7'd20; |
674,25 → 720,9
parameter IY1 = 7'd22; |
parameter IY2 = 7'd23; |
parameter IY3 = 7'd24; |
parameter PHP1 = 7'd27; |
parameter PLP1 = 7'd28; |
parameter PLP2 = 7'd29; |
parameter PLA1 = 7'd30; |
parameter PLA2 = 7'd31; |
parameter BSR1 = 7'd32; |
parameter BYTE_IX1 = 7'd33; |
parameter BYTE_IX2 = 7'd34; |
parameter BYTE_IX3 = 7'd35; |
parameter BYTE_IX4 = 7'd36; |
parameter BYTE_IX5 = 7'd37; |
parameter BYTE_IY1 = 7'd38; |
parameter BYTE_IY2 = 7'd39; |
parameter BYTE_IY3 = 7'd40; |
parameter BYTE_IY4 = 7'd41; |
parameter BYTE_IY5 = 7'd42; |
parameter RTS3 = 7'd43; |
parameter RTS4 = 7'd44; |
parameter RTS5 = 7'd45; |
parameter BYTE_JSR1 = 7'd46; |
parameter BYTE_JSR2 = 7'd47; |
parameter BYTE_JSR3 = 7'd48; |
788,10 → 818,12
wire [63:0] insn; |
reg [63:0] ibuf; |
reg [31:0] bufadr; |
reg [63:0] exbuf; |
|
reg cf,nf,zf,vf,bf,im,df,em; |
reg em1; |
reg gie; |
reg hwi; // hardware interrupt indicator |
reg nmoi; // native mode on interrupt |
wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf}; |
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf}; |
813,13 → 845,17
wire [7:0] sp_inc = sp + 8'd1; |
wire [31:0] isp_dec = isp - 32'd1; |
wire [31:0] isp_inc = isp + 32'd1; |
reg [3:0] suppress_pcinc; |
reg [31:0] pc; |
reg [31:0] opc; |
wire [31:0] pcp1 = pc + 32'd1; |
wire [31:0] pcp2 = pc + 32'd2; |
wire [31:0] pcp3 = pc + 32'd3; |
wire [31:0] pcp4 = pc + 32'd4; |
wire [31:0] pcp8 = pc + 32'd8; |
wire [31:0] pcp1 = pc + (32'd1 & suppress_pcinc); |
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); |
wire [31:0] pcp3 = pc + (32'd3 & suppress_pcinc); |
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); |
wire [31:0] pcp5 = pc + (32'd5 & suppress_pcinc); |
wire [31:0] pcp6 = pc + (32'd6 & suppress_pcinc); |
wire [31:0] pcp7 = pc + (32'd7 & suppress_pcinc); |
wire [31:0] pcp8 = pc + (32'd8 & suppress_pcinc); |
reg [31:0] dp; // 32 bit mode direct page register |
reg [31:0] dp8; // 8 bit mode direct page register |
reg [31:0] abs8; // 8 bit mode absolute address register |
925,6 → 961,8
wire isRTL = ir[7:0]==`RTL; |
wire isRTS = ir[7:0]==`RTS; |
wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN; |
wire isExec = ir[7:0]==`EXEC; |
wire isAtni = ir[7:0]==`ATNI; |
wire ld_muldiv = state==DECODE && ir[7:0]==`RR; |
wire md_done; |
wire clk; |
1048,11 → 1086,11
default: takb <= 1'b0; |
endcase |
|
wire [31:0] zpx_address = dp8 + ir[15:8] + x8; |
wire [31:0] zpy_address = dp8 + ir[15:8] + y8; |
wire [31:0] zp_address = dp8 + ir[15:8]; |
wire [31:0] zpx_address = zp_address + x8; |
wire [31:0] zpy_address = zp_address + y8; |
wire [31:0] abs_address = abs8 + {16'h0,ir[23:8]}; |
wire [31:0] absx_address = abs8 + {16'h0,ir[23:8] + {8'h0,x8}}; |
wire [31:0] absx_address = abs8 + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around |
wire [31:0] absy_address = abs8 + {16'h0,ir[23:8] + {8'h0,y8}}; |
wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa; |
wire [31:0] absx32xy_address = ir[47:16] + rfob; |
1117,6 → 1155,8
em <= 1'b0; |
pc <= 32'hFFFFFFF0; |
end |
suppress_pcinc <= 4'hF; |
exbuf <= 64'd0; |
spage <= 32'h00000100; |
bufadr <= 32'd0; |
dp <= 32'd0; |
1233,7 → 1273,6
end |
end |
|
`include "php.v" |
`include "byte_irq.v" |
|
IRQ1: |
1287,7 → 1326,7
state <= WAIT_DHIT; |
end |
radr <= vect[31:2]; |
if (!bf) |
if (hwi) |
im <= 1'b1; |
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode |
end |
1323,6 → 1362,7
adr_o <= {isp_dec,2'b00}; |
dat_o <= opc; |
vect <= {vbr[31:9],9'd508,2'b00}; |
hwi <= `TRUE; |
state <= IRQ1; |
end |
INSN_BUS_ERROR: |
1337,9 → 1377,10
adr_o <= {isp_dec,2'b00}; |
dat_o <= opc; |
vect <= {vbr[31:9],9'd509,2'b00}; |
hwi <= `TRUE; |
state <= IRQ1; |
end |
|
/* |
MVN1: |
begin |
radr <= x; |
1350,6 → 1391,7
end |
MVN2: |
begin |
radr <= y; |
wadr <= y; |
wdat <= b; |
y <= y + 32'd1; |
1372,6 → 1414,7
end |
MVP2: |
begin |
radr <= y; |
wadr <= y; |
wdat <= b; |
y <= y - 32'd1; |
1378,7 → 1421,7
acc <= acc - 32'd1; |
state <= STORE1; |
end |
|
*/ |
endcase |
|
`include "cache_controller.v" |
/rtf65002/trunk/rtl/verilog/store.v
29,7 → 29,7
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
if (em || isStb) |
if (em || isStb) begin |
case(wadr2LSB) |
2'd0: sel_o <= 4'b0001; |
2'd1: sel_o <= 4'b0010; |
36,6 → 36,7
2'd2: sel_o <= 4'b0100; |
2'd3: sel_o <= 4'b1000; |
endcase |
end |
else |
sel_o <= 4'hf; |
adr_o <= {wadr,2'b00}; |
/rtf65002/trunk/rtl/verilog/ifetch.v
22,11 → 22,14
// |
IFETCH: |
begin |
suppress_pcinc <= 4'hF; // default: no suppression of increment |
opc <= pc; |
if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop |
hwi <= `FALSE; |
if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop |
nmi_edge <= 1'b0; |
wai <= 1'b0; |
bf <= 1'b0; |
hwi <= `TRUE; |
if (em & !nmoi) begin |
radr <= {spage[31:8],sp[7:2]}; |
radr2LSB <= sp[1:0]; |
62,12 → 65,19
state <= IRQ1; |
end |
end |
else if (irq_i && !imiss & gie) begin |
else if (irq_i && !imiss & gie & !isExec & !isAtni) begin |
if (im) begin |
wai <= 1'b0; |
if (unCachedInsn) begin |
if (isExec) begin |
ir <= exbuf; |
exbuf <= 64'd0; |
suppress_pcinc <= 4'h0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else if (unCachedInsn) begin |
if (bhit) begin |
ir <= ibuf; |
ir <= ibuf + exbuf; |
exbuf <= 64'd0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else |
75,7 → 85,8
end |
else begin |
if (ihit) begin |
ir <= insn; |
ir <= insn + exbuf; |
exbuf <= 64'd0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else |
85,6 → 96,7
else begin |
bf <= 1'b0; |
wai <= 1'b0; |
hwi <= `TRUE; |
if (em & !nmoi) begin |
radr <= {spage[31:8],sp[7:2]}; |
radr2LSB <= sp[1:0]; |
122,9 → 134,16
end |
end |
else if (!wai) begin |
if (unCachedInsn) begin |
if (isExec) begin |
ir <= exbuf; |
exbuf <= 64'd0; |
suppress_pcinc <= 4'h0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else if (unCachedInsn) begin |
if (bhit) begin |
ir <= ibuf; |
ir <= ibuf + exbuf; |
exbuf <= 64'd0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else |
132,7 → 151,8
end |
else begin |
if (ihit) begin |
ir <= insn; |
ir <= insn + exbuf; |
exbuf <= 64'd0; |
state <= em ? BYTE_DECODE : DECODE; |
end |
else |
221,7 → 241,8
case(ir[7:0]) |
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end |
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end |
`TAS,`TXS,`SUB_SP: begin isp <= res; gie <= 1'b1; end |
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end |
`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res; |
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end |
`TRS: |
begin |
/rtf65002/trunk/rtl/verilog/byte_decode.v
344,7 → 344,7
radr2LSB <= sp[1:0]; |
wadr <= {spage[31:8],sp[7:2]}; |
wadr2LSB <= sp[1:0]; |
wdat <= {4{pcp1[31:24]}}; |
wdat <= {4{pcp2[31:24]}}; |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
355,7 → 355,7
2'd3: sel_o <= 4'b1000; |
endcase |
adr_o <= {spage[31:8],sp[7:2],2'b00}; |
dat_o <= {4{pcp1[31:24]}}; |
dat_o <= {4{pcp2[31:24]}}; |
sp <= sp_dec; |
vect <= `BYTE_IRQ_VECT; |
state <= BYTE_IRQ1; |
516,7 → 516,8
dat_o <= {4{sr8}}; |
wdat <= {4{sr8}}; |
sp <= sp_dec; |
state <= PHP1; |
state <= STORE2; |
pc <= pc + 32'd1; |
end |
`PHA: |
begin |
537,7 → 538,8
dat_o <= {4{acc8}}; |
wdat <= {4{acc8}}; |
sp <= sp_dec; |
state <= PHP1; |
state <= STORE2; |
pc <= pc + 32'd1; |
end |
`PHX: |
begin |
558,7 → 560,8
dat_o <= {4{x8}}; |
wdat <= {4{x8}}; |
sp <= sp_dec; |
state <= PHP1; |
state <= STORE2; |
pc <= pc + 32'd1; |
end |
`PHY: |
begin |
579,7 → 582,8
dat_o <= {4{y8}}; |
wdat <= {4{y8}}; |
sp <= sp_dec; |
state <= PHP1; |
pc <= pc + 32'd1; |
state <= STORE2; |
end |
`PLP: |
begin |