OpenCores
URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 24 to Rev 25
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  •

Rev 24 → Rev 25

/trunk/bench/verilog/tb_spi_top.v
67,6 → 67,7
reg [31:0] q1;
reg [31:0] q2;
reg [31:0] q3;
reg [31:0] result;
 
parameter SPI_RX_0 = 5'h0;
parameter SPI_RX_1 = 5'h4;
118,6 → 119,8
i_spi_slave.rx_negedge = 1'b0;
i_spi_slave.tx_negedge = 1'b0;
 
result = 32'h0;
 
// Reset system
rst = 1'b0; // negate reset
#2;
132,7 → 135,7
// Program core
i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register
i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a
i_wb_master.wb_write(0, SPI_CTRL, 32'h42); // set 8 bit transfer
i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer
i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0
 
$display("status: %t programmed registers", $time);
139,7 → 142,7
 
i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register
i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register
i_wb_master.wb_cmp(0, SPI_CTRL, 32'h42); // verify tx register
i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register
i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register
 
$display("status: %t verified registers", $time);
147,16 → 150,17
i_spi_slave.rx_negedge = 1'b1;
i_spi_slave.tx_negedge = 1'b0;
i_spi_slave.data[31:0] = 32'ha5967e5a;
i_wb_master.wb_write(0, SPI_CTRL, 32'h43); // set 8 bit transfer, start transfer
i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer
 
$display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time);
 
// Check bsy bit
i_wb_master.wb_read(0, SPI_CTRL, q);
while (q[0])
while (q[8])
i_wb_master.wb_read(1, SPI_CTRL, q);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
 
if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)
$display("status: %t transfer completed: ok", $time);
166,17 → 170,18
i_spi_slave.rx_negedge = 1'b0;
i_spi_slave.tx_negedge = 1'b1;
i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);
i_wb_master.wb_write(0, SPI_CTRL, 32'h44); // set 8 bit transfer, tx negedge
i_wb_master.wb_write(0, SPI_CTRL, 32'h45); // set 8 bit transfer, tx negedge, start transfer
i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge
i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer
 
$display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time);
 
// Check bsy bit
i_wb_master.wb_read(0, SPI_CTRL, q);
while (q[0])
while (q[8])
i_wb_master.wb_read(1, SPI_CTRL, q);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
 
if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)
$display("status: %t transfer completed: ok", $time);
186,17 → 191,18
i_spi_slave.rx_negedge = 1'b0;
i_spi_slave.tx_negedge = 1'b1;
i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);
i_wb_master.wb_write(0, SPI_CTRL, 32'h484); // set 16 bit transfer, tx negedge, lsb
i_wb_master.wb_write(0, SPI_CTRL, 32'h485); // set 16 bit transfer, tx negedge, start transfer
i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb
i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer
 
$display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);
 
// Check bsy bit
i_wb_master.wb_read(0, SPI_CTRL, q);
while (q[0])
while (q[8])
i_wb_master.wb_read(1, SPI_CTRL, q);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
 
if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)
$display("status: %t transfer completed: ok", $time);
207,18 → 213,20
i_spi_slave.tx_negedge = 1'b0;
i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);
i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);
i_wb_master.wb_write(0, SPI_CTRL, 32'h602); // set 64 bit transfer, rx negedge, lsb
i_wb_master.wb_write(0, SPI_CTRL, 32'h603); // set 64 bit transfer, rx negedge, start transfer
i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb
i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer
 
$display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);
 
// Check bsy bit
i_wb_master.wb_read(0, SPI_CTRL, q);
while (q[0])
while (q[8])
i_wb_master.wb_read(1, SPI_CTRL, q);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
i_wb_master.wb_read(1, SPI_RX_1, q1);
result = result + q1;
 
if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)
$display("status: %t transfer completed: ok", $time);
231,20 → 239,24
i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);
i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);
i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);
i_wb_master.wb_write(0, SPI_CTRL, 32'h04);
i_wb_master.wb_write(0, SPI_CTRL, 32'h05);
i_wb_master.wb_write(0, SPI_CTRL, 32'h400);
i_wb_master.wb_write(0, SPI_CTRL, 32'h500);
 
$display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);
 
// Check bsy bit
i_wb_master.wb_read(0, SPI_CTRL, q);
while (q[0])
while (q[8])
i_wb_master.wb_read(1, SPI_CTRL, q);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
i_wb_master.wb_read(1, SPI_RX_1, q1);
result = result + q1;
i_wb_master.wb_read(1, SPI_RX_2, q2);
result = result + q2;
i_wb_master.wb_read(1, SPI_RX_3, q3);
result = result + q3;
 
if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)
$display("status: %t transfer completed: ok", $time);
254,8 → 266,8
i_spi_slave.rx_negedge = 1'b0;
i_spi_slave.tx_negedge = 1'b1;
i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);
i_wb_master.wb_write(0, SPI_CTRL, 32'h904);
i_wb_master.wb_write(0, SPI_CTRL, 32'h905);
i_wb_master.wb_write(0, SPI_CTRL, 32'h1420);
i_wb_master.wb_write(0, SPI_CTRL, 32'h1520);
 
$display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);
 
264,6 → 276,7
@(posedge clk);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
@(posedge clk);
if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)
274,8 → 287,8
i_spi_slave.rx_negedge = 1'b1;
i_spi_slave.tx_negedge = 1'b0;
i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);
i_wb_master.wb_write(0, SPI_CTRL, 32'h1902);
i_wb_master.wb_write(0, SPI_CTRL, 32'h1903);
i_wb_master.wb_write(0, SPI_CTRL, 32'h3220);
i_wb_master.wb_write(0, SPI_CTRL, 32'h3320);
 
$display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
283,6 → 296,7
@(posedge clk);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
 
@(posedge clk);
if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)
293,8 → 307,8
i_spi_slave.rx_negedge = 1'b1;
i_spi_slave.tx_negedge = 1'b0;
i_wb_master.wb_write(0, SPI_TX_0, 32'h1);
i_wb_master.wb_write(0, SPI_CTRL, 32'h180a);
i_wb_master.wb_write(0, SPI_CTRL, 32'h180b);
i_wb_master.wb_write(0, SPI_CTRL, 32'h3201);
i_wb_master.wb_write(0, SPI_CTRL, 32'h3301);
 
$display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
302,6 → 316,7
@(posedge clk);
 
i_wb_master.wb_read(1, SPI_RX_0, q);
result = result + q;
 
@(posedge clk);
if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)
313,6 → 328,9
 
#25000; // wait 25us
 
$display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead);
$display("exit (%h)", result ^ 32'h2e8b36ab);
 
$stop;
end
 
/trunk/rtl/verilog/spi_defines.v
143,16 → 143,17
//
// Number of bits in ctrl register
//
`define SPI_CTRL_BIT_NB 13
`define SPI_CTRL_BIT_NB 14
 
//
// Control register bit position
//
`define SPI_CTRL_ASS 12
`define SPI_CTRL_IE 11
`define SPI_CTRL_LSB 10
`define SPI_CTRL_CHAR_LEN 9:3
`define SPI_CTRL_TX_NEGEDGE 2
`define SPI_CTRL_RX_NEGEDGE 1
`define SPI_CTRL_GO 0
`define SPI_CTRL_ASS 13
`define SPI_CTRL_IE 12
`define SPI_CTRL_LSB 11
`define SPI_CTRL_TX_NEGEDGE 10
`define SPI_CTRL_RX_NEGEDGE 9
`define SPI_CTRL_GO 8
`define SPI_CTRL_RES_1 7
`define SPI_CTRL_CHAR_LEN 6:0
 
/trunk/doc/spi.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/spi.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/sim/run/tcl.scr File deleted
/trunk/sim/run/sim File deleted
trunk/sim/run/sim Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/rtl_sim/run/rtl.fl =================================================================== --- trunk/sim/rtl_sim/run/rtl.fl (nonexistent) +++ trunk/sim/rtl_sim/run/rtl.fl (revision 25) @@ -0,0 +1,3 @@ +spi_top.v +spi_clgen.v +spi_shift.v Index: trunk/sim/rtl_sim/run/sim.fl =================================================================== --- trunk/sim/rtl_sim/run/sim.fl (nonexistent) +++ trunk/sim/rtl_sim/run/sim.fl (revision 25) @@ -0,0 +1,3 @@ +tb_spi_top.v +wb_master_model.v +spi_slave_model.v Index: trunk/sim/rtl_sim/run/run_sim =================================================================== --- trunk/sim/rtl_sim/run/run_sim (nonexistent) +++ trunk/sim/rtl_sim/run/run_sim (revision 25) @@ -0,0 +1,108 @@ +#!/bin/csh -f + +set current_par = 0 +set output_waveform = 0 +while ( $current_par < $# ) + @ current_par = $current_par + 1 + case wave: + @ output_waveform = 1 + breaksw + default: + echo 'Unknown option "'$argv[$current_par]'"!' + exit + breaksw + endsw +end + +echo "TEST: spi" + +#echo "-CDSLIB ./cds.lib" > ncvlog.args +#echo "-HDLVAR ./hdl.var" >> ncvlog.args +echo "-MESSAGES" > ncvlog.args +echo "-INCDIR ../../../bench/verilog" >> ncvlog.args +echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args +echo "-NOCOPYRIGHT" >> ncvlog.args +echo "-UPDATE" >> ncvlog.args +echo "-LOGFILE ncvlog.log" >> ncvlog.args + +foreach filename ( `cat ./rtl.fl` ) + echo "../../../rtl/verilog/"$filename >> ncvlog.args +end + +foreach filename ( `cat ./sim.fl` ) + echo "../../../bench/verilog/"$filename >> ncvlog.args +end + +ncvlog -f ncvlog.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncelab.args +echo "-NOCOPYRIGHT" >> ncelab.args +#echo "-CDSLIB ./cds.lib" >> ncelab.args +#echo "-HDLVAR ./hdl.var" >> ncelab.args +echo "-LOGFILE ncelab.log" >> ncelab.args +echo "-SNAPSHOT worklib.tb_spi_top:v" >> ncelab.args +echo "-NOTIMINGCHECKS" >> ncelab.args +echo "-ACCESS +RWC" >> ncelab.args +echo "tb_spi_top" >> ncelab.args + +ncelab -f ncelab.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncsim.args +echo "-NOCOPYRIGHT" >> ncsim.args +#echo "-CDSLIB ./cds.lib" >> ncsim.args +#echo "-HDLVAR ./hdl.var" >> ncsim.args +echo "-INPUT ncsim.tcl" >> ncsim.args +echo "-LOGFILE ncsim.log" >> ncsim.args +echo "worklib.tb_spi_top:v" >> ncsim.args + +if ( $output_waveform ) then + echo "database -open waves -shm -into ../out/wav" > ./ncsim.tcl + echo "probe -create -database waves -shm tb_spi_top -all -depth all" >> ./ncsim.tcl + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" >> ./ncsim.tcl +else + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" > ./ncsim.tcl +endif + +echo "exit" >> ncsim.tcl + +ncsim -LICQUEUE -f ./ncsim.args + +set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log` + +set dead_line_nb = 0 + +if ( $exit_line_nb ) then + + @ dead_line_nb = $exit_line_nb - 1 + set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log` + set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log` + + if ( "$dead_line" == "report (deaddead)" ) then + if ( "$exit_line" == "exit (00000000)" ) then + echo "STATUS: passed" #|tee -a ./run_sim.log 2>&1 + else + echo "STATUS: failed" #|tee -a ./run_sim.log 2>&1 + endif + else + echo "STATUS: failed" + endif + +endif + +exit + + + +
trunk/sim/rtl_sim/run/run_sim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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