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Rev 24 → Rev 25

/trunk/rtl/vhdl/T80_MCode.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0235
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
52,6 → 52,8
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
 
library IEEE;
use IEEE.std_logic_1164.all;
116,6 → 118,7
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end T80_MCode;
202,6 → 205,7
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
 
case ISet is
708,6 → 712,7
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
722,6 → 727,7
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "1001";
794,6 → 800,7
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
808,6 → 815,7
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
822,6 → 830,7
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
836,6 → 845,7
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
850,6 → 860,7
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
872,6 → 883,7
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
1318,6 → 1330,7
MCycles <= "100";
end if;
when 4 =>
NoRead <= '1';
I_BTR <= '1';
TStates <= "101";
MCycles <= "100";
1342,6 → 1355,7
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
if IR(4) = '1' and F(2) = '1' and F(6) = '0' then
1348,6 → 1362,7
MCycles <= "100";
end if;
when 4 =>
NoRead <= '1';
I_BTR <= '1';
TStates <= "101";
MCycles <= "100";
1375,6 → 1390,7
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "1001";
Read_To_Reg <= '1';
Save_ALU <= '1';
1387,6 → 1403,7
Set_BusB_To <= "1000";
end case;
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "1001";
1406,6 → 1423,7
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
1418,6 → 1436,7
Set_BusB_To <= "1000";
end case;
when 3 =>
NoRead <= '1';
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
1436,6 → 1455,7
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
1544,6 → 1564,7
MCycles <= "100";
end if;
when 4 =>
NoRead <= '1';
I_BTR <= '1';
TStates <= "101";
MCycles <= "100";
1577,6 → 1598,7
MCycles <= "100";
end if;
when 4 =>
NoRead <= '1';
I_BTR <= '1';
TStates <= "101";
MCycles <= "100";
/trunk/rtl/vhdl/T80se.vhd
3,7 → 3,7
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0237
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
52,6 → 52,8
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
89,6 → 91,7
 
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
104,6 → 107,7
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
147,7 → 151,7
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '0' then
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
/trunk/rtl/vhdl/T80_Pack.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0237
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
64,6 → 64,7
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
140,6 → 141,7
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
147,6 → 149,7
component T80_ALU
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
Rot_Op : in std_logic;
Bit_Op : in std_logic_vector(1 downto 0);
/trunk/rtl/vhdl/T80.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0237
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
61,6 → 61,8
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
 
library IEEE;
use IEEE.std_logic_1164.all;
81,6 → 83,7
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
134,7 → 137,7
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal XY_Fetch : std_logic;
signal XY_Fetch : std_logic_vector(1 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
 
148,6 → 151,7
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal AALU_OP_r : std_logic_vector(2 downto 0);
signal Rot_Op_r : std_logic;
265,11 → 269,13
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
 
alu : T80_ALU
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
Rot_Op => Rot_Op_r,
Bit_Op => Bit_Op_r,
282,8 → 288,9
F_Out => F_Out,
F_Save => F_Save);
 
T_Res <= '1' when (TState = unsigned(TStates) and XY_Fetch = '0') or
(XY_Fetch = '1' and TState = 4) else '0'; -- Incorrect, should be 8 !!!!!!!!!!!!!!!!
T_Res <= '1' when (TState = unsigned(TStates) and XY_Fetch(0) = '0') or
(XY_Fetch(0) = '1' and TState = "111" and Mode = 0) or
(XY_Fetch(0) = '1' and TState = "100" and Mode = 1) else '0';
 
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and ((Set_Addr_To = aXY and IR /= "11001011") or
(MCycle = "001" and IR = "11001011") or
311,6 → 318,7
 
Read_To_Reg_r <= "00000";
Arith16_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Rot_Op_r <= '0';
Bit_Op_r <= "00";
323,12 → 331,10
 
if CEN = '1' then
 
Arith16_r <= '0';
ALU_Op_r <= "0000";
Rot_Op_r <= '0';
Bit_Op_r <= "00";
Save_ALU_r <= '0';
PreserveC_r <= '0';
AALU_OP_r <= "000";
Read_To_Reg_r <= "00000";
 
338,7 → 344,15
IStatus <= IMode;
end if;
 
if MCycle = "001" and TState(2) = '0' and XY_Fetch = '0' then
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
 
if MCycle = "001" and TState(2) = '0' and XY_Fetch(0) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
 
if TState = 2 and Wait_n = '1' then
384,7 → 398,7
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
 
if XY_Fetch = '1' then
if XY_Fetch(0) = '1' then
XY_Ind <= '1';
end if;
 
460,12 → 474,10
end case;
end if;
 
Arith16_r <= Arith16;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
Rot_Op_r <= Rot_Op;
Bit_Op_r <= Bit_Op;
Save_ALU_r <= Save_ALU;
PreserveC_r <= PreserveC;
if Save_ALU = '1' then
if Rot_Op = '0' and Bit_Op = "00" then
if ALU_Op(3) = '1' then
505,7 → 517,7
if TState = 2 and Wait_n = '1' then
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' or XY_Fetch = '1' then
elsif Inc_PC = '1' or XY_Fetch(0) = '1' then
PC <= PC + 1;
end if;
if I_BTR = '1' then
516,7 → 528,7
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and XY_Fetch = '1' then
if TState = 3 and XY_Fetch = "01" then
if XY_State = "01" then
TmpAddr <= std_logic_vector(signed(IX) + signed(DI_Reg));
end if;
917,7 → 929,7
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
False_M1 <= XY_Fetch;
False_M1 <= XY_Fetch(0);
IntCycle_n <= not IntCycle;
 
process (RESET_n,CLK_n)
976,7 → 988,7
BUSAK_n <= '1';
NMICycle <= '0';
IntCycle <= '0';
XY_Fetch <= '0';
XY_Fetch <= "00";
IntE_FF1 <= '0';
IntE_FF2 <= '0';
elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
1006,6 → 1018,9
end if;
else
if TState = 2 and Wait_n = '0' then
elsif XY_Fetch = "01" and TState = "100" and Mode = 0 then
XY_Fetch <= "11";
TState <= "011";
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
1015,9 → 1030,9
BUSAK_n <= '0';
else
TState <= "001";
XY_Fetch <= '0';
XY_Fetch <= "00";
if NextIs_XY_Fetch = '1' then
XY_Fetch <= '1';
XY_Fetch <= "01";
elsif MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000") then
MCycle <= "001";
IntCycle <= '0';
/trunk/rtl/vhdl/T8080se.vhd
3,7 → 3,7
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0237
-- Version : 0238
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
47,6 → 47,10
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
81,6 → 85,7
 
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
118,6 → 123,7
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
153,7 → 159,7
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '0' then
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
/trunk/rtl/vhdl/T80_ALU.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0214
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
--
46,6 → 46,8
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
 
library IEEE;
use IEEE.std_logic_1164.all;
54,6 → 56,7
entity T80_ALU is
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
Rot_Op : in std_logic;
Bit_Op : in std_logic_vector(1 downto 0);
246,7 → 249,7
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if ISet = "10" and AALU_OP(2) = '0' and AALU_OP(0) = '1' then
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
/trunk/rtl/vhdl/T80a.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0235
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
50,6 → 50,8
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
87,6 → 89,7
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
119,6 → 122,7
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
215,7 → 219,7
MREQ <= '0';
end if;
else
if TState = "001" then
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n <= not IORQ;
MREQ <= not IORQ;
/trunk/rtl/vhdl/T80s.vhd
3,7 → 3,7
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0237
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
58,6 → 58,8
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
95,6 → 97,7
signal CEN : std_logic;
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
112,6 → 115,7
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
154,7 → 158,7
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '0' then
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;

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