URL
https://opencores.org/ocsvn/zet86/zet86/trunk
Subversion Repositories zet86
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- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/trunk/rtl-model/alu.v
147,7 → 147,7
assign ofo = word_op ? ofo16 : ofo8; |
endmodule |
|
/* |
|
module adj(x, y, out, func, afi, cfi, afo, cfo); |
// IO ports |
input [15:0] x, y; |
157,19 → 157,26
output [16:0] out; |
|
// Net declarations |
wire [16:0] aaa, aad, aam, aas, daa, das, aad16; |
wire [15:0] aaa, aad, aam, aas, daa, das, aad16; |
wire [7:0] ala, als, alout; |
wire alcnd; |
wire [4:0] q; |
wire [3:0] r; |
|
// Module instances |
mux8_17 m0(func, aaa, aad, aam, aas, |
daa, das, {9'd0, y[7:0]}, {1'b0, y}, out); |
div10b8 div10 ( |
.a (x[7:0]), |
.q (q), |
.r (r) |
); |
|
// Assignments |
assign aaa = afo ? { x[15:8] + 8'd1, (x[7:0] + 8'd6) & 8'h0f } : x; |
assign aad16 = x[15:8] * 8'd10 + x[7:0]; |
assign aad16 = (x[15:8] << 3) + (x[15:8] << 1) + x[7:0]; |
assign aad = { 8'b0, aad16[7:0] }; |
assign aam = 17'h0; //{ x[7:0] / 8'd10, x[7:0] % 8'd10 }; |
assign aam = { 3'b0, q, 4'b0, r }; |
assign aas = afo ? { x[15:8] - 8'd1, (x[7:0] - 8'd6) & 8'h0f } : x; |
|
assign ala = afo ? x[7:0] + 8'd6 : x[7:0]; |
201,7 → 208,7
assign cwd = { x15_16, x[7:0] }; |
assign out = func ? cwd : cbw; |
endmodule |
|
/* |
module muldiv(x, y, out, func, word_op, cfo, ofo); |
// IO ports |
input [31:0] x; |
/trunk/rtl-model/util/primitives.v
184,4 → 184,72
2'd2: out = in2; |
2'd3: out = in3; |
endcase |
endmodule |
endmodule |
|
// |
// 1 bit cell divider by 10 |
// |
module div10b1 ( |
input [3:0] c, |
input a, |
output q, |
output [3:0] r |
); |
|
// Continuous assignments |
assign r = { c[3]&c[0] | c[2]&~c[1]&~c[0], |
~c[2]&c[1] | c[1]&c[0] | c[3]&~c[0], |
c[3]&~c[0] | c[2]&c[1]&~c[0] | ~c[3]&~c[2]&~c[0], |
a }; |
assign q = c[3] | c[2]&c[1] | c[2]&c[0]; |
endmodule |
|
// |
// 8 bit divider by 10 |
// |
module div10b8 ( |
input [7:0] a, |
output [4:0] q, |
output [3:0] r |
); |
|
// Net declarations |
wire [3:0] c10, c21, c32, c43; |
|
// Module instantiations |
div10b1 bit4 ( |
.c ({1'b0, a[7:5]}), |
.a (a[4]), |
.q (q[4]), |
.r (c43) |
); |
|
div10b1 bit3 ( |
.c (c43), |
.a (a[3]), |
.q (q[3]), |
.r (c32) |
); |
|
div10b1 bit2 ( |
.c (c32), |
.a (a[2]), |
.q (q[2]), |
.r (c21) |
); |
|
div10b1 bit1 ( |
.c (c21), |
.a (a[1]), |
.q (q[1]), |
.r (c10) |
); |
|
div10b1 bit0 ( |
.c (c10), |
.a (a[0]), |
.q (q[0]), |
.r (r) |
); |
|
endmodule |