OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 241 to Rev 242
    ↔ Reverse comparison
  •

Rev 241 → Rev 242

/open8_urisc/trunk/VHDL/o8_ram_1k.vhd
1,96 → 1,204
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ram_1k is
generic(
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
 
architecture behave of o8_ram_1k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 10)
:= Address(15 downto 10);
alias Comp_Addr is Open8_Bus.Address(15 downto 10);
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_1k_core
port map(
address => RAM_Addr,
clock => Clock,
data => Open8_Bus.Wr_Data,
wren => Wr_En,
q => Rd_Data_i
);
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
end if;
end if;
end process;
 
end architecture;
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model with interface
-- : logic for the Open8 CPU. Also provides an optional write
-- : enable register that prevents regions from being written
-- : by non-ISR code (uses the I flag) as a way to prevent tasks
-- : from inadvertently writing outside of their designated
-- : memory space.
-- : When enabled, the write mask logically divides the memory into
-- : 16, 64 byte regions, corresponding to the 16 bits in the WPR
-- : register.
--
-- WP Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/12/20 Added write protect logic
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ram_1k is
generic(
Write_Protect : boolean := FALSE;
Default_Mask : ADDRESS_TYPE := x"0000";
Address_WPR : ADDRESS_TYPE := x"0400";
Address_RAM : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
 
architecture behave of o8_ram_1k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
alias Wr_En is Open8_Bus.Wr_En;
alias Rd_En is Open8_Bus.Rd_En;
 
constant WPR_User_Addr : std_logic_vector(15 downto 1)
:= Address_WPR(15 downto 1);
 
constant RAM_User_Addr : std_logic_vector(15 downto 10)
:= Address_RAM(15 downto 10);
 
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
signal WPR_Reg_Sel : std_logic := '0';
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data : DATA_TYPE := x"00";
 
signal Write_Mask : std_logic_vector(15 downto 0) :=
x"0000";
alias Write_Mask_0 is Write_Mask(7 downto 0);
alias Write_Mask_1 is Write_Mask(15 downto 8);
 
signal WPR_Wr_En : std_logic := '0';
signal WPR_Rd_En : std_logic := '0';
 
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
 
alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
 
signal RAM_Region_Match : std_logic := '0';
signal RAM_Addr_Match : std_logic := '0';
 
signal RAM_Wr_En : std_logic := '0';
signal RAM_Rd_En : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
Write_Protect_On : if( Write_Protect )generate
 
WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
ISR_En;
 
RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Write_Mask <= Default_Mask;
 
WPR_Reg_Sel <= '0';
 
WPR_Wr_En <= '0';
WPR_Rd_En <= '0';
 
RAM_Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
WPR_Reg_Sel <= WPR_Reg_Sel_d;
 
WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
Wr_Data <= Wr_Data_d;
if( WPR_Wr_En = '1' )then
case( WPR_Reg_Sel )is
when '0' =>
Write_Mask_0 <= Wr_Data;
when '1' =>
Write_Mask_1 <= Wr_Data;
when others =>
null;
end case;
end if;
 
WPR_Rd_En <= WPR_Addr_Match and Rd_En;
RAM_Rd_En <= RAM_Addr_Match and Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( WPR_Rd_En = '1' )then
case( WPR_Reg_Sel )is
when '0' =>
Rd_Data <= Write_Mask_0;
when '1' =>
Rd_Data <= Write_Mask_1;
when others =>
null;
end case;
end if;
if( RAM_Rd_En = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
end process;
 
end generate;
 
Write_Protect_Off : if( not Write_Protect )generate
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
RAM_Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
end process;
 
end generate;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_1k_core
port map(
address => RAM_Addr,
clock => Clock,
data => Wr_Data_d,
wren => RAM_Wr_En,
q => RAM_Rd_Data
);
 
end architecture;
/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
1,96 → 1,219
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ram_4k is
generic(
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
 
architecture behave of o8_ram_4k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 12)
:= Address(15 downto 12);
alias Comp_Addr is Open8_Bus.Address(15 downto 12);
alias RAM_Addr is Open8_Bus.Address(11 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_4k_core
port map(
address => RAM_Addr,
clock => Clock,
data => Open8_Bus.Wr_Data,
wren => Wr_En,
q => Rd_Data_i
);
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
end if;
end if;
end process;
 
end architecture;
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_ram_4k
-- Description: Provides a wrapper layer for a 4kx8 RAM model with interface
-- : logic for the Open8 CPU. Also provides an optional write
-- : enable register that prevents regions from being written
-- : by non-ISR code (uses the I flag) as a way to prevent tasks
-- : from inadvertently writing outside of their designated
-- : memory space.
-- : When enabled, the write mask logically divides the memory into
-- : 32, 128 byte regions, corresponding to the 32 bits in the WPR
-- : register.
--
-- WP Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/12/20 Added write protect logic
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ram_4k is
generic(
Write_Protect : boolean := FALSE;
Default_Mask : std_logic_vector(31 downto 0) := x"00000000";
Address_WPR : ADDRESS_TYPE := x"1000";
Address_RAM : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
 
architecture behave of o8_ram_4k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
alias Wr_En is Open8_Bus.Wr_En;
alias Rd_En is Open8_Bus.Rd_En;
 
constant WPR_User_Addr : std_logic_vector(15 downto 2)
:= Address_WPR(15 downto 2);
 
constant RAM_User_Addr : std_logic_vector(15 downto 12)
:= Address_RAM(15 downto 12);
 
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 2);
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal WPR_Reg_Sel : std_logic_vector(1 downto 0) :=
(others => '0');
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data : DATA_TYPE := x"00";
 
signal Write_Mask : std_logic_vector(31 downto 0) :=
x"00000000";
alias Write_Mask_0 is Write_Mask( 7 downto 0);
alias Write_Mask_1 is Write_Mask(15 downto 8);
alias Write_Mask_2 is Write_Mask(23 downto 16);
alias Write_Mask_3 is Write_Mask(31 downto 24);
 
signal WPR_Wr_En_d : std_logic := '0';
signal WPR_Wr_En : std_logic := '0';
signal WPR_Rd_En_d : std_logic := '0';
signal WPR_Rd_En : std_logic := '0';
 
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 12);
alias RAM_Addr is Open8_Bus.Address(11 downto 0);
 
alias RAM_Rgn_Addr is Open8_Bus.Address(11 downto 7);
 
signal RAM_Region_Match : std_logic := '0';
signal RAM_Addr_Match : std_logic := '0';
 
signal RAM_Wr_En : std_logic := '0';
signal RAM_Rd_En : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
Write_Protect_On : if( Write_Protect )generate
 
WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
ISR_En;
 
RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Write_Mask <= Default_Mask;
 
WPR_Reg_Sel <= (others => '0');
 
WPR_Wr_En <= '0';
WPR_Rd_En <= '0';
 
RAM_Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
WPR_Reg_Sel <= WPR_Reg_Sel_d;
 
WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
Wr_Data <= Wr_Data_d;
if( WPR_Wr_En = '1' )then
case( WPR_Reg_Sel )is
when "00" =>
Write_Mask_0 <= Wr_Data;
when "01" =>
Write_Mask_1 <= Wr_Data;
when "10" =>
Write_Mask_2 <= Wr_Data;
when "11" =>
Write_Mask_3 <= Wr_Data;
when others =>
null;
end case;
end if;
 
WPR_Rd_En <= WPR_Addr_Match and Rd_En;
RAM_Rd_En <= RAM_Addr_Match and Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( WPR_Rd_En = '1' )then
case( WPR_Reg_Sel )is
when "00" =>
Rd_Data <= Write_Mask_0;
when "01" =>
Rd_Data <= Write_Mask_1;
when "10" =>
Rd_Data <= Write_Mask_2;
when "11" =>
Rd_Data <= Write_Mask_3;
when others =>
null;
end case;
end if;
if( RAM_Rd_En = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
end process;
 
end generate;
 
Write_Protect_Off : if( not Write_Protect )generate
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
RAM_Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
end process;
 
end generate;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_4k_core
port map(
address => RAM_Addr,
clock => Clock,
data => Wr_Data_d,
wren => RAM_Wr_En,
q => RAM_Rd_Data
);
 
end architecture;
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
25,7 → 25,10
-- Description: Provides an 8-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU.
--
-- Notes : Setting the output to 0x00 will disable the timer
-- Notes : It is possible to set the value to zero, resulting in the
-- : output staying high indefinitely. This may cause an issue if
-- : the output is connected to an interrupt input.
-- : Also provides uSec_Tick as an output
--
-- Revision History
-- Author Date Change
47,6 → 50,7
 
entity o8_sys_timer is
generic(
Write_Protect : boolean := FALSE;
Address : ADDRESS_TYPE
);
port(
61,7 → 65,13
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
 
signal Wr_En_d : std_logic;
signal Rd_En_d : std_logic;
 
alias Wr_Data is Open8_Bus.Wr_Data;
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
78,6 → 88,19
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
-- If the Write_Protect generic is set only allow the memory to be written
-- if the ISR bit is set. Otherwise, the memory should be read-only
 
Write_Protect_On : if( Write_Protect )generate
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and ISR_En;
end generate;
 
Write_Protect_Off : if( not Write_Protect )generate
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
end generate;
 
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
88,16 → 111,16
Interval <= x"00";
Update_Interval <= '0';
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Update_Interval <= '0';
Wr_En <= Wr_En_d;
Wr_Data_q <= Wr_Data;
 
Update_Interval <= Wr_En;
if( Wr_En = '1' )then
Interval <= Wr_Data_q;
Update_Interval <= '1';
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= (others => '0');
Rd_En <= Rd_En_d;
if( Rd_En = '1' )then
Rd_Data <= Interval;
end if;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.