OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 243 to Rev 244
    ↔ Reverse comparison
  •

Rev 243 → Rev 244

/openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c
47,7 → 47,10
#include "or1ksim.h"
#include "or32sim.h"
 
/* Define this to turn on debug messages */
/* #define OR32_SIM_DEBUG */
 
 
/* ------------------------------------------------------------------------- */
/*!Create a fully initialized simulator instance.
 
110,6 → 113,10
/*!A global record of the simulator description */
static SIM_DESC static_sd = NULL;
 
#ifdef OR32_SIM_DEBUG
printf ("sim_open called\n");
#endif
 
/* If static_sd is not yet allocated, we allocate it and mark the simulator
as not yet open. This is the only time we can process any custom
arguments and only time we initialize the simulator. */
131,8 → 138,9
config file or a memory size. */
for (argc = 1; NULL != argv[argc]; argc++)
{
/* printf ("argv[%d] = %s\n", argc, argv[argc]); */
 
#ifdef OR32_SIM_DEBUG
printf ("argv[%d] = %s\n", argc, argv[argc]);
#endif
if ((0 == strcmp (argv[argc], "-f")) ||
(0 == strcmp (argv[argc], "-file")) ||
(0 == strcmp (argv[argc], "-m")) ||
164,7 → 172,7
 
/* Try to initialize, then we can free the local argument vector. If we
fail to initialize return NULL to indicate that failure. */
res == or1ksim_init (local_argc, local_argv, NULL, NULL, NULL);
res = or1ksim_init (local_argc, local_argv, NULL, NULL, NULL);
free (local_argv);
 
if (res)
205,6 → 213,10
sim_close (SIM_DESC sd,
int quitting)
{
#ifdef OR32_SIM_DEBUG
printf ("sim_close called\n");
#endif
 
if (NULL == sd)
{
fprintf (stderr,
256,6 → 268,10
{
bfd *prog_bfd;
 
#ifdef OR32_SIM_DEBUG
printf ("sim_load called\n");
#endif
 
/* Use the built in loader, which will in turn use our write function. */
prog_bfd = sim_load_file (sd, sd->myname, sd->callback, prog, abfd,
sd->is_debug, 0, sim_write);
314,6 → 330,10
char **argv ATTRIBUTE_UNUSED,
char **env ATTRIBUTE_UNUSED)
{
#ifdef OR32_SIM_DEBUG
printf ("sim_create_inferior called\n");
#endif
 
or1ksim_set_stall_state (1);
sd->entry_point = (NULL == abfd) ? OR32_RESET_EXCEPTION :
bfd_get_start_address (abfd);
343,7 → 363,9
{
int res = or1ksim_read_mem (mem, buf, len);
 
/* printf ("Reading %d bytes from 0x%08p\n", len, mem); */
#ifdef OR32_SIM_DEBUG
printf ("Reading %d bytes from 0x%08p\n", len, mem);
#endif
 
return res;
 
367,7 → 389,9
unsigned char *buf,
int len)
{
/* printf ("Writing %d bytes to 0x%08p\n", len, mem); */
#ifdef OR32_SIM_DEBUG
printf ("Writing %d bytes to 0x%08p\n", len, mem);
#endif
 
return or1ksim_write_mem ((unsigned int) mem, buf, len);
 
404,6 → 428,9
unsigned long int regval;
int res;
 
#ifdef OR32_SIM_DEBUG
printf ("sim_fetch_register (regno=%d\n) called\n", regno);
#endif
if (4 != len)
{
fprintf (stderr, "Invalid register length %d\n");
427,11 → 454,13
buf[1] = (regval >> 16) & 0xff;
buf[2] = (regval >> 8) & 0xff;
buf[3] = regval & 0xff;
 
return 4; /* Success */
}
 
/* printf ("Read register 0x%02x, value 0x%08x\n", regno, regval); */
return res;
 
else
{
return 0; /* Failure */
}
} /* sim_fetch_register () */
 
 
464,6 → 493,10
{
unsigned int regval;
 
#ifdef OR32_SIM_DEBUG
printf ("sim_store_register (regno=%d\n) called\n", regno);
#endif
 
if (4 != len)
{
fprintf (stderr, "Invalid register length %d\n");
476,7 → 509,9
(((unsigned int) buf[2]) << 8) |
(((unsigned int) buf[3]) );
 
/* printf ("Writing register 0x%02x, value 0x%08x\n", regno, regval); */
#ifdef OR32_SIM_DEBUG
printf ("Writing register 0x%02x, value 0x%08x\n", regno, regval);
#endif
 
if (OR32_NPC_REGNUM == regno)
{
555,6 → 590,10
 
int res; /* Result of a run. */
 
#ifdef OR32_SIM_DEBUG
printf ("sim_resume called\n");
#endif
 
/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
Register 2 */
(void) or1ksim_write_spr (OR32_SPR_DRR, 0);
586,6 → 625,10
/* Set the NPC if it has changed */
(void) or1ksim_read_reg (OR32_NPC_REGNUM, &npc);
 
#ifdef OR32_SIM_DEBUG
printf (" npc = 0x%08lx, resume_npc = 0x%08lx\n", npc, sd->resume_npc);
#endif
 
if (npc != sd->resume_npc)
{
(void) or1ksim_write_reg (OR32_NPC_REGNUM, sd->resume_npc);
645,6 → 688,10
/* ------------------------------------------------------------------------- */
int sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
{
#ifdef OR32_SIM_DEBUG
printf ("sim_stop called\n");
#endif
 
return 0; /* We don't support this */
 
} /* sim_stop () */
/openrisc/trunk/gnu-src/gdb-7.1/sim/or32/ChangeLog
1,3 → 1,18
2010-08-19 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* wrapper.c: OR32_SIM_DEBUG added to control debug messages.
(sim_close, sim_load, sim_create_inferior, sim_fetch_register)
(sim_stop): Debug statement added.
(sim_read, sim_write): Debug statements now controlled by
OR32_SIM_DEBUG.
(sim_store_register, sim_resume): Debug statement added and
existing debug statements now controlled by OR32_SIM_DEBUG.
 
2010-08-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* wrapper.c (sim_open): Assign result of or1ksim_init correctly.
(sim_fetch_register): Return correct length on success.
 
2010-08-04 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* wrapper.c (sim_resume): Only set the NPC back on a true
/openrisc/trunk/gnu-src/gdb-7.1/gdb/or32-tdep.c
578,10 → 578,10
static char *or32_gdb_reg_names[OR32_TOTAL_NUM_REGS] =
{
/* general purpose registers */
"gpr0", "gpr1", "gpr2", "gpr3", "gpr4", "gpr5", "gpr6", "gpr7",
"gpr8", "gpr9", "gpr10", "gpr11", "gpr12", "gpr13", "gpr14", "gpr15",
"gpr16", "gpr17", "gpr18", "gpr19", "gpr20", "gpr21", "gpr22", "gpr23",
"gpr24", "gpr25", "gpr26", "gpr27", "gpr28", "gpr29", "gpr30", "gpr31",
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 
/* previous program counter, next program counter and status register */
"ppc", "npc", "sr"
758,6 → 758,43
 
 
/*----------------------------------------------------------------------------*/
/*!Is this one of the registers used for passing arguments?
 
These are r3-r8 in the API.
 
@param[in] regnum The register to consider
 
@return Non-zero (TRUE) if it is an argument register, zero (FALSE)
otherwise. */
/*----------------------------------------------------------------------------*/
static int
or32_is_arg_reg (unsigned int regnum)
{
return (OR32_FIRST_ARG_REGNUM <= regnum) && (regnum <= OR32_LAST_ARG_REGNUM);
 
} /* or32_is_arg_reg () */
 
 
/*----------------------------------------------------------------------------*/
/*!Is this a callee saved register?
 
These are r10, r12, r14, r16, r18, r20, r22, r24, r26, r28 and r30 in the
API.
 
@param[in] regnum The register to consider
 
@return Non-zero (TRUE) if it is a callee saved register, zero (FALSE)
otherwise. */
/*----------------------------------------------------------------------------*/
static int
or32_is_callee_saved_reg (unsigned int regnum)
{
return (OR32_FIRST_SAVED_REGNUM <= regnum) && (0 == regnum % 2);
 
} /* or32_is_callee_saved_reg () */
 
 
/*----------------------------------------------------------------------------*/
/*!Skip a function prolog
 
If the input address, PC, is in a function prologue, return the address of
764,8 → 801,12
the end of the prologue, otherwise return the input address.
 
@see For details of the stack frame, see the function
or32_frame_cache().
or32_frame_cache().
 
@note The old version of this function used to use skip_prologue_using_sal
to skip the prologue without checking if it had actually worked. It
doesn't for STABS, so we had better check for a valid result.
 
This function reuses the helper functions from or32_frame_cache() to
locate the various parts of the prolog, any or all of which may be missing.
 
775,7 → 816,6
@return The address of the end of the prolog if the PC is in a function
prologue, otherwise the input address. */
/*----------------------------------------------------------------------------*/
 
static CORE_ADDR
or32_skip_prologue (struct gdbarch *gdbarch,
CORE_ADDR pc)
789,12 → 829,15
int frame_size = 0;
 
/* Try using SAL first if we have symbolic information available. */
if (find_pc_partial_function (pc, NULL, NULL, NULL))
{
CORE_ADDR prologue_end = skip_prologue_using_sal( gdbarch, pc );
/* if (find_pc_partial_function (pc, NULL, NULL, NULL)) */
/* { */
/* CORE_ADDR prologue_end = skip_prologue_using_sal( gdbarch, pc ); */
 
return (prologue_end > pc) ? prologue_end : pc;
}
/* if (0 != prologue_end) */
/* { */
/* return (prologue_end > pc) ? prologue_end : pc; */
/* } */
/* } */
 
/* Look to see if we can find any of the standard prologue sequence. All
quite difficult, since any or all of it may be missing. So this is just a
837,14 → 880,17
inst = or32_fetch_instruction (gdbarch, addr);
}
 
/* Look for callee-saved register being saved. The register must be one
of the 10 callee saved registers (r10, r12, r14, r16, r18, r20, r22,
r24, r26, r28, r30).*/
/* Look for arguments or callee-saved register being saved. The register
must be one of the arguments (r3-r8) or the 10 callee saved registers
(r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base
register must be the FP (for the args) or the SP (for the callee_saved
registers). */
while (1)
{
if (or32_analyse_l_sw (inst, &simm, &ra, &rb) &&
(OR32_SP_REGNUM == ra) && (rb >= OR32_FIRST_SAVED_REGNUM) &&
(0 == rb % 2) && (simm >= 0) && (0 == (simm % 4)))
(((OR32_FP_REGNUM == ra) && or32_is_arg_reg (rb)) ||
((OR32_SP_REGNUM == ra) && or32_is_callee_saved_reg (rb))) &&
(0 == (simm % 4)))
{
addr += OR32_INSTLEN;
inst = or32_fetch_instruction (gdbarch, addr);
1248,8 → 1294,9
get_frame_register_unsigned (this_frame,
OR32_SP_REGNUM);
 
/* The frame base of THIS frame is its stack pointer. This is the same
whether we are frameless or not. */
/* The frame base of THIS frame (for ID purposes only - frame base is an
overloaded term) is its stack pointer. This is the same whether we are
frameless or not. */
trad_frame_set_this_base (info, this_sp);
 
/* The default is to find the PC of the PREVIOUS frame in the link register
1346,14 → 1393,17
trad_frame_set_reg_addr (info, OR32_NPC_REGNUM, this_sp + simm);
}
 
/* Look for callee-saved register being save. The register must be one
of the 10 callee saved registers (r10, r12, r14, r16, r18, r20, r22,
r24, r26, r28, r30).*/
/* Look for arguments or callee-saved register being saved. The register
must be one of the arguments (r3-r8) or the 10 callee saved registers
(r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base
register must be the FP (for the args) or the SP (for the
callee_saved registers). */
while (addr < end_addr)
{
if (or32_analyse_l_sw (inst, &simm, &ra, &rb) &&
(OR32_SP_REGNUM == ra) && (rb >= OR32_FIRST_SAVED_REGNUM) &&
(0 == rb % 2) && (simm >= 0) && (0 == (simm % 4)))
(((OR32_FP_REGNUM == ra) && or32_is_arg_reg (rb)) ||
((OR32_SP_REGNUM == ra) && or32_is_callee_saved_reg (rb))) &&
(0 == (simm % 4)))
{
addr += OR32_INSTLEN;
inst = or32_fetch_instruction (gdbarch, addr);
1465,7 → 1515,7
The implementations has changed since GDB 6.8, since we are now provided
with the address of THIS frame, rather than the NEXT frame.
 
For the OR32, the base address is defined to be the stack pointer.
For the OR32, the base address is the frame pointer
 
@param[in] this_frame The current stack frame.
@param[in] prologue_cache Any cached prologue for THIS function.
1477,7 → 1527,7
or32_frame_base_address (struct frame_info *this_frame,
void **prologue_cache)
{
return (CORE_ADDR) get_frame_register_unsigned (this_frame, OR32_SP_REGNUM);
return (CORE_ADDR) get_frame_register_unsigned (this_frame, OR32_FP_REGNUM);
 
} /* or32_frame_base_address() */
 
/openrisc/trunk/gnu-src/gdb-7.1/gdb/ChangeLog.or32
1,3 → 1,17
2010-08-19 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* or32-tdep.c (or32_register_name): Changed to rnn rather than
gprnn to mach the assembler.
(or32_is_arg_reg, or32_is_callee_saved_reg): Added.
(or32_skip_prologue): Don't use skip_prologue_using_sal. Check for
argument as well as callee saved registers in prologue.
(or32_frame_cache):Check for argument as well as callee saved
registers in prologue.
 
2010-08-13 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* or32-tdep.c (or32_frame_base_address): Frame base is FP, not SP.
 
2010-07-30 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* or32-tdep.c (or32_fetch_instruction): Rewritten to use

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.