URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/
- from Rev 249 to Rev 250
- ↔ Reverse comparison
Rev 249 → Rev 250
/open8_urisc/trunk/VHDL/sdlc_monitor.vhd
File deleted
/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
79,8 → 79,6
|
entity o8_sdlc_if is |
generic( |
Monitor_Enable : boolean := false; |
Attach_Monitor_to_CPU_Side : boolean := false; |
Poly_Init : std_logic_vector(15 downto 0) := x"0000"; |
Set_As_Master : boolean := true; |
Clock_Offset : integer := 6; |
193,7 → 191,7
Open8_Bus.Wr_En and |
Write_Qual; |
|
DP_A_Wr_En <= Base_Addr_Match and |
DP_A_Wr_En <= Base_Addr_Match and |
Open8_Bus.Wr_En and |
Write_Qual; |
|
248,31 → 246,6
q_b => DP_B_Rd_Data |
); |
|
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate |
|
U_MON: entity work.sdlc_monitor |
port map( |
clock => Clock, |
address => DP_A_Addr, |
data => DP_A_Wr_Data, |
wren => DP_A_Wr_En, |
q => open |
); |
end generate; |
|
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate |
|
U_MON: entity work.sdlc_monitor |
port map( |
clock => Clock, |
address => DP_B_Addr, |
data => DP_B_Wr_Data, |
wren => DP_B_Wr_En, |
q => open |
); |
|
end generate; |
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-- *************************************************************************** |
-- * Memory Arbitration * |
-- *************************************************************************** |