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Rev 25 → Rev 26

/trunk/gcpad/bench/vhdl/tb-c.vhd
5,7 → 5,7
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: tb-c.vhd,v 1.1 2004-10-07 21:24:06 arniml Exp $
-- $Id: tb-c.vhd,v 1.2 2004-10-10 17:27:36 arniml Exp $
--
-------------------------------------------------------------------------------
 
15,6 → 15,14
for basic_b : gcpad_basic
use configuration work.gcpad_basic_struct_c0;
end for;
 
for full_b : gcpad_full
use configuration work.gcpad_full_struct_c0;
end for;
 
for all : gcpad_mod
use configuration work.gcpad_mod_behav_c0;
end for;
end for;
 
end tb_behav_c0;
/trunk/gcpad/bench/vhdl/tb.vhd
3,7 → 3,7
-- Testbench for the
-- GCpad controller core
--
-- $Id: tb.vhd,v 1.2 2004-10-09 17:05:59 arniml Exp $
-- $Id: tb.vhd,v 1.3 2004-10-10 17:27:44 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
56,55 → 56,48
 
 
use work.gcpad_pack.all;
use work.gcpad_comp.gcpad_basic;
use work.gcpad_comp.gcpad_full;
 
architecture behav of tb is
 
constant period_c : time := 100 ns;
constant reset_level_c : natural := 0;
constant clocks_per_1us_c : natural := 10;
 
component gcpad_basic
component gcpad_mod
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
pad_data_io : inout std_logic;
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_z_o : out std_logic;
but_start_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
ana_joy_x_o : out std_logic_vector(7 downto 0);
ana_joy_y_o : out std_logic_vector(7 downto 0);
ana_c_x_o : out std_logic_vector(7 downto 0);
ana_c_y_o : out std_logic_vector(7 downto 0);
ana_l_o : out std_logic_vector(7 downto 0);
ana_r_o : out std_logic_vector(7 downto 0)
rx_data_i : in std_logic_vector(63 downto 0)
);
end component;
 
constant period_c : time := 100 ns;
constant reset_level_c : natural := 0;
constant clocks_per_1us_c : natural := 10;
 
signal clk_s : std_logic;
signal reset_s : std_logic;
 
signal pad_data_s : std_logic;
-- signals for basic gcpad
signal stimuli_1_end_s : boolean;
signal pad_data_1_s : std_logic;
signal buttons_1_s : std_logic_vector(64 downto 0);
signal pad_request_1_s : std_logic;
signal pad_avail_1_s : std_logic;
signal rx_data_1_s : std_logic_vector(63 downto 0);
 
signal buttons_s : std_logic_vector(64 downto 0);
-- signals for full gcpad
signal stimuli_2_end_s : boolean;
signal pad_data_2_s : std_logic;
signal pad_request_2_s : std_logic;
signal pad_avail_2_s : std_logic;
signal pad_timeout_2_s : std_logic;
signal tx_size_2_s : std_logic_vector( 1 downto 0);
signal tx_command_2_s : std_logic_vector(23 downto 0);
signal rx_size_2_s : std_logic_vector( 3 downto 0);
signal rx_data_2_s : std_logic_vector(63 downto 0);
 
signal pad_request_s : std_logic;
signal pad_avail_s : std_logic;
 
begin
 
basic_b : gcpad_basic
115,99 → 108,91
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_s,
pad_avail_o => pad_avail_s,
pad_data_io => pad_data_s,
but_a_o => buttons_s(56),
but_b_o => buttons_s(57),
but_x_o => buttons_s(58),
but_y_o => buttons_s(59),
but_z_o => buttons_s(52),
but_start_o => buttons_s(60),
but_tl_o => buttons_s(54),
but_tr_o => buttons_s(53),
but_left_o => buttons_s(48),
but_right_o => buttons_s(49),
but_up_o => buttons_s(51),
but_down_o => buttons_s(50),
ana_joy_x_o => buttons_s(47 downto 40),
ana_joy_y_o => buttons_s(39 downto 32),
ana_c_x_o => buttons_s(31 downto 24),
ana_c_y_o => buttons_s(23 downto 16),
ana_l_o => buttons_s(15 downto 8),
ana_r_o => buttons_s( 7 downto 0)
pad_request_i => pad_request_1_s,
pad_avail_o => pad_avail_1_s,
pad_data_io => pad_data_1_s,
but_a_o => buttons_1_s(56),
but_b_o => buttons_1_s(57),
but_x_o => buttons_1_s(58),
but_y_o => buttons_1_s(59),
but_z_o => buttons_1_s(52),
but_start_o => buttons_1_s(60),
but_tl_o => buttons_1_s(54),
but_tr_o => buttons_1_s(53),
but_left_o => buttons_1_s(48),
but_right_o => buttons_1_s(49),
but_up_o => buttons_1_s(51),
but_down_o => buttons_1_s(50),
ana_joy_x_o => buttons_1_s(47 downto 40),
ana_joy_y_o => buttons_1_s(39 downto 32),
ana_c_x_o => buttons_1_s(31 downto 24),
ana_c_y_o => buttons_1_s(23 downto 16),
ana_l_o => buttons_1_s(15 downto 8),
ana_r_o => buttons_1_s( 7 downto 0)
);
 
buttons_s(64) <= '0';
buttons_s(63 downto 61) <= (others => '0');
buttons_s(55) <= '1';
buttons_1_s(64) <= '0';
buttons_1_s(63 downto 61) <= (others => '0');
buttons_1_s(55) <= '1';
 
 
-- pullup on pad_data
-- pad_data_s <= 'H';
full_b: gcpad_full
generic map (
reset_level_g => reset_level_c,
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_2_s,
pad_avail_o => pad_avail_2_s,
pad_timeout_o => pad_timeout_2_s,
tx_size_i => tx_size_2_s,
tx_command_i => tx_command_2_s,
rx_size_i => rx_size_2_s,
rx_data_o => rx_data_2_s,
pad_data_io => pad_data_2_s
);
 
 
stimuli: process
pad_1 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_1_s,
rx_data_i => rx_data_1_s
);
 
procedure check_request is
constant request_c : std_logic_vector(24 downto 0) := "H0H000000HH000000000000H0";
begin
-----------------------------------------------------------------------------
-- Process stimuli_pad_1
--
-- Executes test stimuli with Pad 1, the gcpad_basic flavour.
--
stimuli_pad_1: process
 
-- read 25 bits from pad_data_s
for i in 0 to 24 loop
wait until pad_data_s = '0';
 
wait for 2 * clocks_per_1us_c * period_c;
if pad_data_s /= request_c(i) then
assert false
report "Found wrong level on pad_data_s while checking request packet!"
severity error;
end if;
 
wait for 2 * clocks_per_1us_c * period_c;
 
end loop;
 
 
end check_request;
 
procedure send_packet(packet : in std_logic_vector(64 downto 0)) is
variable time_low_v, time_high_v : time;
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
 
rx_data_1_s <= packet(64 downto 1);
 
-- send request;
pad_request_s <= '1';
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_s <= '0';
pad_request_1_s <= '0';
 
check_request;
 
wait for 10 * 40 * period_c;
 
for i in packet'high downto 0 loop
if packet(i) = '0' then
time_low_v := 3 us;
time_high_v := 1 us;
else
time_low_v := 1 us;
time_high_v := 3 us;
end if;
 
pad_data_s <= '0';
wait for time_low_v;
 
pad_data_s <= 'H';
wait for time_high_v;
 
end loop;
 
wait until pad_avail_s = '1';
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
 
-- check result
for i in 1 to packet'high loop
assert packet(i) = buttons_s(i-1)
assert packet(i) = buttons_1_s(i-1)
report "Button mismatch!"
severity error;
end loop;
218,21 → 203,29
procedure timeout_gcpad is
begin
-- send request;
pad_request_s <= '1';
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_s <= '0';
pad_request_1_s <= '0';
 
check_request;
wait for 2 * period_c;
 
wait until pad_avail_s = '1';
-- disturb communication
pad_data_1_s <= 'X';
 
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
pad_data_1_s <= 'H';
wait for 10 * period_c;
 
end timeout_gcpad;
 
begin
pad_data_s <= 'H';
pad_request_s <= '0';
stimuli_1_end_s <= false;
 
pad_data_1_s <= 'H';
pad_request_1_s <= '0';
rx_data_1_s <= (others => '0');
 
wait until reset_s = '1';
wait for period_c * 4;
 
306,15 → 299,74
 
 
wait for period_c * 2*40;
assert false
report "End of simulation reached."
severity failure;
stimuli_1_end_s <= true;
wait;
 
end process stimuli;
end process stimuli_pad_1;
--
-----------------------------------------------------------------------------
 
 
pad_2 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_2_s,
rx_data_i => rx_data_2_s
);
 
-----------------------------------------------------------------------------
-- Process stimuli_pad_2
--
-- Executes test stimuli with Pad 2, the gcpad_full flavour.
--
stimuli_pad_2: process
 
procedure issue_command(cmd : in std_logic_vector(23 downto 0);
size : in std_logic_vector( 1 downto 0)) is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
 
tx_command_2_s <= cmd;
tx_size_2_s <= size;
-- send request;
pad_request_2_s <= '1';
wait for 1 * period_c;
pad_request_2_s <= '0';
 
 
end issue_command;
 
begin
stimuli_2_end_s <= false;
 
pad_data_2_s <= 'H';
pad_request_2_s <= '0';
tx_size_2_s <= (others => '0');
tx_command_2_s <= (others => '0');
rx_size_2_s <= (others => '0');
 
wait until reset_s = '1';
wait for period_c * 4;
 
 
issue_command(cmd => "010000000000001100000010",
size => "11");
 
 
wait for period_c * 2*40;
stimuli_2_end_s <= true;
wait;
 
end process stimuli_pad_2;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
344,6 → 396,19
wait;
end process reset;
 
 
-----------------------------------------------------------------------------
-- End of simulation detection
-----------------------------------------------------------------------------
eos: process (stimuli_1_end_s, stimuli_2_end_s)
begin
if stimuli_1_end_s and stimuli_2_end_s then
assert false
report "End of simulation reached."
severity failure;
end if;
end process eos;
 
end behav;
 
 
351,6 → 416,9
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/10/09 17:05:59 arniml
-- delay assertion of request signal by real time (instead of delta cycles)
--
-- Revision 1.1 2004/10/07 21:24:06 arniml
-- initial check-in
--

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