OpenCores

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/trunk/doc/i2s.pdf

trunk/doc/i2s.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/copying.txt =================================================================== --- trunk/doc/copying.txt (revision 25) +++ trunk/doc/copying.txt (nonexistent) @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. 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Index: trunk/doc/src/i2s.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/i2s.doc =================================================================== --- trunk/doc/src/i2s.doc (revision 25) +++ trunk/doc/src/i2s.doc (nonexistent)

trunk/doc/src/i2s.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/bench/vhdl/wb_tb_pack.txt =================================================================== --- trunk/bench/vhdl/wb_tb_pack.txt (revision 25) +++ trunk/bench/vhdl/wb_tb_pack.txt (nonexistent) @@ -1,2 +0,0 @@ -The VHDL file wb_tb_pack.vhd is reused from the SPDIF interface project. -Fetch the file spdif_interface/bench/vhdl/wb_tb_pack.vhd. \ No newline at end of file Index: trunk/bench/vhdl/tb_i2s.vhd =================================================================== --- trunk/bench/vhdl/tb_i2s.vhd (revision 25) +++ trunk/bench/vhdl/tb_i2s.vhd (nonexistent) @@ -1,465 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S top level test bench. Two transmitters and two receivers ---- ----- are instantiated, one each in slave and master mode. ---- ----- Test result is displayed in the log window, there should ---- ----- be no errors. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/07 12:33:29 gedra --- De-linted. --- --- Revision 1.1 2004/08/04 14:31:02 gedra --- Top level test bench. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.wb_tb_pack.all; - -entity tb_i2s is - -end tb_i2s; - -architecture behav of tb_i2s is - - component tx_i2s_topm - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - -- Wishbone interface - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - -- Interrupt line - tx_int_o : out std_logic; - -- I2S signals - i2s_sd_o : out std_logic; - i2s_sck_o : out std_logic; - i2s_ws_o : out std_logic); - end component; - - component tx_i2s_tops - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sck_i : in std_logic; - i2s_ws_i : in std_logic; - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - tx_int_o : out std_logic; - i2s_sd_o : out std_logic); - end component; - - component rx_i2s_topm - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sd_i : in std_logic; -- I2S data input - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - rx_int_o : out std_logic; -- Interrupt line - i2s_sck_o : out std_logic; -- I2S clock out - i2s_ws_o : out std_logic); -- I2S word select out - end component; - - component rx_i2s_tops - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sd_i : in std_logic; -- I2S data input - i2s_sck_i : in std_logic; -- I2S clock input - i2s_ws_i : in std_logic; -- I2S word select input - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - rx_int_o : out std_logic); -- Interrupt line - end component; - - signal wb_clk_o, wb_rst_o, wb_sel_o, wb_stb_o, wb_we_o : std_logic; - signal wb_cyc_o, wb_ack_i, rx1_int_o : std_logic; - signal tx_int_o, tx1_ack, rx1_ack, tx2_ack, rx2_ack : std_logic; - signal rx2_int_o, tx1_int_o, tx2_int_o : std_logic; - signal wb_bte_o : std_logic_vector(1 downto 0); - signal wb_cti_o : std_logic_vector(2 downto 0); - signal wb_adr_o : std_logic_vector(15 downto 0); - signal wb_dat_i, wb_dat_o, rx1_dat_i : std_logic_vector(31 downto 0); - signal tx1_dat_i, rx2_dat_i, tx2_dat_i : std_logic_vector(31 downto 0); - signal wb_stb_32bit_rx1, wb_stb_32bit_tx1 : std_logic; - signal wb_stb_32bit_rx2, wb_stb_32bit_tx2 : std_logic; - signal i2s_sd1, i2s_sd2, i2s_sck1, i2s_sck2, i2s_ws1, i2s_ws2 : std_logic; - -- register address definitions - constant RX1_VERSION : natural := 16#1000#; - constant RX1_CONFIG : natural := 16#1001#; - constant RX1_INTMASK : natural := 16#1002#; - constant RX1_INTSTAT : natural := 16#1003#; - constant RX1_BUF_BASE : natural := 16#1020#; - constant TX1_VERSION : natural := 16#2000#; - constant TX1_CONFIG : natural := 16#2001#; - constant TX1_INTMASK : natural := 16#2002#; - constant TX1_INTSTAT : natural := 16#2003#; - constant TX1_BUF_BASE : natural := 16#2020#; - constant RX2_VERSION : natural := 16#3000#; - constant RX2_CONFIG : natural := 16#3001#; - constant RX2_INTMASK : natural := 16#3002#; - constant RX2_INTSTAT : natural := 16#3003#; - constant RX2_BUF_BASE : natural := 16#3020#; - constant TX2_VERSION : natural := 16#4000#; - constant TX2_CONFIG : natural := 16#4001#; - constant TX2_INTMASK : natural := 16#4002#; - constant TX2_INTSTAT : natural := 16#4003#; - constant TX2_BUF_BASE : natural := 16#4020#; - -begin - - wb_ack_i <= rx1_ack or tx1_ack or rx2_ack or tx2_ack; - wb_dat_i <= rx1_dat_i when wb_stb_32bit_rx1 = '1' - else tx1_dat_i when wb_stb_32bit_tx1 = '1' - else rx2_dat_i when wb_stb_32bit_rx2 = '1' - else tx2_dat_i when wb_stb_32bit_tx2 = '1' - else (others => '0'); - --- I2S transmitter 1, slave mode - ITX32S : tx_i2s_tops - generic map (DATA_WIDTH => 32, - ADDR_WIDTH => 6) - port map ( - -- Wishbone interface - wb_clk_i => wb_clk_o, - wb_rst_i => wb_rst_o, - wb_sel_i => wb_sel_o, - wb_stb_i => wb_stb_32bit_tx1, - wb_we_i => wb_we_o, - wb_cyc_i => wb_cyc_o, - wb_bte_i => wb_bte_o, - wb_cti_i => wb_cti_o, - wb_adr_i => wb_adr_o(5 downto 0), - wb_dat_i => wb_dat_o(31 downto 0), - wb_ack_o => tx1_ack, - wb_dat_o => tx1_dat_i, - tx_int_o => tx1_int_o, - i2s_sd_o => i2s_sd1, - i2s_sck_i => i2s_sck1, - i2s_ws_i => i2s_ws1); - --- I2S transmitter 2, master mode - ITX32M : tx_i2s_topm - generic map (DATA_WIDTH => 32, - ADDR_WIDTH => 6) - port map ( - -- Wishbone interface - wb_clk_i => wb_clk_o, - wb_rst_i => wb_rst_o, - wb_sel_i => wb_sel_o, - wb_stb_i => wb_stb_32bit_tx2, - wb_we_i => wb_we_o, - wb_cyc_i => wb_cyc_o, - wb_bte_i => wb_bte_o, - wb_cti_i => wb_cti_o, - wb_adr_i => wb_adr_o(5 downto 0), - wb_dat_i => wb_dat_o(31 downto 0), - wb_ack_o => tx2_ack, - wb_dat_o => tx2_dat_i, - tx_int_o => tx2_int_o, - i2s_sd_o => i2s_sd2, - i2s_sck_o => i2s_sck2, - i2s_ws_o => i2s_ws2); - --- I2S receiver 1, master mode - IRX32M : rx_i2s_topm - generic map (DATA_WIDTH => 32, - ADDR_WIDTH => 6) - port map ( - -- Wishbone interface - wb_clk_i => wb_clk_o, - wb_rst_i => wb_rst_o, - wb_sel_i => wb_sel_o, - wb_stb_i => wb_stb_32bit_rx1, - wb_we_i => wb_we_o, - wb_cyc_i => wb_cyc_o, - wb_bte_i => wb_bte_o, - wb_cti_i => wb_cti_o, - wb_adr_i => wb_adr_o(5 downto 0), - wb_dat_i => wb_dat_o(31 downto 0), - i2s_sd_i => i2s_sd1, - wb_ack_o => rx1_ack, - wb_dat_o => rx1_dat_i, - rx_int_o => rx1_int_o, - i2s_sck_o => i2s_sck1, - i2s_ws_o => i2s_ws1); - --- I2S receiver 2, slave mode - IRX32S : rx_i2s_tops - generic map (DATA_WIDTH => 32, - ADDR_WIDTH => 6) - port map ( - -- Wishbone interface - wb_clk_i => wb_clk_o, - wb_rst_i => wb_rst_o, - wb_sel_i => wb_sel_o, - wb_stb_i => wb_stb_32bit_rx2, - wb_we_i => wb_we_o, - wb_cyc_i => wb_cyc_o, - wb_bte_i => wb_bte_o, - wb_cti_i => wb_cti_o, - wb_adr_i => wb_adr_o(5 downto 0), - wb_dat_i => wb_dat_o(31 downto 0), - i2s_sd_i => i2s_sd2, - i2s_sck_i => i2s_sck2, - i2s_ws_i => i2s_ws2, - wb_ack_o => rx2_ack, - wb_dat_o => rx2_dat_i, - rx_int_o => rx2_int_o); - --- Main test process - MAIN : process - variable read_32bit : std_logic_vector(31 downto 0); - variable idx : integer; - - -- Make simplified versions of procedures in wb_tb_pack - procedure wb_write_32 ( - constant ADDRESS : in natural; - constant DATA : in natural) is - begin - wb_write(ADDRESS, DATA, wb_adr_o, wb_dat_o(31 downto 0), wb_cyc_o, - wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); - end; - - procedure wb_check_32 ( - constant ADDRESS : in natural; - constant EXP_DATA : in natural) is - begin - wb_check(ADDRESS, EXP_DATA, wb_adr_o, wb_dat_i(31 downto 0), wb_cyc_o, - wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); - end; - - procedure wb_read_32 ( - constant ADDRESS : in natural) is - begin - wb_read(ADDRESS, read_32bit, wb_adr_o, wb_dat_i(31 downto 0), wb_cyc_o, - wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); - end; - - begin - message("Simulation start with system reset."); - wb_rst_o <= '1'; -- system reset - wb_sel_o <= '0'; - wb_stb_o <= '0'; - wb_sel_o <= '0'; - wb_we_o <= '0'; - wb_cyc_o <= '0'; - wb_bte_o <= "00"; - wb_cti_o <= "000"; - wb_adr_o <= (others => '0'); - wb_dat_o <= (others => '0'); - wait for 200 ns; - wb_rst_o <= '0'; - message("Check receiver version registers:"); - wb_check_32(RX1_VERSION, 16#000001b1#); - wb_check_32(RX2_VERSION, 16#00000191#); - message("Check transmitter version registers:"); - wb_check_32(TX1_VERSION, 16#00000191#); - wb_check_32(TX2_VERSION, 16#000001b1#); - message("Fill up sample buffers with test signal, "); - message("ramp up in left, ramp down in right:"); - SGEN : for i in 0 to 15 loop - wb_write_32(TX1_BUF_BASE + 2*i, (32768 + i*497)*256); -- left - wb_write_32(TX1_BUF_BASE + 2*i + 1, (32767 - i*497)*256); -- right - wb_write_32(TX2_BUF_BASE + 2*i, (32767 - i*497)*16); -- left - wb_write_32(TX2_BUF_BASE + 2*i + 1, (32768 + i*497)*16); --right - end loop; - message("*** Test of master TX and slave RX ***"); - message("Enable transmitter 2:"); - wb_write_32(TX2_INTMASK, 16#00000003#); -- enable interrupts - wb_write_32(TX2_CONFIG, 16#00140703#); -- 20bit resolution - message("Enable recevier 2:"); - wb_write_32(RX2_INTMASK, 16#00000003#); -- enable interrupts - wb_write_32(RX2_CONFIG, 16#00180003#); -- 24bit resolution - wait_for_event("Wait for transmitter 2 LSBF interrupt", 150 us, tx2_int_o); - wait for 1 us; - message("Check for receiver LSBF interrupt:"); - wb_check_32(RX2_INTSTAT, 16#00000001#); - message("Clear transmitter LSBF interrupt:"); - wb_write_32(TX2_INTSTAT, 16#00000001#); - wb_check_32(TX2_INTSTAT, 16#00000000#); - signal_check("tx2_int_o", '0', tx2_int_o); - message("Clear receiver LSBF interrupt:"); - wb_write_32(RX2_INTSTAT, 16#00000001#); - wb_check_32(RX2_INTSTAT, 16#00000000#); - signal_check("rx2_int_o", '0', rx2_int_o); - message("Check received data, lower sample buffer:"); - wb_read_32(RX2_BUF_BASE); - -- calculate which index this word was generated with - idx := (32767 - to_integer(unsigned(read_32bit(31 downto 8)))) / 497; - -- then check for correct values - CHKL : for i in 0 to 7 - idx loop - wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256); - wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256); - end loop; - wait_for_event("Wait for transmitter 2 HSBF interrupt", 150 us, tx2_int_o); - wait for 1 us; - message("Check for receiver LSBF interrupt:"); - wb_check_32(RX2_INTSTAT, 16#00000002#); - message("Clear transmitter HSBF interrupt:"); - wb_write_32(TX2_INTSTAT, 16#00000002#); - wb_check_32(TX2_INTSTAT, 16#00000000#); - signal_check("tx2_int_o", '0', tx2_int_o); - message("Clear receiver HSBF interrupt:"); - wb_write_32(RX2_INTSTAT, 16#00000002#); - wb_check_32(RX2_INTSTAT, 16#00000000#); - signal_check("rx2_int_o", '0', rx2_int_o); - message("Check received data, upper sample buffer:"); - CHKH : for i in 8 - idx to 15 - idx loop - wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256); - wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256); - end loop; - - message("*** Test of slave TX and master RX ***"); - message("Enable transmitter 1:"); - wb_write_32(TX1_INTMASK, 16#00000003#); -- enable interrupts - wb_write_32(TX1_CONFIG, 16#00180007#); -- 24bit resolution - message("Enable recevier 1:"); - wb_write_32(RX1_INTMASK, 16#00000003#); -- enable interrupts - wb_write_32(RX1_CONFIG, 16#00100707#); -- 16bit resolution - wait_for_event("Wait for transmitter 1 LSBF interrupt", 150 us, tx1_int_o); - message("Clear LSBF interrupt:"); - wb_write_32(TX1_INTSTAT, 16#00000001#); - wb_check_32(TX1_INTSTAT, 16#00000000#); - signal_check("tx1_int_o", '0', tx1_int_o); - wait_for_event("Wait for recevier 1 LSBF interrupt", 150 us, rx1_int_o); - message("Clear LSBF interrupt:"); - wb_write_32(RX1_INTSTAT, 16#00000001#); - wb_check_32(RX1_INTSTAT, 16#00000000#); - signal_check("rx1_int_o", '0', rx1_int_o); - message("Check received data (#1), lower sample buffer:"); - wb_read_32(RX1_BUF_BASE); - -- calculate which index this word was generated with - idx := (32767 - to_integer(unsigned(read_32bit(15 downto 0)))) / 497; - -- then check for correct values - CHKL1 : for i in 0 to 7 - idx loop - wb_check_32(RX1_BUF_BASE + 2*i, 32768 + (i+idx)*497); - wb_check_32(RX1_BUF_BASE + 2*i + 1, 32767 - (i+idx)*497); - end loop; - wait_for_event("Wait for transmitter 1 HSBF interrupt", 150 us, tx1_int_o); - message("Clear HSBF interrupt:"); - wb_write_32(TX1_INTSTAT, 16#00000002#); - wb_check_32(TX1_INTSTAT, 16#00000000#); - signal_check("tx1_int_o", '0', tx1_int_o); - wait_for_event("Wait for recevier 1 HSBF interrupt", 150 us, rx1_int_o); - message("Clear HSBF interrupt:"); - wb_write_32(RX1_INTSTAT, 16#00000002#); - wb_check_32(RX1_INTSTAT, 16#00000000#); - signal_check("rx1_int_o", '0', rx1_int_o); - message("Check received data (#1), higher sample buffer:"); - CHKH1 : for i in 8 - idx to 15 - idx loop - wb_check_32(RX1_BUF_BASE + 2*i, 32768 + (i+idx)*497); - wb_check_32(RX1_BUF_BASE + 2*i + 1, 32767 - (i+idx)*497); - end loop; - - sim_report(""); - report "End of simulation! (ignore this failure)" - severity failure; - wait; - end process MAIN; - --- Bus strobe generator based on address. 32bit recevier mapped to addr. 0x1000 --- 32bit transmitter mapped to address 0x2000 - wb_stb_32bit_rx1 <= '1' when wb_adr_o(15 downto 12) = "0001" else '0'; - wb_stb_32bit_tx1 <= '1' when wb_adr_o(15 downto 12) = "0010" else '0'; - wb_stb_32bit_rx2 <= '1' when wb_adr_o(15 downto 12) = "0011" else '0'; - wb_stb_32bit_tx2 <= '1' when wb_adr_o(15 downto 12) = "0100" else '0'; - --- Clock process, 50Mhz Wishbone master freq. - CLKGEN : process - begin - wb_clk_o <= '0'; - wait for 10 ns; - wb_clk_o <= '1'; - wait for 10 ns; - end process CLKGEN; - -end behav; - - - Index: trunk/rtl/vhdl/tx_i2s_pack.vhd =================================================================== --- trunk/rtl/vhdl/tx_i2s_pack.vhd (revision 25) +++ trunk/rtl/vhdl/tx_i2s_pack.vhd (nonexistent) @@ -1,165 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S transmitter component declarations. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:29:10 gedra --- Transmitter component declarations. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; - -package tx_i2s_pack is - --- components used in the transmitter - - component gen_control_reg - generic (DATA_WIDTH : integer; - -- note that this vector is (0 to xx), reverse order - ACTIVE_BIT_MASK : std_logic_vector); - port ( - clk : in std_logic; -- clock - rst : in std_logic; -- reset - ctrl_wr : in std_logic; -- control register write - ctrl_rd : in std_logic; -- control register read - ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); - ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); - ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component gen_event_reg - generic (DATA_WIDTH : integer); - port ( - clk : in std_logic; -- clock - rst : in std_logic; -- reset - evt_wr : in std_logic; -- event register write - evt_rd : in std_logic; -- event register read - evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data - event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector - evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask - evt_en : in std_logic; -- irq enable - evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data - evt_irq : out std_logic); -- interrupt request - end component; - - component dpram - generic (DATA_WIDTH : positive; - RAM_WIDTH : positive); - port ( - clk : in std_logic; - rst : in std_logic; -- reset is optional, not used here - din : in std_logic_vector(DATA_WIDTH - 1 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); - rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); - dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component i2s_version - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer); - port ( - ver_rd : in std_logic; -- version register read - ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component tx_i2s_wbd - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - wb_clk_i : in std_logic; -- wishbone clock - wb_rst_i : in std_logic; -- reset signal - wb_sel_i : in std_logic; -- select input - wb_stb_i : in std_logic; -- strobe input - wb_we_i : in std_logic; -- write enable - wb_cyc_i : in std_logic; -- cycle input - wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension - wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address - data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus - wb_ack_o : out std_logic; -- acknowledge - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out - version_rd : out std_logic; -- Version register read - config_rd : out std_logic; -- Config register read - config_wr : out std_logic; -- Config register write - intmask_rd : out std_logic; -- Interrupt mask register read - intmask_wr : out std_logic; -- Interrupt mask register write - intstat_rd : out std_logic; -- Interrupt status register read - intstat_wr : out std_logic; -- Interrupt status register read - mem_wr : out std_logic); -- Sample memory write - end component; - - component i2s_codec - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer range 0 to 1; - IS_RECEIVER : integer range 0 to 1); - port ( - wb_clk_i : in std_logic; -- wishbone clock - conf_res : in std_logic_vector(5 downto 0); -- sample resolution - conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio - conf_swap : in std_logic; -- left/right sample order - conf_en : in std_logic; -- transmitter/recevier enable - i2s_sd_i : in std_logic; -- I2S serial data input - i2s_sck_i : in std_logic; -- I2S clock input - i2s_ws_i : in std_logic; -- I2S word select input - sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - mem_rdwr : out std_logic; -- sample buffer read/write - sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address - evt_hsbf : out std_logic; -- higher sample buf empty event - evt_lsbf : out std_logic; -- lower sample buf empty event - i2s_sd_o : out std_logic; -- I2S serial data output - i2s_sck_o : out std_logic; -- I2S clock output - i2s_ws_o : out std_logic); -- I2S word select output - end component; - -end tx_i2s_pack; Index: trunk/rtl/vhdl/tx_i2s_topm.vhd =================================================================== --- trunk/rtl/vhdl/tx_i2s_topm.vhd (revision 25) +++ trunk/rtl/vhdl/tx_i2s_topm.vhd (nonexistent) @@ -1,277 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S transmitter. Top level entity for the transmitter core, ---- ----- master mode. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:30:14 gedra --- Transmitter top level, master mode. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use work.tx_i2s_pack.all; - -entity tx_i2s_topm is - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - -- Wishbone interface - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - -- Interrupt line - tx_int_o : out std_logic; - -- I2S signals - i2s_sd_o : out std_logic; - i2s_sck_o : out std_logic; - i2s_ws_o : out std_logic); -end tx_i2s_topm; - -architecture rtl of tx_i2s_topm is - - signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal version_rd : std_logic; - signal config_rd, config_wr, status_rd : std_logic; - signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_rd, intmask_wr : std_logic; - signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_rd, intstat_wr : std_logic; - signal evt_hsbf, evt_lsbf : std_logic; - signal mem_wr, mem_rd : std_logic; - signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0); - signal sample_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal conf_ratio : std_logic_vector(7 downto 0); - signal conf_res : std_logic_vector(5 downto 0); - signal conf_tswap, conf_tinten, conf_txen : std_logic; - signal zero : std_logic; - -begin - --- Data bus or'ing - data_out <= version_dout or config_dout or intmask_dout or intstat_dout - when wb_adr_i(ADDR_WIDTH - 1) = '0' else (others => '0'); - --- Wishbone bus cycle decoder - WB : tx_i2s_wbd - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH) - port map ( - wb_clk_i => wb_clk_i, - wb_rst_i => wb_rst_i, - wb_sel_i => wb_sel_i, - wb_stb_i => wb_stb_i, - wb_we_i => wb_we_i, - wb_cyc_i => wb_cyc_i, - wb_bte_i => wb_bte_i, - wb_cti_i => wb_cti_i, - wb_adr_i => wb_adr_i, - data_out => data_out, - wb_ack_o => wb_ack_o, - wb_dat_o => wb_dat_o, - version_rd => version_rd, - config_rd => config_rd, - config_wr => config_wr, - intmask_rd => intmask_rd, - intmask_wr => intmask_wr, - intstat_rd => intstat_rd, - intstat_wr => intstat_wr, - mem_wr => mem_wr); - --- TxVersion - Version register - VER : i2s_version - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 1) - port map ( - ver_rd => version_rd, - ver_dout => version_dout); - --- TxConfig - Configuration register - CG32 : if DATA_WIDTH = 32 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11100000111111111111110000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= config_bits(21 downto 16); - end generate CG32; - CG16 : if DATA_WIDTH = 16 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1110000011111111") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= "010000"; -- 16bit only - end generate CG16; - conf_ratio(7 downto 0) <= config_bits(15 downto 8); - conf_tswap <= config_bits(2); - conf_tinten <= config_bits(1); - conf_txen <= config_bits(0); - --- TxIntMask - interrupt mask register - IM32 : if DATA_WIDTH = 32 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11000000000000000000000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM32; - IM16 : if DATA_WIDTH = 16 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1100000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM16; - --- TxIntStat - interrupt status register - ISTAT : gen_event_reg - generic map ( - DATA_WIDTH => DATA_WIDTH) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - evt_wr => intstat_wr, - evt_rd => intstat_rd, - evt_din => wb_dat_i, - evt_dout => intstat_dout, - event => intstat_events, - evt_mask => intmask_bits, - evt_en => conf_tinten, - evt_irq => tx_int_o); - intstat_events(0) <= evt_lsbf; -- lower sample buffer empty - intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty - intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); - --- Sample buffer memory - MEM : dpram - generic map ( - DATA_WIDTH => DATA_WIDTH, - RAM_WIDTH => ADDR_WIDTH - 1) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - din => wb_dat_i(DATA_WIDTH - 1 downto 0), - wr_en => mem_wr, - rd_en => mem_rd, - wr_addr => wb_adr_i(ADDR_WIDTH - 2 downto 0), - rd_addr => sample_addr, - dout => sample_data); - --- Transmit encoder - zero <= '0'; - - ENC : i2s_codec - generic map (DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 1, - IS_RECEIVER => 0) - port map ( - wb_clk_i => wb_clk_i, - conf_res => conf_res, - conf_ratio => conf_ratio, - conf_swap => conf_tswap, - conf_en => conf_txen, - i2s_sd_i => zero, - i2s_sck_i => zero, - i2s_ws_i => zero, - sample_dat_i => sample_data, - sample_dat_o => open, - mem_rdwr => mem_rd, - sample_addr => sample_addr, - evt_hsbf => evt_hsbf, - evt_lsbf => evt_lsbf, - i2s_sd_o => i2s_sd_o, - i2s_sck_o => i2s_sck_o, - i2s_ws_o => i2s_ws_o); - -end rtl; - Index: trunk/rtl/vhdl/i2s_codec.vhd =================================================================== --- trunk/rtl/vhdl/i2s_codec.vhd (revision 25) +++ trunk/rtl/vhdl/i2s_codec.vhd (nonexistent) @@ -1,458 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S encoder/decoder. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.3 2005/06/03 17:18:08 gedra --- BugFix: LSB of transmitted word would be set to zero in slave master mode. (Credit: Julien Dumont) --- --- Revision 1.2 2004/08/06 18:55:05 gedra --- Removed conf_inten, and fixed bug in transmitter master mode. --- --- Revision 1.1 2004/08/03 18:49:43 gedra --- I2S encoder/decoder. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity i2s_codec is - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer range 0 to 1; - IS_RECEIVER : integer range 0 to 1); - port ( - wb_clk_i : in std_logic; -- wishbone clock - conf_res : in std_logic_vector(5 downto 0); -- sample resolution - conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio - conf_swap : in std_logic; -- left/right sample order - conf_en : in std_logic; -- transmitter/recevier enable - i2s_sd_i : in std_logic; -- I2S serial data input - i2s_sck_i : in std_logic; -- I2S clock input - i2s_ws_i : in std_logic; -- I2S word select input - sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - mem_rdwr : out std_logic; -- sample buffer read/write - sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address - evt_hsbf : out std_logic; -- higher sample buf empty event - evt_lsbf : out std_logic; -- lower sample buf empty event - i2s_sd_o : out std_logic; -- I2S serial data output - i2s_sck_o : out std_logic; -- I2S clock output - i2s_ws_o : out std_logic); -- I2S word select output -end i2s_codec; - -architecture rtl of i2s_codec is - - signal i2s_clk_en, zsck, zzsck, zzzsck, imem_rd : std_logic; - signal clk_cnt : integer range 0 to 255; - signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; - type srx_states is (IDLE, WAIT_CLK, TRX_DATA, RX_WRITE, SYNC); - signal sd_ctrl : srx_states; - signal bit_cnt, bits_to_trx : integer range 0 to 63; - signal toggle, master, neg_edge, ws_pos_edge, ws_neg_edge : std_logic; - signal data_in : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal zws, zzws, zzzws, i2s_ws, new_word, last_bit : std_logic; - signal imem_rdwr, receiver : std_logic; - signal ws_cnt : integer range 0 to 31; - -begin - --- Create signals that reflect generics - SGM : if IS_MASTER = 1 generate - master <= '1'; - end generate SGM; - SGS : if IS_MASTER = 0 generate - master <= '0'; - end generate SGS; - SGRX : if IS_RECEIVER = 1 generate - receiver <= '1'; - end generate SGRX; - SGTX : if IS_RECEIVER = 0 generate - receiver <= '0'; - end generate SGTX; - --- I2S clock enable generation, master mode. The clock is a fraction of the --- Wishbone bus clock, determined by the conf_ratio value. - CGM : if IS_MASTER = 1 generate - CGEN : process (wb_clk_i) - begin - if rising_edge(wb_clk_i) then - if conf_en = '0' then -- disabled - i2s_clk_en <= '0'; - clk_cnt <= 0; - neg_edge <= '0'; - toggle <= '0'; - else -- enabled - if clk_cnt < to_integer(unsigned(conf_ratio)) + 1 then - clk_cnt <= (clk_cnt + 1) mod 256; - i2s_clk_en <= '0'; - else - clk_cnt <= 0; - i2s_clk_en <= '1'; - neg_edge <= not neg_edge; - end if; - toggle <= neg_edge; - end if; - end if; - end process CGEN; - end generate CGM; - --- I2S clock enable generation, slave mode. The input clock signal is sampeled --- and the negative edge is located. - CGS : if IS_MASTER = 0 generate - CGEN : process (wb_clk_i) - begin - if rising_edge(wb_clk_i) then - if conf_en = '0' then -- disabled - i2s_clk_en <= '0'; - zsck <= '0'; - zzsck <= '0'; - zzzsck <= '0'; - toggle <= '0'; - neg_edge <= '0'; - else -- enabled - -- synchronize input clock to Wishbone clock domaine - zsck <= i2s_sck_i; - zzsck <= zsck; - zzzsck <= zzsck; - -- look for edges - if zzzsck = '1' and zzsck = '0' then - i2s_clk_en <= '1'; - neg_edge <= '1'; - elsif zzzsck = '0' and zzsck = '1' then - i2s_clk_en <= '1'; - neg_edge <= '0'; - else - i2s_clk_en <= '0'; - end if; - toggle <= neg_edge; - end if; - end if; - end process CGEN; - end generate CGS; - --- Process to generate word select signal, master mode - WSM : if IS_MASTER = 1 generate - i2s_ws_o <= i2s_ws; - WSG : process (wb_clk_i) - begin - if rising_edge(wb_clk_i) then - if conf_en = '0' then - i2s_ws <= '0'; - ws_cnt <= 0; - ws_pos_edge <= '0'; - ws_neg_edge <= '0'; - else - if i2s_clk_en = '1' and toggle = '1' then - if ws_cnt < bits_to_trx then - ws_cnt <= ws_cnt + 1; - else - i2s_ws <= not i2s_ws; - ws_cnt <= 0; - if i2s_ws = '1' then - ws_neg_edge <= '1'; - else - ws_pos_edge <= '1'; - end if; - end if; - else - ws_pos_edge <= '0'; - ws_neg_edge <= '0'; - end if; - end if; - end if; - end process WSG; - end generate WSM; - --- Process to detect word select edges, slave mode - WSD : if IS_MASTER = 0 generate - i2s_ws <= i2s_ws_i; - WSDET : process (wb_clk_i) - begin - if rising_edge(wb_clk_i) then - if conf_en = '0' then - ws_pos_edge <= '0'; - ws_neg_edge <= '0'; - zws <= i2s_ws; - zzws <= i2s_ws; - zzzws <= i2s_ws; - else - -- sync i2s_ws_io to our clock domaine - zws <= i2s_ws; - zzws <= zws; - zzzws <= zzws; - -- detect negative edge - if zzzws = '1' and zzws = '0' then - ws_neg_edge <= '1'; - else - ws_neg_edge <= '0'; - end if; - -- detect positive edge - if zzzws = '0' and zzws = '1' then - ws_pos_edge <= '1'; - else - ws_pos_edge <= '0'; - end if; - end if; - end if; - end process WSDET; - end generate WSD; - --- Logic to generate clock signal, master mode - SCKM : if IS_MASTER = 1 generate - i2s_sck_o <= toggle; - end generate SCKM; - --- Process to receive data on i2s_sd_i, or transmit data on i2s_sd_o - sample_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1)); - mem_rdwr <= imem_rdwr; - sample_dat_o <= data_in; - - SDRX : process (wb_clk_i) - begin - if rising_edge(wb_clk_i) then - if conf_en = '0' then -- codec disabled - imem_rdwr <= '0'; - sd_ctrl <= IDLE; - data_in <= (others => '0'); - bit_cnt <= 0; - bits_to_trx <= 0; - new_word <= '0'; - last_bit <= '0'; - adr_cnt <= 0; - evt_lsbf <= '0'; - evt_hsbf <= '0'; - i2s_sd_o <= '0'; - else - case sd_ctrl is - when IDLE => - imem_rdwr <= '0'; - if to_integer(unsigned(conf_res)) > 15 and - to_integer(unsigned(conf_res)) < 33 then - bits_to_trx <= to_integer(unsigned(conf_res)) - 1; - else - bits_to_trx <= 15; - end if; - if conf_en = '1' then - if (ws_pos_edge = '1' and conf_swap = '1') or - (ws_neg_edge = '1' and conf_swap = '0') then - if receiver = '1' then -- recevier - sd_ctrl <= WAIT_CLK; - else - imem_rdwr <= '1'; -- read first data if transmitter - sd_ctrl <= TRX_DATA; - end if; - end if; - end if; - when WAIT_CLK => -- wait for first bit after WS - adr_cnt <= 0; - bit_cnt <= 0; - new_word <= '0'; - last_bit <= '0'; - data_in <= (others => '0'); - if i2s_clk_en = '1' and neg_edge = '0' then - sd_ctrl <= TRX_DATA; - end if; - when TRX_DATA => -- transmit/receive serial data - imem_rdwr <= '0'; - evt_hsbf <= '0'; - evt_lsbf <= '0'; - if master = '0' then - if zzzws /= zzws then - new_word <= '1'; - end if; - else - if ws_pos_edge = '1' or ws_neg_edge = '1' then - new_word <= '1'; - end if; - end if; - if new_word = '1' and i2s_clk_en = '1' and neg_edge = '0' then - last_bit <= '1'; - end if; - -- recevier operation - if receiver = '1' then - if i2s_clk_en = '1' and neg_edge = '1' then - if master = '1' then -- master mode - if bit_cnt < bits_to_trx and new_word = '0' then - bit_cnt <= bit_cnt + 1; - data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; - else - imem_rdwr <= '1'; - data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; - sd_ctrl <= RX_WRITE; - end if; - else -- slave mode - if bit_cnt <= bits_to_trx and new_word = '0' then - bit_cnt <= bit_cnt + 1; - data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; - else - imem_rdwr <= '1'; - sd_ctrl <= RX_WRITE; - end if; - end if; - end if; - end if; - -- transmitter operation - if receiver = '0' then - if master = '1' then -- master mode - if i2s_clk_en = '1' and neg_edge = '0' then - if bit_cnt < bits_to_trx and new_word = '0' then - bit_cnt <= bit_cnt + 1; - i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); - else - bit_cnt <= bit_cnt + 1; - if bit_cnt > bits_to_trx then - i2s_sd_o <= '0'; - else - i2s_sd_o <= sample_dat_i(0); - end if; - -- transmitter address counter - imem_rdwr <= '1'; - adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); - if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then - evt_lsbf <= '1'; - else - evt_lsbf <= '0'; - end if; - if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then - evt_hsbf <= '1'; - else - evt_hsbf <= '0'; - end if; - sd_ctrl <= SYNC; - end if; - end if; - else -- slave mode - if i2s_clk_en = '1' and neg_edge = '1' then - if bit_cnt < bits_to_trx and new_word = '0' then - bit_cnt <= bit_cnt + 1; - i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); - else - bit_cnt <= bit_cnt + 1; - if bit_cnt > bits_to_trx then - i2s_sd_o <= '0'; - else - i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); - end if; - if new_word = '1' then -- transmitter address counter - imem_rdwr <= '1'; - adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); - if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then - evt_lsbf <= '1'; - else - evt_lsbf <= '0'; - end if; - if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then - evt_hsbf <= '1'; - else - evt_hsbf <= '0'; - end if; - sd_ctrl <= SYNC; - end if; - end if; - end if; - end if; - end if; - when RX_WRITE => -- write received word to sample buffer - imem_rdwr <= '0'; - adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); - if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then - evt_lsbf <= '1'; - else - evt_lsbf <= '0'; - end if; - if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then - evt_hsbf <= '1'; - else - evt_hsbf <= '0'; - end if; - sd_ctrl <= SYNC; - when SYNC => -- synchronise with next word - imem_rdwr <= '0'; - evt_hsbf <= '0'; - evt_lsbf <= '0'; - bit_cnt <= 0; - if ws_pos_edge = '1' or ws_neg_edge = '1' then - new_word <= '1'; - end if; - if new_word = '1' and i2s_clk_en = '1' and neg_edge = '0' then - last_bit <= '1'; - end if; - if receiver = '1' then -- receive mode - if master = '1' then - new_word <= '0'; - last_bit <= '0'; - data_in <= (others => '0'); - sd_ctrl <= TRX_DATA; - else - if i2s_clk_en = '1' and neg_edge = '0' and new_word = '1' then - new_word <= '0'; - last_bit <= '0'; - data_in <= (others => '0'); - sd_ctrl <= TRX_DATA; - end if; - end if; - else -- transmit mode - if master = '1' then - new_word <= '0'; - last_bit <= '0'; - data_in <= (others => '0'); - sd_ctrl <= TRX_DATA; - elsif i2s_clk_en = '1' and neg_edge = '0' then - new_word <= '0'; - last_bit <= '0'; - data_in <= (others => '0'); - sd_ctrl <= TRX_DATA; - end if; - end if; - when others => null; - end case; - end if; - end if; - end process SDRX; - -end rtl; Index: trunk/rtl/vhdl/rx_i2s_tops.vhd =================================================================== --- trunk/rtl/vhdl/rx_i2s_tops.vhd (revision 25) +++ trunk/rtl/vhdl/rx_i2s_tops.vhd (nonexistent) @@ -1,276 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S receiver. Top level entity for the receiver core, ---- ----- slave mode. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:29:50 gedra --- Receiver top level, slave mode. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use work.rx_i2s_pack.all; - -entity rx_i2s_tops is - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sd_i : in std_logic; -- I2S data input - i2s_sck_i : in std_logic; -- I2S clock input - i2s_ws_i : in std_logic; -- I2S word select input - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - rx_int_o : out std_logic); -- Interrupt line -end rx_i2s_tops; - -architecture rtl of rx_i2s_tops is - - signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal version_rd : std_logic; - signal config_rd, config_wr, status_rd : std_logic; - signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_rd, intmask_wr : std_logic; - signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_rd, intstat_wr : std_logic; - signal evt_hsbf, evt_lsbf : std_logic; - signal mem_wr, mem_rd : std_logic; - signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0); - signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal conf_res : std_logic_vector(5 downto 0); - signal conf_ratio : std_logic_vector(7 downto 0); - signal conf_rswap, conf_rinten, conf_rxen : std_logic; - signal zero : std_logic; - -begin - --- Data bus or'ing - data_out <= version_dout or config_dout or intmask_dout or intstat_dout - when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout; - --- Wishbone bus cycle decoder - WB : rx_i2s_wbd - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH) - port map ( - wb_clk_i => wb_clk_i, - wb_rst_i => wb_rst_i, - wb_sel_i => wb_sel_i, - wb_stb_i => wb_stb_i, - wb_we_i => wb_we_i, - wb_cyc_i => wb_cyc_i, - wb_bte_i => wb_bte_i, - wb_cti_i => wb_cti_i, - wb_adr_i => wb_adr_i, - data_out => data_out, - wb_ack_o => wb_ack_o, - wb_dat_o => wb_dat_o, - version_rd => version_rd, - config_rd => config_rd, - config_wr => config_wr, - intmask_rd => intmask_rd, - intmask_wr => intmask_wr, - intstat_rd => intstat_rd, - intstat_wr => intstat_wr, - mem_rd => mem_rd, - mem_addr => sbuf_rd_adr); - --- TxVersion - Version register - VER : i2s_version - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 0) - port map ( - ver_rd => version_rd, - ver_dout => version_dout); - --- TxConfig - Configuration register - CG32 : if DATA_WIDTH = 32 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11100000111111111111110000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= config_bits(21 downto 16); - end generate CG32; - CG16 : if DATA_WIDTH = 16 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1110000011111111") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= "010000"; -- 16bit only - end generate CG16; - conf_ratio(7 downto 0) <= config_bits(15 downto 8); - conf_rswap <= config_bits(2); - conf_rinten <= config_bits(1); - conf_rxen <= config_bits(0); - --- TxIntMask - interrupt mask register - IM32 : if DATA_WIDTH = 32 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11000000000000000000000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM32; - IM16 : if DATA_WIDTH = 16 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1100000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM16; - --- TxIntStat - interrupt status register - ISTAT : gen_event_reg - generic map ( - DATA_WIDTH => DATA_WIDTH) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - evt_wr => intstat_wr, - evt_rd => intstat_rd, - evt_din => wb_dat_i, - evt_dout => intstat_dout, - event => intstat_events, - evt_mask => intmask_bits, - evt_en => conf_rinten, - evt_irq => rx_int_o); - intstat_events(0) <= evt_lsbf; -- lower sample buffer empty - intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty - intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); - --- Sample buffer memory - MEM : dpram - generic map ( - DATA_WIDTH => DATA_WIDTH, - RAM_WIDTH => ADDR_WIDTH - 1) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - din => sbuf_din, - wr_en => mem_wr, - rd_en => mem_rd, - wr_addr => sbuf_wr_adr, - rd_addr => sbuf_rd_adr, - dout => sbuf_dout); - --- Receive decoder - zero <= '0'; - zeros <= (others => '0'); - - DEC : i2s_codec - generic map (DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 0, - IS_RECEIVER => 1) - port map ( - wb_clk_i => wb_clk_i, - conf_res => conf_res, - conf_ratio => conf_ratio, - conf_swap => conf_rswap, - conf_en => conf_rxen, - i2s_sd_i => i2s_sd_i, - i2s_sck_i => i2s_sck_i, - i2s_ws_i => i2s_ws_i, - sample_dat_i => zeros, - sample_dat_o => sbuf_din, - mem_rdwr => mem_wr, - sample_addr => sbuf_wr_adr, - evt_hsbf => evt_hsbf, - evt_lsbf => evt_lsbf, - i2s_sd_o => open, - i2s_sck_o => open, - i2s_ws_o => open); - -end rtl; - Index: trunk/rtl/vhdl/tx_i2s_tops.vhd =================================================================== --- trunk/rtl/vhdl/tx_i2s_tops.vhd (revision 25) +++ trunk/rtl/vhdl/tx_i2s_tops.vhd (nonexistent) @@ -1,274 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S transmitter. Top level entity for the transmitter core, ---- ----- slave mode. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:30:28 gedra --- Transmitter top level, slave mode. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use work.tx_i2s_pack.all; - -entity tx_i2s_tops is - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sck_i : in std_logic; - i2s_ws_i : in std_logic; - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - tx_int_o : out std_logic; - i2s_sd_o : out std_logic); -end tx_i2s_tops; - -architecture rtl of tx_i2s_tops is - - signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal version_rd : std_logic; - signal config_rd, config_wr, status_rd : std_logic; - signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_rd, intmask_wr : std_logic; - signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_rd, intstat_wr : std_logic; - signal evt_hsbf, evt_lsbf : std_logic; - signal mem_wr, mem_rd : std_logic; - signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0); - signal sample_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal conf_ratio : std_logic_vector(7 downto 0); - signal conf_res : std_logic_vector(5 downto 0); - signal conf_tswap, conf_tinten, conf_txen : std_logic; - signal zero : std_logic; - -begin - --- Data bus or'ing - data_out <= version_dout or config_dout or intmask_dout or intstat_dout - when wb_adr_i(ADDR_WIDTH - 1) = '0' else (others => '0'); - --- Wishbone bus cycle decoder - WB : tx_i2s_wbd - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH) - port map ( - wb_clk_i => wb_clk_i, - wb_rst_i => wb_rst_i, - wb_sel_i => wb_sel_i, - wb_stb_i => wb_stb_i, - wb_we_i => wb_we_i, - wb_cyc_i => wb_cyc_i, - wb_bte_i => wb_bte_i, - wb_cti_i => wb_cti_i, - wb_adr_i => wb_adr_i, - data_out => data_out, - wb_ack_o => wb_ack_o, - wb_dat_o => wb_dat_o, - version_rd => version_rd, - config_rd => config_rd, - config_wr => config_wr, - intmask_rd => intmask_rd, - intmask_wr => intmask_wr, - intstat_rd => intstat_rd, - intstat_wr => intstat_wr, - mem_wr => mem_wr); - --- TxVersion - Version register - VER : i2s_version - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 0) - port map ( - ver_rd => version_rd, - ver_dout => version_dout); - --- TxConfig - Configuration register - CG32 : if DATA_WIDTH = 32 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11100000111111111111110000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= config_bits(21 downto 16); - end generate CG32; - CG16 : if DATA_WIDTH = 16 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1110000011111111") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= "010000"; -- 16bit only - end generate CG16; - conf_ratio(7 downto 0) <= config_bits(15 downto 8); - conf_tswap <= config_bits(2); - conf_tinten <= config_bits(1); - conf_txen <= config_bits(0); - --- TxIntMask - interrupt mask register - IM32 : if DATA_WIDTH = 32 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11000000000000000000000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM32; - IM16 : if DATA_WIDTH = 16 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1100000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM16; - --- TxIntStat - interrupt status register - ISTAT : gen_event_reg - generic map ( - DATA_WIDTH => DATA_WIDTH) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - evt_wr => intstat_wr, - evt_rd => intstat_rd, - evt_din => wb_dat_i, - evt_dout => intstat_dout, - event => intstat_events, - evt_mask => intmask_bits, - evt_en => conf_tinten, - evt_irq => tx_int_o); - intstat_events(0) <= evt_lsbf; -- lower sample buffer empty - intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty - intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); - --- Sample buffer memory - MEM : dpram - generic map ( - DATA_WIDTH => DATA_WIDTH, - RAM_WIDTH => ADDR_WIDTH - 1) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - din => wb_dat_i(DATA_WIDTH - 1 downto 0), - wr_en => mem_wr, - rd_en => mem_rd, - wr_addr => wb_adr_i(ADDR_WIDTH - 2 downto 0), - rd_addr => sample_addr, - dout => sample_data); - --- Transmit encoder - zero <= '0'; - - ENC : i2s_codec - generic map (DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 0, - IS_RECEIVER => 0) - port map ( - wb_clk_i => wb_clk_i, - conf_res => conf_res, - conf_ratio => conf_ratio, - conf_swap => conf_tswap, - conf_en => conf_txen, - i2s_sd_i => zero, - i2s_sck_i => i2s_sck_i, - i2s_ws_i => i2s_ws_i, - sample_dat_i => sample_data, - sample_dat_o => open, - mem_rdwr => mem_rd, - sample_addr => sample_addr, - evt_hsbf => evt_hsbf, - evt_lsbf => evt_lsbf, - i2s_sd_o => i2s_sd_o, - i2s_sck_o => open, - i2s_ws_o => open); - -end rtl; - Index: trunk/rtl/vhdl/i2s_version.vhd =================================================================== --- trunk/rtl/vhdl/i2s_version.vhd (revision 25) +++ trunk/rtl/vhdl/i2s_version.vhd (nonexistent) @@ -1,89 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S transmitter/receiver version register. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/03 18:49:03 gedra --- Version register. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity i2s_version is - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer); - port ( - ver_rd : in std_logic; -- version register read - ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- reg. contents -end i2s_version; - -architecture rtl of i2s_version is - - signal version : std_logic_vector(DATA_WIDTH - 1 downto 0); - -begin - ver_dout <= version when ver_rd = '1' else (others => '0'); - - -- version vector generation - version(3 downto 0) <= "0001"; -- version 1 - G32 : if DATA_WIDTH = 32 generate - version(4) <= '1'; - version(31 downto 16) <= (others => '0'); - end generate G32; - G16 : if DATA_WIDTH = 16 generate - version(4) <= '0'; - end generate G16; - version(15 downto 13) <= (others => '0'); - version(12 downto 6) <= std_logic_vector(to_unsigned(ADDR_WIDTH, 7)); - version(5) <= '1' when IS_MASTER = 1 else '0'; - -end rtl; Index: trunk/rtl/vhdl/rx_i2s_wbd.vhd =================================================================== --- trunk/rtl/vhdl/rx_i2s_wbd.vhd (revision 25) +++ trunk/rtl/vhdl/rx_i2s_wbd.vhd (nonexistent) @@ -1,218 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S receiver Wishbone bus cycle decoder. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.3 2005/01/17 17:26:47 gedra --- Bugfix of register read/write strobes --- --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/03 18:50:29 gedra --- Receiver Wishbone cycle decoder. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity rx_i2s_wbd is - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - wb_clk_i : in std_logic; -- wishbone clock - wb_rst_i : in std_logic; -- reset signal - wb_sel_i : in std_logic; -- select input - wb_stb_i : in std_logic; -- strobe input - wb_we_i : in std_logic; -- write enable - wb_cyc_i : in std_logic; -- cycle input - wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension - wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address - data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus - wb_ack_o : out std_logic; -- acknowledge - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out - version_rd : out std_logic; -- Version register read - config_rd : out std_logic; -- Config register read - config_wr : out std_logic; -- Config register write - intmask_rd : out std_logic; -- Interrupt mask register read - intmask_wr : out std_logic; -- Interrupt mask register write - intstat_rd : out std_logic; -- Interrupt status register read - intstat_wr : out std_logic; -- Interrupt status register read - mem_rd : out std_logic; -- Sample memory read - mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr. -end rx_i2s_wbd; - -architecture rtl of rx_i2s_wbd is - - constant REG_RXVERSION : std_logic_vector(3 downto 0) := "0000"; - constant REG_RXCONFIG : std_logic_vector(3 downto 0) := "0001"; - constant REG_RXINTMASK : std_logic_vector(3 downto 0) := "0010"; - constant REG_RXINTSTAT : std_logic_vector(3 downto 0) := "0011"; - signal iack, iwr, ird : std_logic; - signal acnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; - signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0); - signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0); - -begin - - wb_ack_o <= iack; - --- acknowledge generation - ACK : process (wb_clk_i, wb_rst_i) - begin - if wb_rst_i = '1' then - iack <= '0'; - elsif rising_edge(wb_clk_i) then - if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then - case wb_cti_i is - when "010" => -- incrementing burst - case wb_bte_i is -- burst extension - when "00" => -- linear burst - iack <= '1'; - when others => -- all other treated assert classic cycle - iack <= not iack; - end case; - when "111" => -- end of burst - iack <= not iack; - when others => -- all other treated assert classic cycle - iack <= not iack; - end case; - else - iack <= '0'; - end if; - end if; - end process ACK; - --- write generation - WR : process (wb_clk_i, wb_rst_i) - begin - if wb_rst_i = '1' then - iwr <= '0'; - elsif rising_edge(wb_clk_i) then - if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and - wb_we_i = '1' then - case wb_cti_i is - when "010" => -- incrementing burst - case wb_bte_i is -- burst extension - when "00" => -- linear burst - iwr <= '1'; - when others => -- all other treated assert classic cycle - iwr <= not iwr; - end case; - when "111" => -- end of burst - iwr <= not iwr; - when others => -- all other treated assert classic cycle - iwr <= not iwr; - end case; - else - iwr <= '0'; - end if; - end if; - end process WR; - --- read generation - ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and - wb_we_i = '0' else '0'; - - wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout; - - DREG : process (wb_clk_i) -- clock data from registers - begin - if rising_edge(wb_clk_i) then - rdout <= data_out; - end if; - end process DREG; - --- sample memory read address. This needs special attention due to read latency - mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when - wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and - wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0); - - all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1'); - - SMA : process (wb_clk_i, wb_rst_i) - begin - if wb_rst_i = '1' then - acnt <= 0; - elsif rising_edge(wb_clk_i) then - if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then - if iack = '0' then - if wb_adr_i = all_ones then - acnt <= 0; - else - acnt <= to_integer(unsigned(wb_adr_i)) + 1; - end if; - else - if acnt < 2**(ADDR_WIDTH - 1) - 1 then - acnt <= acnt + 1; - else - acnt <= 0; - end if; - end if; - end if; - end if; - end process SMA; - --- read and write strobe generation - - version_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXVERSION and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - config_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - config_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and iwr = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and iwr = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and iwr = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0'; - -end rtl; Index: trunk/rtl/vhdl/dpram_rtl.txt =================================================================== --- trunk/rtl/vhdl/dpram_rtl.txt (revision 25) +++ trunk/rtl/vhdl/dpram_rtl.txt (nonexistent) @@ -1,2 +0,0 @@ -The VHDL file dpram_rtl.vhd is reused from the SPDIF interface project. -Fetch the file spdif_interface/rtl/vhdl/dpram_rtl.vhd. Index: trunk/rtl/vhdl/gen_control_reg.txt =================================================================== --- trunk/rtl/vhdl/gen_control_reg.txt (revision 25) +++ trunk/rtl/vhdl/gen_control_reg.txt (nonexistent) @@ -1,2 +0,0 @@ -The VHDL file gen_control_reg.vhd is reused from the SPDIF interface project. -Fetch the file spdif_interface/rtl/vhdl/gen_control_reg.vhd. \ No newline at end of file Index: trunk/rtl/vhdl/tx_i2s_wbd.vhd =================================================================== --- trunk/rtl/vhdl/tx_i2s_wbd.vhd (revision 25) +++ trunk/rtl/vhdl/tx_i2s_wbd.vhd (nonexistent) @@ -1,187 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S transmitter Wishbone bus cycle decoder. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.3 2005/01/17 17:26:49 gedra --- Bugfix of register read/write strobes --- --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/03 18:50:51 gedra --- Transmitter Wishbone cycle decoder. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tx_i2s_wbd is - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - wb_clk_i : in std_logic; -- wishbone clock - wb_rst_i : in std_logic; -- reset signal - wb_sel_i : in std_logic; -- select input - wb_stb_i : in std_logic; -- strobe input - wb_we_i : in std_logic; -- write enable - wb_cyc_i : in std_logic; -- cycle input - wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension - wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address - data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus - wb_ack_o : out std_logic; -- acknowledge - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out - version_rd : out std_logic; -- Version register read - config_rd : out std_logic; -- Config register read - config_wr : out std_logic; -- Config register write - intmask_rd : out std_logic; -- Interrupt mask register read - intmask_wr : out std_logic; -- Interrupt mask register write - intstat_rd : out std_logic; -- Interrupt status register read - intstat_wr : out std_logic; -- Interrupt status register read - mem_wr : out std_logic); -- Sample memory write -end tx_i2s_wbd; - -architecture rtl of tx_i2s_wbd is - - constant REG_TXVERSION : std_logic_vector(3 downto 0) := "0000"; - constant REG_TXCONFIG : std_logic_vector(3 downto 0) := "0001"; - constant REG_TXINTMASK : std_logic_vector(3 downto 0) := "0010"; - constant REG_TXINTSTAT : std_logic_vector(3 downto 0) := "0011"; - signal iack, iwr, ird : std_logic; - signal acnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; - signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0); - -begin - - wb_ack_o <= iack; - --- acknowledge generation - ACK : process (wb_clk_i, wb_rst_i) - begin - if wb_rst_i = '1' then - iack <= '0'; - elsif rising_edge(wb_clk_i) then - if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then - case wb_cti_i is - when "010" => -- incrementing burst - case wb_bte_i is -- burst extension - when "00" => -- linear burst - iack <= '1'; - when others => -- all other treated assert classic cycle - iack <= not iack; - end case; - when "111" => -- end of burst - iack <= not iack; - when others => -- all other treated assert classic cycle - iack <= not iack; - end case; - else - iack <= '0'; - end if; - end if; - end process ACK; - --- write generation - WR : process (wb_clk_i, wb_rst_i) - begin - if wb_rst_i = '1' then - iwr <= '0'; - elsif rising_edge(wb_clk_i) then - if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and - wb_we_i = '1' then - case wb_cti_i is - when "010" => -- incrementing burst - case wb_bte_i is -- burst extension - when "00" => -- linear burst - iwr <= '1'; - when others => -- all other treated as classic cycle - iwr <= not iwr; - end case; - when "111" => -- end of burst - iwr <= not iwr; - when others => -- all other treated as classic cycle - iwr <= not iwr; - end case; - else - iwr <= '0'; - end if; - end if; - end process WR; - --- read generation - ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and - wb_we_i = '0' else '0'; - - wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout; - - DREG : process (wb_clk_i) -- clock data from registers - begin - if rising_edge(wb_clk_i) then - rdout <= data_out; - end if; - end process DREG; - --- read and write strobe generation - - version_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXVERSION and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - config_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - config_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and iwr = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and iwr = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and ird = '1' - and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; - intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1' - else '0'; - mem_wr <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and iwr = '1' else '0'; - -end rtl; Index: trunk/rtl/vhdl/rx_i2s_pack.vhd =================================================================== --- trunk/rtl/vhdl/rx_i2s_pack.vhd (revision 25) +++ trunk/rtl/vhdl/rx_i2s_pack.vhd (nonexistent) @@ -1,166 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S receiver component declarations. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:28:54 gedra --- Receiver component declarations. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; - -package rx_i2s_pack is - --- components used in the receiver - - component gen_control_reg - generic (DATA_WIDTH : integer; - -- note that this vector is (0 to xx), reverse order - ACTIVE_BIT_MASK : std_logic_vector); - port ( - clk : in std_logic; -- clock - rst : in std_logic; -- reset - ctrl_wr : in std_logic; -- control register write - ctrl_rd : in std_logic; -- control register read - ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); - ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); - ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component gen_event_reg - generic (DATA_WIDTH : integer); - port ( - clk : in std_logic; -- clock - rst : in std_logic; -- reset - evt_wr : in std_logic; -- event register write - evt_rd : in std_logic; -- event register read - evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data - event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector - evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask - evt_en : in std_logic; -- irq enable - evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data - evt_irq : out std_logic); -- interrupt request - end component; - - component dpram - generic (DATA_WIDTH : positive; - RAM_WIDTH : positive); - port ( - clk : in std_logic; - rst : in std_logic; -- reset is optional, not used here - din : in std_logic_vector(DATA_WIDTH - 1 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); - rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); - dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component i2s_version - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer); - port ( - ver_rd : in std_logic; -- version register read - ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); - end component; - - component rx_i2s_wbd - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - wb_clk_i : in std_logic; -- wishbone clock - wb_rst_i : in std_logic; -- reset signal - wb_sel_i : in std_logic; -- select input - wb_stb_i : in std_logic; -- strobe input - wb_we_i : in std_logic; -- write enable - wb_cyc_i : in std_logic; -- cycle input - wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension - wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address - data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus - wb_ack_o : out std_logic; -- acknowledge - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out - version_rd : out std_logic; -- Version register read - config_rd : out std_logic; -- Config register read - config_wr : out std_logic; -- Config register write - intmask_rd : out std_logic; -- Interrupt mask register read - intmask_wr : out std_logic; -- Interrupt mask register write - intstat_rd : out std_logic; -- Interrupt status register read - intstat_wr : out std_logic; -- Interrupt status register read - mem_rd : out std_logic; -- Sample memory write - mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr. - end component; - - component i2s_codec - generic (DATA_WIDTH : integer; - ADDR_WIDTH : integer; - IS_MASTER : integer range 0 to 1; - IS_RECEIVER : integer range 0 to 1); - port ( - wb_clk_i : in std_logic; -- wishbone clock - conf_res : in std_logic_vector(5 downto 0); -- sample resolution - conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio - conf_swap : in std_logic; -- left/right sample order - conf_en : in std_logic; -- transmitter/recevier enable - i2s_sd_i : in std_logic; -- I2S serial data input - i2s_sck_i : in std_logic; -- I2S clock input - i2s_ws_i : in std_logic; -- I2S word select input - sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data - mem_rdwr : out std_logic; -- sample buffer read/write - sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address - evt_hsbf : out std_logic; -- higher sample buf empty event - evt_lsbf : out std_logic; -- lower sample buf empty event - i2s_sd_o : out std_logic; -- I2S serial data output - i2s_sck_o : out std_logic; -- I2S clock output - i2s_ws_o : out std_logic); -- I2S word select output - end component; - -end rx_i2s_pack; Index: trunk/rtl/vhdl/gen_event_reg.txt =================================================================== --- trunk/rtl/vhdl/gen_event_reg.txt (revision 25) +++ trunk/rtl/vhdl/gen_event_reg.txt (nonexistent) @@ -1,2 +0,0 @@ -The VHDL file gen_event_reg.vhd is reused from the SPDIF interface project. -Fetch the file spdif_interface/rtl/vhdl/gen_event_reg.vhd. \ No newline at end of file Index: trunk/rtl/vhdl/rx_i2s_topm.vhd =================================================================== --- trunk/rtl/vhdl/rx_i2s_topm.vhd (revision 25) +++ trunk/rtl/vhdl/rx_i2s_topm.vhd (nonexistent) @@ -1,276 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- WISHBONE I2S Interface IP Core ---- ----- ---- ----- This file is part of the I2S Interface project ---- ----- http://www.opencores.org/cores/i2s_interface/ ---- ----- ---- ----- Description ---- ----- I2S receiver. Top level entity for the receiver core, ---- ----- master mode. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2004/08/06 18:55:43 gedra --- De-linting. --- --- Revision 1.1 2004/08/04 14:29:34 gedra --- Receiver top level, master mode. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use work.rx_i2s_pack.all; - -entity rx_i2s_topm is - generic (DATA_WIDTH : integer range 16 to 32; - ADDR_WIDTH : integer range 5 to 32); - port ( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_sel_i : in std_logic; - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_cyc_i : in std_logic; - wb_bte_i : in std_logic_vector(1 downto 0); - wb_cti_i : in std_logic_vector(2 downto 0); - wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); - i2s_sd_i : in std_logic; -- I2S data input - wb_ack_o : out std_logic; - wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); - rx_int_o : out std_logic; -- Interrupt line - i2s_sck_o : out std_logic; -- I2S clock out - i2s_ws_o : out std_logic); -- I2S word select out -end rx_i2s_topm; - -architecture rtl of rx_i2s_topm is - - signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal version_rd : std_logic; - signal config_rd, config_wr, status_rd : std_logic; - signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intmask_rd, intmask_wr : std_logic; - signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal intstat_rd, intstat_wr : std_logic; - signal evt_hsbf, evt_lsbf : std_logic; - signal mem_wr, mem_rd : std_logic; - signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0); - signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal conf_res : std_logic_vector(5 downto 0); - signal conf_ratio : std_logic_vector(7 downto 0); - signal conf_rswap, conf_rinten, conf_rxen : std_logic; - signal zero : std_logic; - -begin - --- Data bus or'ing - data_out <= version_dout or config_dout or intmask_dout or intstat_dout - when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout; - --- Wishbone bus cycle decoder - WB : rx_i2s_wbd - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH) - port map ( - wb_clk_i => wb_clk_i, - wb_rst_i => wb_rst_i, - wb_sel_i => wb_sel_i, - wb_stb_i => wb_stb_i, - wb_we_i => wb_we_i, - wb_cyc_i => wb_cyc_i, - wb_bte_i => wb_bte_i, - wb_cti_i => wb_cti_i, - wb_adr_i => wb_adr_i, - data_out => data_out, - wb_ack_o => wb_ack_o, - wb_dat_o => wb_dat_o, - version_rd => version_rd, - config_rd => config_rd, - config_wr => config_wr, - intmask_rd => intmask_rd, - intmask_wr => intmask_wr, - intstat_rd => intstat_rd, - intstat_wr => intstat_wr, - mem_rd => mem_rd, - mem_addr => sbuf_rd_adr); - --- TxVersion - Version register - VER : i2s_version - generic map ( - DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 1) - port map ( - ver_rd => version_rd, - ver_dout => version_dout); - --- TxConfig - Configuration register - CG32 : if DATA_WIDTH = 32 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11100000111111111111110000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= config_bits(21 downto 16); - end generate CG32; - CG16 : if DATA_WIDTH = 16 generate - CONF : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1110000011111111") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => config_wr, - ctrl_rd => config_rd, - ctrl_din => wb_dat_i, - ctrl_dout => config_dout, - ctrl_bits => config_bits); - conf_res(5 downto 0) <= "010000"; -- 16bit only - end generate CG16; - conf_ratio(7 downto 0) <= config_bits(15 downto 8); - conf_rswap <= config_bits(2); - conf_rinten <= config_bits(1); - conf_rxen <= config_bits(0); - --- TxIntMask - interrupt mask register - IM32 : if DATA_WIDTH = 32 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 32, - ACTIVE_BIT_MASK => "11000000000000000000000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM32; - IM16 : if DATA_WIDTH = 16 generate - IMASK : gen_control_reg - generic map ( - DATA_WIDTH => 16, - ACTIVE_BIT_MASK => "1100000000000000") - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - ctrl_wr => intmask_wr, - ctrl_rd => intmask_rd, - ctrl_din => wb_dat_i, - ctrl_dout => intmask_dout, - ctrl_bits => intmask_bits); - end generate IM16; - --- TxIntStat - interrupt status register - ISTAT : gen_event_reg - generic map ( - DATA_WIDTH => DATA_WIDTH) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - evt_wr => intstat_wr, - evt_rd => intstat_rd, - evt_din => wb_dat_i, - evt_dout => intstat_dout, - event => intstat_events, - evt_mask => intmask_bits, - evt_en => conf_rinten, - evt_irq => rx_int_o); - intstat_events(0) <= evt_lsbf; -- lower sample buffer empty - intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty - intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); - --- Sample buffer memory - MEM : dpram - generic map ( - DATA_WIDTH => DATA_WIDTH, - RAM_WIDTH => ADDR_WIDTH - 1) - port map ( - clk => wb_clk_i, - rst => wb_rst_i, - din => sbuf_din, - wr_en => mem_wr, - rd_en => mem_rd, - wr_addr => sbuf_wr_adr, - rd_addr => sbuf_rd_adr, - dout => sbuf_dout); - --- Receive decoder - zero <= '0'; - zeros <= (others => '0'); - - DEC : i2s_codec - generic map (DATA_WIDTH => DATA_WIDTH, - ADDR_WIDTH => ADDR_WIDTH, - IS_MASTER => 1, - IS_RECEIVER => 1) - port map ( - wb_clk_i => wb_clk_i, - conf_res => conf_res, - conf_ratio => conf_ratio, - conf_swap => conf_rswap, - conf_en => conf_rxen, - i2s_sd_i => i2s_sd_i, - i2s_sck_i => zero, - i2s_ws_i => zero, - sample_dat_i => zeros, - sample_dat_o => sbuf_din, - mem_rdwr => mem_wr, - sample_addr => sbuf_wr_adr, - evt_hsbf => evt_hsbf, - evt_lsbf => evt_lsbf, - i2s_sd_o => open, - i2s_sck_o => i2s_sck_o, - i2s_ws_o => i2s_ws_o); - -end rtl; - Index: i2s_interface/trunk/bench/vhdl/tb_i2s.vhd =================================================================== --- i2s_interface/trunk/bench/vhdl/tb_i2s.vhd (nonexistent) +++ i2s_interface/trunk/bench/vhdl/tb_i2s.vhd (revision 26) @@ -0,0 +1,465 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S top level test bench. Two transmitters and two receivers ---- +---- are instantiated, one each in slave and master mode. ---- +---- Test result is displayed in the log window, there should ---- +---- be no errors. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/07 12:33:29 gedra +-- De-linted. +-- +-- Revision 1.1 2004/08/04 14:31:02 gedra +-- Top level test bench. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wb_tb_pack.all; + +entity tb_i2s is + +end tb_i2s; + +architecture behav of tb_i2s is + + component tx_i2s_topm + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + -- Wishbone interface + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + -- Interrupt line + tx_int_o : out std_logic; + -- I2S signals + i2s_sd_o : out std_logic; + i2s_sck_o : out std_logic; + i2s_ws_o : out std_logic); + end component; + + component tx_i2s_tops + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sck_i : in std_logic; + i2s_ws_i : in std_logic; + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + tx_int_o : out std_logic; + i2s_sd_o : out std_logic); + end component; + + component rx_i2s_topm + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sd_i : in std_logic; -- I2S data input + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rx_int_o : out std_logic; -- Interrupt line + i2s_sck_o : out std_logic; -- I2S clock out + i2s_ws_o : out std_logic); -- I2S word select out + end component; + + component rx_i2s_tops + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sd_i : in std_logic; -- I2S data input + i2s_sck_i : in std_logic; -- I2S clock input + i2s_ws_i : in std_logic; -- I2S word select input + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rx_int_o : out std_logic); -- Interrupt line + end component; + + signal wb_clk_o, wb_rst_o, wb_sel_o, wb_stb_o, wb_we_o : std_logic; + signal wb_cyc_o, wb_ack_i, rx1_int_o : std_logic; + signal tx_int_o, tx1_ack, rx1_ack, tx2_ack, rx2_ack : std_logic; + signal rx2_int_o, tx1_int_o, tx2_int_o : std_logic; + signal wb_bte_o : std_logic_vector(1 downto 0); + signal wb_cti_o : std_logic_vector(2 downto 0); + signal wb_adr_o : std_logic_vector(15 downto 0); + signal wb_dat_i, wb_dat_o, rx1_dat_i : std_logic_vector(31 downto 0); + signal tx1_dat_i, rx2_dat_i, tx2_dat_i : std_logic_vector(31 downto 0); + signal wb_stb_32bit_rx1, wb_stb_32bit_tx1 : std_logic; + signal wb_stb_32bit_rx2, wb_stb_32bit_tx2 : std_logic; + signal i2s_sd1, i2s_sd2, i2s_sck1, i2s_sck2, i2s_ws1, i2s_ws2 : std_logic; + -- register address definitions + constant RX1_VERSION : natural := 16#1000#; + constant RX1_CONFIG : natural := 16#1001#; + constant RX1_INTMASK : natural := 16#1002#; + constant RX1_INTSTAT : natural := 16#1003#; + constant RX1_BUF_BASE : natural := 16#1020#; + constant TX1_VERSION : natural := 16#2000#; + constant TX1_CONFIG : natural := 16#2001#; + constant TX1_INTMASK : natural := 16#2002#; + constant TX1_INTSTAT : natural := 16#2003#; + constant TX1_BUF_BASE : natural := 16#2020#; + constant RX2_VERSION : natural := 16#3000#; + constant RX2_CONFIG : natural := 16#3001#; + constant RX2_INTMASK : natural := 16#3002#; + constant RX2_INTSTAT : natural := 16#3003#; + constant RX2_BUF_BASE : natural := 16#3020#; + constant TX2_VERSION : natural := 16#4000#; + constant TX2_CONFIG : natural := 16#4001#; + constant TX2_INTMASK : natural := 16#4002#; + constant TX2_INTSTAT : natural := 16#4003#; + constant TX2_BUF_BASE : natural := 16#4020#; + +begin + + wb_ack_i <= rx1_ack or tx1_ack or rx2_ack or tx2_ack; + wb_dat_i <= rx1_dat_i when wb_stb_32bit_rx1 = '1' + else tx1_dat_i when wb_stb_32bit_tx1 = '1' + else rx2_dat_i when wb_stb_32bit_rx2 = '1' + else tx2_dat_i when wb_stb_32bit_tx2 = '1' + else (others => '0'); + +-- I2S transmitter 1, slave mode + ITX32S : tx_i2s_tops + generic map (DATA_WIDTH => 32, + ADDR_WIDTH => 6) + port map ( + -- Wishbone interface + wb_clk_i => wb_clk_o, + wb_rst_i => wb_rst_o, + wb_sel_i => wb_sel_o, + wb_stb_i => wb_stb_32bit_tx1, + wb_we_i => wb_we_o, + wb_cyc_i => wb_cyc_o, + wb_bte_i => wb_bte_o, + wb_cti_i => wb_cti_o, + wb_adr_i => wb_adr_o(5 downto 0), + wb_dat_i => wb_dat_o(31 downto 0), + wb_ack_o => tx1_ack, + wb_dat_o => tx1_dat_i, + tx_int_o => tx1_int_o, + i2s_sd_o => i2s_sd1, + i2s_sck_i => i2s_sck1, + i2s_ws_i => i2s_ws1); + +-- I2S transmitter 2, master mode + ITX32M : tx_i2s_topm + generic map (DATA_WIDTH => 32, + ADDR_WIDTH => 6) + port map ( + -- Wishbone interface + wb_clk_i => wb_clk_o, + wb_rst_i => wb_rst_o, + wb_sel_i => wb_sel_o, + wb_stb_i => wb_stb_32bit_tx2, + wb_we_i => wb_we_o, + wb_cyc_i => wb_cyc_o, + wb_bte_i => wb_bte_o, + wb_cti_i => wb_cti_o, + wb_adr_i => wb_adr_o(5 downto 0), + wb_dat_i => wb_dat_o(31 downto 0), + wb_ack_o => tx2_ack, + wb_dat_o => tx2_dat_i, + tx_int_o => tx2_int_o, + i2s_sd_o => i2s_sd2, + i2s_sck_o => i2s_sck2, + i2s_ws_o => i2s_ws2); + +-- I2S receiver 1, master mode + IRX32M : rx_i2s_topm + generic map (DATA_WIDTH => 32, + ADDR_WIDTH => 6) + port map ( + -- Wishbone interface + wb_clk_i => wb_clk_o, + wb_rst_i => wb_rst_o, + wb_sel_i => wb_sel_o, + wb_stb_i => wb_stb_32bit_rx1, + wb_we_i => wb_we_o, + wb_cyc_i => wb_cyc_o, + wb_bte_i => wb_bte_o, + wb_cti_i => wb_cti_o, + wb_adr_i => wb_adr_o(5 downto 0), + wb_dat_i => wb_dat_o(31 downto 0), + i2s_sd_i => i2s_sd1, + wb_ack_o => rx1_ack, + wb_dat_o => rx1_dat_i, + rx_int_o => rx1_int_o, + i2s_sck_o => i2s_sck1, + i2s_ws_o => i2s_ws1); + +-- I2S receiver 2, slave mode + IRX32S : rx_i2s_tops + generic map (DATA_WIDTH => 32, + ADDR_WIDTH => 6) + port map ( + -- Wishbone interface + wb_clk_i => wb_clk_o, + wb_rst_i => wb_rst_o, + wb_sel_i => wb_sel_o, + wb_stb_i => wb_stb_32bit_rx2, + wb_we_i => wb_we_o, + wb_cyc_i => wb_cyc_o, + wb_bte_i => wb_bte_o, + wb_cti_i => wb_cti_o, + wb_adr_i => wb_adr_o(5 downto 0), + wb_dat_i => wb_dat_o(31 downto 0), + i2s_sd_i => i2s_sd2, + i2s_sck_i => i2s_sck2, + i2s_ws_i => i2s_ws2, + wb_ack_o => rx2_ack, + wb_dat_o => rx2_dat_i, + rx_int_o => rx2_int_o); + +-- Main test process + MAIN : process + variable read_32bit : std_logic_vector(31 downto 0); + variable idx : integer; + + -- Make simplified versions of procedures in wb_tb_pack + procedure wb_write_32 ( + constant ADDRESS : in natural; + constant DATA : in natural) is + begin + wb_write(ADDRESS, DATA, wb_adr_o, wb_dat_o(31 downto 0), wb_cyc_o, + wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); + end; + + procedure wb_check_32 ( + constant ADDRESS : in natural; + constant EXP_DATA : in natural) is + begin + wb_check(ADDRESS, EXP_DATA, wb_adr_o, wb_dat_i(31 downto 0), wb_cyc_o, + wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); + end; + + procedure wb_read_32 ( + constant ADDRESS : in natural) is + begin + wb_read(ADDRESS, read_32bit, wb_adr_o, wb_dat_i(31 downto 0), wb_cyc_o, + wb_sel_o, wb_we_o, wb_clk_o, wb_ack_i); + end; + + begin + message("Simulation start with system reset."); + wb_rst_o <= '1'; -- system reset + wb_sel_o <= '0'; + wb_stb_o <= '0'; + wb_sel_o <= '0'; + wb_we_o <= '0'; + wb_cyc_o <= '0'; + wb_bte_o <= "00"; + wb_cti_o <= "000"; + wb_adr_o <= (others => '0'); + wb_dat_o <= (others => '0'); + wait for 200 ns; + wb_rst_o <= '0'; + message("Check receiver version registers:"); + wb_check_32(RX1_VERSION, 16#000001b1#); + wb_check_32(RX2_VERSION, 16#00000191#); + message("Check transmitter version registers:"); + wb_check_32(TX1_VERSION, 16#00000191#); + wb_check_32(TX2_VERSION, 16#000001b1#); + message("Fill up sample buffers with test signal, "); + message("ramp up in left, ramp down in right:"); + SGEN : for i in 0 to 15 loop + wb_write_32(TX1_BUF_BASE + 2*i, (32768 + i*497)*256); -- left + wb_write_32(TX1_BUF_BASE + 2*i + 1, (32767 - i*497)*256); -- right + wb_write_32(TX2_BUF_BASE + 2*i, (32767 - i*497)*16); -- left + wb_write_32(TX2_BUF_BASE + 2*i + 1, (32768 + i*497)*16); --right + end loop; + message("*** Test of master TX and slave RX ***"); + message("Enable transmitter 2:"); + wb_write_32(TX2_INTMASK, 16#00000003#); -- enable interrupts + wb_write_32(TX2_CONFIG, 16#00140703#); -- 20bit resolution + message("Enable recevier 2:"); + wb_write_32(RX2_INTMASK, 16#00000003#); -- enable interrupts + wb_write_32(RX2_CONFIG, 16#00180003#); -- 24bit resolution + wait_for_event("Wait for transmitter 2 LSBF interrupt", 150 us, tx2_int_o); + wait for 1 us; + message("Check for receiver LSBF interrupt:"); + wb_check_32(RX2_INTSTAT, 16#00000001#); + message("Clear transmitter LSBF interrupt:"); + wb_write_32(TX2_INTSTAT, 16#00000001#); + wb_check_32(TX2_INTSTAT, 16#00000000#); + signal_check("tx2_int_o", '0', tx2_int_o); + message("Clear receiver LSBF interrupt:"); + wb_write_32(RX2_INTSTAT, 16#00000001#); + wb_check_32(RX2_INTSTAT, 16#00000000#); + signal_check("rx2_int_o", '0', rx2_int_o); + message("Check received data, lower sample buffer:"); + wb_read_32(RX2_BUF_BASE); + -- calculate which index this word was generated with + idx := (32767 - to_integer(unsigned(read_32bit(31 downto 8)))) / 497; + -- then check for correct values + CHKL : for i in 0 to 7 - idx loop + wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256); + wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256); + end loop; + wait_for_event("Wait for transmitter 2 HSBF interrupt", 150 us, tx2_int_o); + wait for 1 us; + message("Check for receiver LSBF interrupt:"); + wb_check_32(RX2_INTSTAT, 16#00000002#); + message("Clear transmitter HSBF interrupt:"); + wb_write_32(TX2_INTSTAT, 16#00000002#); + wb_check_32(TX2_INTSTAT, 16#00000000#); + signal_check("tx2_int_o", '0', tx2_int_o); + message("Clear receiver HSBF interrupt:"); + wb_write_32(RX2_INTSTAT, 16#00000002#); + wb_check_32(RX2_INTSTAT, 16#00000000#); + signal_check("rx2_int_o", '0', rx2_int_o); + message("Check received data, upper sample buffer:"); + CHKH : for i in 8 - idx to 15 - idx loop + wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256); + wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256); + end loop; + + message("*** Test of slave TX and master RX ***"); + message("Enable transmitter 1:"); + wb_write_32(TX1_INTMASK, 16#00000003#); -- enable interrupts + wb_write_32(TX1_CONFIG, 16#00180007#); -- 24bit resolution + message("Enable recevier 1:"); + wb_write_32(RX1_INTMASK, 16#00000003#); -- enable interrupts + wb_write_32(RX1_CONFIG, 16#00100707#); -- 16bit resolution + wait_for_event("Wait for transmitter 1 LSBF interrupt", 150 us, tx1_int_o); + message("Clear LSBF interrupt:"); + wb_write_32(TX1_INTSTAT, 16#00000001#); + wb_check_32(TX1_INTSTAT, 16#00000000#); + signal_check("tx1_int_o", '0', tx1_int_o); + wait_for_event("Wait for recevier 1 LSBF interrupt", 150 us, rx1_int_o); + message("Clear LSBF interrupt:"); + wb_write_32(RX1_INTSTAT, 16#00000001#); + wb_check_32(RX1_INTSTAT, 16#00000000#); + signal_check("rx1_int_o", '0', rx1_int_o); + message("Check received data (#1), lower sample buffer:"); + wb_read_32(RX1_BUF_BASE); + -- calculate which index this word was generated with + idx := (32767 - to_integer(unsigned(read_32bit(15 downto 0)))) / 497; + -- then check for correct values + CHKL1 : for i in 0 to 7 - idx loop + wb_check_32(RX1_BUF_BASE + 2*i, 32768 + (i+idx)*497); + wb_check_32(RX1_BUF_BASE + 2*i + 1, 32767 - (i+idx)*497); + end loop; + wait_for_event("Wait for transmitter 1 HSBF interrupt", 150 us, tx1_int_o); + message("Clear HSBF interrupt:"); + wb_write_32(TX1_INTSTAT, 16#00000002#); + wb_check_32(TX1_INTSTAT, 16#00000000#); + signal_check("tx1_int_o", '0', tx1_int_o); + wait_for_event("Wait for recevier 1 HSBF interrupt", 150 us, rx1_int_o); + message("Clear HSBF interrupt:"); + wb_write_32(RX1_INTSTAT, 16#00000002#); + wb_check_32(RX1_INTSTAT, 16#00000000#); + signal_check("rx1_int_o", '0', rx1_int_o); + message("Check received data (#1), higher sample buffer:"); + CHKH1 : for i in 8 - idx to 15 - idx loop + wb_check_32(RX1_BUF_BASE + 2*i, 32768 + (i+idx)*497); + wb_check_32(RX1_BUF_BASE + 2*i + 1, 32767 - (i+idx)*497); + end loop; + + sim_report(""); + report "End of simulation! (ignore this failure)" + severity failure; + wait; + end process MAIN; + +-- Bus strobe generator based on address. 32bit recevier mapped to addr. 0x1000 +-- 32bit transmitter mapped to address 0x2000 + wb_stb_32bit_rx1 <= '1' when wb_adr_o(15 downto 12) = "0001" else '0'; + wb_stb_32bit_tx1 <= '1' when wb_adr_o(15 downto 12) = "0010" else '0'; + wb_stb_32bit_rx2 <= '1' when wb_adr_o(15 downto 12) = "0011" else '0'; + wb_stb_32bit_tx2 <= '1' when wb_adr_o(15 downto 12) = "0100" else '0'; + +-- Clock process, 50Mhz Wishbone master freq. + CLKGEN : process + begin + wb_clk_o <= '0'; + wait for 10 ns; + wb_clk_o <= '1'; + wait for 10 ns; + end process CLKGEN; + +end behav; + + + Index: i2s_interface/trunk/bench/vhdl/wb_tb_pack.txt =================================================================== --- i2s_interface/trunk/bench/vhdl/wb_tb_pack.txt (nonexistent) +++ i2s_interface/trunk/bench/vhdl/wb_tb_pack.txt (revision 26) @@ -0,0 +1,2 @@ +The VHDL file wb_tb_pack.vhd is reused from the SPDIF interface project. +Fetch the file spdif_interface/bench/vhdl/wb_tb_pack.vhd. \ No newline at end of file Index: i2s_interface/trunk/rtl/vhdl/i2s_version.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/i2s_version.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/i2s_version.vhd (revision 26) @@ -0,0 +1,89 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S transmitter/receiver version register. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/03 18:49:03 gedra +-- Version register. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2s_version is + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer); + port ( + ver_rd : in std_logic; -- version register read + ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- reg. contents +end i2s_version; + +architecture rtl of i2s_version is + + signal version : std_logic_vector(DATA_WIDTH - 1 downto 0); + +begin + ver_dout <= version when ver_rd = '1' else (others => '0'); + + -- version vector generation + version(3 downto 0) <= "0001"; -- version 1 + G32 : if DATA_WIDTH = 32 generate + version(4) <= '1'; + version(31 downto 16) <= (others => '0'); + end generate G32; + G16 : if DATA_WIDTH = 16 generate + version(4) <= '0'; + end generate G16; + version(15 downto 13) <= (others => '0'); + version(12 downto 6) <= std_logic_vector(to_unsigned(ADDR_WIDTH, 7)); + version(5) <= '1' when IS_MASTER = 1 else '0'; + +end rtl; Index: i2s_interface/trunk/rtl/vhdl/rx_i2s_wbd.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/rx_i2s_wbd.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/rx_i2s_wbd.vhd (revision 26) @@ -0,0 +1,218 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S receiver Wishbone bus cycle decoder. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2005/01/17 17:26:47 gedra +-- Bugfix of register read/write strobes +-- +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/03 18:50:29 gedra +-- Receiver Wishbone cycle decoder. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rx_i2s_wbd is + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + wb_clk_i : in std_logic; -- wishbone clock + wb_rst_i : in std_logic; -- reset signal + wb_sel_i : in std_logic; -- select input + wb_stb_i : in std_logic; -- strobe input + wb_we_i : in std_logic; -- write enable + wb_cyc_i : in std_logic; -- cycle input + wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension + wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o : out std_logic; -- acknowledge + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd : out std_logic; -- Version register read + config_rd : out std_logic; -- Config register read + config_wr : out std_logic; -- Config register write + intmask_rd : out std_logic; -- Interrupt mask register read + intmask_wr : out std_logic; -- Interrupt mask register write + intstat_rd : out std_logic; -- Interrupt status register read + intstat_wr : out std_logic; -- Interrupt status register read + mem_rd : out std_logic; -- Sample memory read + mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr. +end rx_i2s_wbd; + +architecture rtl of rx_i2s_wbd is + + constant REG_RXVERSION : std_logic_vector(3 downto 0) := "0000"; + constant REG_RXCONFIG : std_logic_vector(3 downto 0) := "0001"; + constant REG_RXINTMASK : std_logic_vector(3 downto 0) := "0010"; + constant REG_RXINTSTAT : std_logic_vector(3 downto 0) := "0011"; + signal iack, iwr, ird : std_logic; + signal acnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; + signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0); + signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0); + +begin + + wb_ack_o <= iack; + +-- acknowledge generation + ACK : process (wb_clk_i, wb_rst_i) + begin + if wb_rst_i = '1' then + iack <= '0'; + elsif rising_edge(wb_clk_i) then + if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then + case wb_cti_i is + when "010" => -- incrementing burst + case wb_bte_i is -- burst extension + when "00" => -- linear burst + iack <= '1'; + when others => -- all other treated assert classic cycle + iack <= not iack; + end case; + when "111" => -- end of burst + iack <= not iack; + when others => -- all other treated assert classic cycle + iack <= not iack; + end case; + else + iack <= '0'; + end if; + end if; + end process ACK; + +-- write generation + WR : process (wb_clk_i, wb_rst_i) + begin + if wb_rst_i = '1' then + iwr <= '0'; + elsif rising_edge(wb_clk_i) then + if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and + wb_we_i = '1' then + case wb_cti_i is + when "010" => -- incrementing burst + case wb_bte_i is -- burst extension + when "00" => -- linear burst + iwr <= '1'; + when others => -- all other treated assert classic cycle + iwr <= not iwr; + end case; + when "111" => -- end of burst + iwr <= not iwr; + when others => -- all other treated assert classic cycle + iwr <= not iwr; + end case; + else + iwr <= '0'; + end if; + end if; + end process WR; + +-- read generation + ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and + wb_we_i = '0' else '0'; + + wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout; + + DREG : process (wb_clk_i) -- clock data from registers + begin + if rising_edge(wb_clk_i) then + rdout <= data_out; + end if; + end process DREG; + +-- sample memory read address. This needs special attention due to read latency + mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when + wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and + wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0); + + all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1'); + + SMA : process (wb_clk_i, wb_rst_i) + begin + if wb_rst_i = '1' then + acnt <= 0; + elsif rising_edge(wb_clk_i) then + if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then + if iack = '0' then + if wb_adr_i = all_ones then + acnt <= 0; + else + acnt <= to_integer(unsigned(wb_adr_i)) + 1; + end if; + else + if acnt < 2**(ADDR_WIDTH - 1) - 1 then + acnt <= acnt + 1; + else + acnt <= 0; + end if; + end if; + end if; + end if; + end process SMA; + +-- read and write strobe generation + + version_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXVERSION and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + config_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + config_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and iwr = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and iwr = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and iwr = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0'; + +end rtl; Index: i2s_interface/trunk/rtl/vhdl/rx_i2s_pack.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/rx_i2s_pack.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/rx_i2s_pack.vhd (revision 26) @@ -0,0 +1,166 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S receiver component declarations. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:28:54 gedra +-- Receiver component declarations. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +package rx_i2s_pack is + +-- components used in the receiver + + component gen_control_reg + generic (DATA_WIDTH : integer; + -- note that this vector is (0 to xx), reverse order + ACTIVE_BIT_MASK : std_logic_vector); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + ctrl_wr : in std_logic; -- control register write + ctrl_rd : in std_logic; -- control register read + ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component gen_event_reg + generic (DATA_WIDTH : integer); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + evt_wr : in std_logic; -- event register write + evt_rd : in std_logic; -- event register read + evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data + event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector + evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask + evt_en : in std_logic; -- irq enable + evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data + evt_irq : out std_logic); -- interrupt request + end component; + + component dpram + generic (DATA_WIDTH : positive; + RAM_WIDTH : positive); + port ( + clk : in std_logic; + rst : in std_logic; -- reset is optional, not used here + din : in std_logic_vector(DATA_WIDTH - 1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); + rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); + dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component i2s_version + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer); + port ( + ver_rd : in std_logic; -- version register read + ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component rx_i2s_wbd + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + wb_clk_i : in std_logic; -- wishbone clock + wb_rst_i : in std_logic; -- reset signal + wb_sel_i : in std_logic; -- select input + wb_stb_i : in std_logic; -- strobe input + wb_we_i : in std_logic; -- write enable + wb_cyc_i : in std_logic; -- cycle input + wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension + wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o : out std_logic; -- acknowledge + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd : out std_logic; -- Version register read + config_rd : out std_logic; -- Config register read + config_wr : out std_logic; -- Config register write + intmask_rd : out std_logic; -- Interrupt mask register read + intmask_wr : out std_logic; -- Interrupt mask register write + intstat_rd : out std_logic; -- Interrupt status register read + intstat_wr : out std_logic; -- Interrupt status register read + mem_rd : out std_logic; -- Sample memory write + mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr. + end component; + + component i2s_codec + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer range 0 to 1; + IS_RECEIVER : integer range 0 to 1); + port ( + wb_clk_i : in std_logic; -- wishbone clock + conf_res : in std_logic_vector(5 downto 0); -- sample resolution + conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio + conf_swap : in std_logic; -- left/right sample order + conf_en : in std_logic; -- transmitter/recevier enable + i2s_sd_i : in std_logic; -- I2S serial data input + i2s_sck_i : in std_logic; -- I2S clock input + i2s_ws_i : in std_logic; -- I2S word select input + sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + mem_rdwr : out std_logic; -- sample buffer read/write + sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address + evt_hsbf : out std_logic; -- higher sample buf empty event + evt_lsbf : out std_logic; -- lower sample buf empty event + i2s_sd_o : out std_logic; -- I2S serial data output + i2s_sck_o : out std_logic; -- I2S clock output + i2s_ws_o : out std_logic); -- I2S word select output + end component; + +end rx_i2s_pack; Index: i2s_interface/trunk/rtl/vhdl/tx_i2s_wbd.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/tx_i2s_wbd.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/tx_i2s_wbd.vhd (revision 26) @@ -0,0 +1,187 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S transmitter Wishbone bus cycle decoder. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2005/01/17 17:26:49 gedra +-- Bugfix of register read/write strobes +-- +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/03 18:50:51 gedra +-- Transmitter Wishbone cycle decoder. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tx_i2s_wbd is + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + wb_clk_i : in std_logic; -- wishbone clock + wb_rst_i : in std_logic; -- reset signal + wb_sel_i : in std_logic; -- select input + wb_stb_i : in std_logic; -- strobe input + wb_we_i : in std_logic; -- write enable + wb_cyc_i : in std_logic; -- cycle input + wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension + wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o : out std_logic; -- acknowledge + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd : out std_logic; -- Version register read + config_rd : out std_logic; -- Config register read + config_wr : out std_logic; -- Config register write + intmask_rd : out std_logic; -- Interrupt mask register read + intmask_wr : out std_logic; -- Interrupt mask register write + intstat_rd : out std_logic; -- Interrupt status register read + intstat_wr : out std_logic; -- Interrupt status register read + mem_wr : out std_logic); -- Sample memory write +end tx_i2s_wbd; + +architecture rtl of tx_i2s_wbd is + + constant REG_TXVERSION : std_logic_vector(3 downto 0) := "0000"; + constant REG_TXCONFIG : std_logic_vector(3 downto 0) := "0001"; + constant REG_TXINTMASK : std_logic_vector(3 downto 0) := "0010"; + constant REG_TXINTSTAT : std_logic_vector(3 downto 0) := "0011"; + signal iack, iwr, ird : std_logic; + signal acnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; + signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0); + +begin + + wb_ack_o <= iack; + +-- acknowledge generation + ACK : process (wb_clk_i, wb_rst_i) + begin + if wb_rst_i = '1' then + iack <= '0'; + elsif rising_edge(wb_clk_i) then + if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then + case wb_cti_i is + when "010" => -- incrementing burst + case wb_bte_i is -- burst extension + when "00" => -- linear burst + iack <= '1'; + when others => -- all other treated assert classic cycle + iack <= not iack; + end case; + when "111" => -- end of burst + iack <= not iack; + when others => -- all other treated assert classic cycle + iack <= not iack; + end case; + else + iack <= '0'; + end if; + end if; + end process ACK; + +-- write generation + WR : process (wb_clk_i, wb_rst_i) + begin + if wb_rst_i = '1' then + iwr <= '0'; + elsif rising_edge(wb_clk_i) then + if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and + wb_we_i = '1' then + case wb_cti_i is + when "010" => -- incrementing burst + case wb_bte_i is -- burst extension + when "00" => -- linear burst + iwr <= '1'; + when others => -- all other treated as classic cycle + iwr <= not iwr; + end case; + when "111" => -- end of burst + iwr <= not iwr; + when others => -- all other treated as classic cycle + iwr <= not iwr; + end case; + else + iwr <= '0'; + end if; + end if; + end process WR; + +-- read generation + ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and + wb_we_i = '0' else '0'; + + wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout; + + DREG : process (wb_clk_i) -- clock data from registers + begin + if rising_edge(wb_clk_i) then + rdout <= data_out; + end if; + end process DREG; + +-- read and write strobe generation + + version_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXVERSION and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + config_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + config_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and iwr = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and iwr = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and ird = '1' + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; + intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1' + else '0'; + mem_wr <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and iwr = '1' else '0'; + +end rtl; Index: i2s_interface/trunk/rtl/vhdl/rx_i2s_topm.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/rx_i2s_topm.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/rx_i2s_topm.vhd (revision 26) @@ -0,0 +1,276 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S receiver. Top level entity for the receiver core, ---- +---- master mode. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:29:34 gedra +-- Receiver top level, master mode. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.rx_i2s_pack.all; + +entity rx_i2s_topm is + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sd_i : in std_logic; -- I2S data input + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rx_int_o : out std_logic; -- Interrupt line + i2s_sck_o : out std_logic; -- I2S clock out + i2s_ws_o : out std_logic); -- I2S word select out +end rx_i2s_topm; + +architecture rtl of rx_i2s_topm is + + signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal version_rd : std_logic; + signal config_rd, config_wr, status_rd : std_logic; + signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_rd, intmask_wr : std_logic; + signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_rd, intstat_wr : std_logic; + signal evt_hsbf, evt_lsbf : std_logic; + signal mem_wr, mem_rd : std_logic; + signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0); + signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal conf_res : std_logic_vector(5 downto 0); + signal conf_ratio : std_logic_vector(7 downto 0); + signal conf_rswap, conf_rinten, conf_rxen : std_logic; + signal zero : std_logic; + +begin + +-- Data bus or'ing + data_out <= version_dout or config_dout or intmask_dout or intstat_dout + when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout; + +-- Wishbone bus cycle decoder + WB : rx_i2s_wbd + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH) + port map ( + wb_clk_i => wb_clk_i, + wb_rst_i => wb_rst_i, + wb_sel_i => wb_sel_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + wb_cyc_i => wb_cyc_i, + wb_bte_i => wb_bte_i, + wb_cti_i => wb_cti_i, + wb_adr_i => wb_adr_i, + data_out => data_out, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o, + version_rd => version_rd, + config_rd => config_rd, + config_wr => config_wr, + intmask_rd => intmask_rd, + intmask_wr => intmask_wr, + intstat_rd => intstat_rd, + intstat_wr => intstat_wr, + mem_rd => mem_rd, + mem_addr => sbuf_rd_adr); + +-- TxVersion - Version register + VER : i2s_version + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 1) + port map ( + ver_rd => version_rd, + ver_dout => version_dout); + +-- TxConfig - Configuration register + CG32 : if DATA_WIDTH = 32 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11100000111111111111110000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= config_bits(21 downto 16); + end generate CG32; + CG16 : if DATA_WIDTH = 16 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1110000011111111") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= "010000"; -- 16bit only + end generate CG16; + conf_ratio(7 downto 0) <= config_bits(15 downto 8); + conf_rswap <= config_bits(2); + conf_rinten <= config_bits(1); + conf_rxen <= config_bits(0); + +-- TxIntMask - interrupt mask register + IM32 : if DATA_WIDTH = 32 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11000000000000000000000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM32; + IM16 : if DATA_WIDTH = 16 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1100000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM16; + +-- TxIntStat - interrupt status register + ISTAT : gen_event_reg + generic map ( + DATA_WIDTH => DATA_WIDTH) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + evt_wr => intstat_wr, + evt_rd => intstat_rd, + evt_din => wb_dat_i, + evt_dout => intstat_dout, + event => intstat_events, + evt_mask => intmask_bits, + evt_en => conf_rinten, + evt_irq => rx_int_o); + intstat_events(0) <= evt_lsbf; -- lower sample buffer empty + intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty + intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); + +-- Sample buffer memory + MEM : dpram + generic map ( + DATA_WIDTH => DATA_WIDTH, + RAM_WIDTH => ADDR_WIDTH - 1) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + din => sbuf_din, + wr_en => mem_wr, + rd_en => mem_rd, + wr_addr => sbuf_wr_adr, + rd_addr => sbuf_rd_adr, + dout => sbuf_dout); + +-- Receive decoder + zero <= '0'; + zeros <= (others => '0'); + + DEC : i2s_codec + generic map (DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 1, + IS_RECEIVER => 1) + port map ( + wb_clk_i => wb_clk_i, + conf_res => conf_res, + conf_ratio => conf_ratio, + conf_swap => conf_rswap, + conf_en => conf_rxen, + i2s_sd_i => i2s_sd_i, + i2s_sck_i => zero, + i2s_ws_i => zero, + sample_dat_i => zeros, + sample_dat_o => sbuf_din, + mem_rdwr => mem_wr, + sample_addr => sbuf_wr_adr, + evt_hsbf => evt_hsbf, + evt_lsbf => evt_lsbf, + i2s_sd_o => open, + i2s_sck_o => i2s_sck_o, + i2s_ws_o => i2s_ws_o); + +end rtl; + Index: i2s_interface/trunk/rtl/vhdl/tx_i2s_pack.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/tx_i2s_pack.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/tx_i2s_pack.vhd (revision 26) @@ -0,0 +1,165 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S transmitter component declarations. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:29:10 gedra +-- Transmitter component declarations. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +package tx_i2s_pack is + +-- components used in the transmitter + + component gen_control_reg + generic (DATA_WIDTH : integer; + -- note that this vector is (0 to xx), reverse order + ACTIVE_BIT_MASK : std_logic_vector); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + ctrl_wr : in std_logic; -- control register write + ctrl_rd : in std_logic; -- control register read + ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component gen_event_reg + generic (DATA_WIDTH : integer); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + evt_wr : in std_logic; -- event register write + evt_rd : in std_logic; -- event register read + evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data + event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector + evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask + evt_en : in std_logic; -- irq enable + evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data + evt_irq : out std_logic); -- interrupt request + end component; + + component dpram + generic (DATA_WIDTH : positive; + RAM_WIDTH : positive); + port ( + clk : in std_logic; + rst : in std_logic; -- reset is optional, not used here + din : in std_logic_vector(DATA_WIDTH - 1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); + rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0); + dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component i2s_version + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer); + port ( + ver_rd : in std_logic; -- version register read + ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component tx_i2s_wbd + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + wb_clk_i : in std_logic; -- wishbone clock + wb_rst_i : in std_logic; -- reset signal + wb_sel_i : in std_logic; -- select input + wb_stb_i : in std_logic; -- strobe input + wb_we_i : in std_logic; -- write enable + wb_cyc_i : in std_logic; -- cycle input + wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension + wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o : out std_logic; -- acknowledge + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd : out std_logic; -- Version register read + config_rd : out std_logic; -- Config register read + config_wr : out std_logic; -- Config register write + intmask_rd : out std_logic; -- Interrupt mask register read + intmask_wr : out std_logic; -- Interrupt mask register write + intstat_rd : out std_logic; -- Interrupt status register read + intstat_wr : out std_logic; -- Interrupt status register read + mem_wr : out std_logic); -- Sample memory write + end component; + + component i2s_codec + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer range 0 to 1; + IS_RECEIVER : integer range 0 to 1); + port ( + wb_clk_i : in std_logic; -- wishbone clock + conf_res : in std_logic_vector(5 downto 0); -- sample resolution + conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio + conf_swap : in std_logic; -- left/right sample order + conf_en : in std_logic; -- transmitter/recevier enable + i2s_sd_i : in std_logic; -- I2S serial data input + i2s_sck_i : in std_logic; -- I2S clock input + i2s_ws_i : in std_logic; -- I2S word select input + sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + mem_rdwr : out std_logic; -- sample buffer read/write + sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address + evt_hsbf : out std_logic; -- higher sample buf empty event + evt_lsbf : out std_logic; -- lower sample buf empty event + i2s_sd_o : out std_logic; -- I2S serial data output + i2s_sck_o : out std_logic; -- I2S clock output + i2s_ws_o : out std_logic); -- I2S word select output + end component; + +end tx_i2s_pack; Index: i2s_interface/trunk/rtl/vhdl/tx_i2s_topm.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/tx_i2s_topm.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/tx_i2s_topm.vhd (revision 26) @@ -0,0 +1,277 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S transmitter. Top level entity for the transmitter core, ---- +---- master mode. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:30:14 gedra +-- Transmitter top level, master mode. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.tx_i2s_pack.all; + +entity tx_i2s_topm is + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + -- Wishbone interface + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + -- Interrupt line + tx_int_o : out std_logic; + -- I2S signals + i2s_sd_o : out std_logic; + i2s_sck_o : out std_logic; + i2s_ws_o : out std_logic); +end tx_i2s_topm; + +architecture rtl of tx_i2s_topm is + + signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal version_rd : std_logic; + signal config_rd, config_wr, status_rd : std_logic; + signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_rd, intmask_wr : std_logic; + signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_rd, intstat_wr : std_logic; + signal evt_hsbf, evt_lsbf : std_logic; + signal mem_wr, mem_rd : std_logic; + signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0); + signal sample_data : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal conf_ratio : std_logic_vector(7 downto 0); + signal conf_res : std_logic_vector(5 downto 0); + signal conf_tswap, conf_tinten, conf_txen : std_logic; + signal zero : std_logic; + +begin + +-- Data bus or'ing + data_out <= version_dout or config_dout or intmask_dout or intstat_dout + when wb_adr_i(ADDR_WIDTH - 1) = '0' else (others => '0'); + +-- Wishbone bus cycle decoder + WB : tx_i2s_wbd + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH) + port map ( + wb_clk_i => wb_clk_i, + wb_rst_i => wb_rst_i, + wb_sel_i => wb_sel_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + wb_cyc_i => wb_cyc_i, + wb_bte_i => wb_bte_i, + wb_cti_i => wb_cti_i, + wb_adr_i => wb_adr_i, + data_out => data_out, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o, + version_rd => version_rd, + config_rd => config_rd, + config_wr => config_wr, + intmask_rd => intmask_rd, + intmask_wr => intmask_wr, + intstat_rd => intstat_rd, + intstat_wr => intstat_wr, + mem_wr => mem_wr); + +-- TxVersion - Version register + VER : i2s_version + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 1) + port map ( + ver_rd => version_rd, + ver_dout => version_dout); + +-- TxConfig - Configuration register + CG32 : if DATA_WIDTH = 32 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11100000111111111111110000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= config_bits(21 downto 16); + end generate CG32; + CG16 : if DATA_WIDTH = 16 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1110000011111111") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= "010000"; -- 16bit only + end generate CG16; + conf_ratio(7 downto 0) <= config_bits(15 downto 8); + conf_tswap <= config_bits(2); + conf_tinten <= config_bits(1); + conf_txen <= config_bits(0); + +-- TxIntMask - interrupt mask register + IM32 : if DATA_WIDTH = 32 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11000000000000000000000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM32; + IM16 : if DATA_WIDTH = 16 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1100000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM16; + +-- TxIntStat - interrupt status register + ISTAT : gen_event_reg + generic map ( + DATA_WIDTH => DATA_WIDTH) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + evt_wr => intstat_wr, + evt_rd => intstat_rd, + evt_din => wb_dat_i, + evt_dout => intstat_dout, + event => intstat_events, + evt_mask => intmask_bits, + evt_en => conf_tinten, + evt_irq => tx_int_o); + intstat_events(0) <= evt_lsbf; -- lower sample buffer empty + intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty + intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); + +-- Sample buffer memory + MEM : dpram + generic map ( + DATA_WIDTH => DATA_WIDTH, + RAM_WIDTH => ADDR_WIDTH - 1) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + din => wb_dat_i(DATA_WIDTH - 1 downto 0), + wr_en => mem_wr, + rd_en => mem_rd, + wr_addr => wb_adr_i(ADDR_WIDTH - 2 downto 0), + rd_addr => sample_addr, + dout => sample_data); + +-- Transmit encoder + zero <= '0'; + + ENC : i2s_codec + generic map (DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 1, + IS_RECEIVER => 0) + port map ( + wb_clk_i => wb_clk_i, + conf_res => conf_res, + conf_ratio => conf_ratio, + conf_swap => conf_tswap, + conf_en => conf_txen, + i2s_sd_i => zero, + i2s_sck_i => zero, + i2s_ws_i => zero, + sample_dat_i => sample_data, + sample_dat_o => open, + mem_rdwr => mem_rd, + sample_addr => sample_addr, + evt_hsbf => evt_hsbf, + evt_lsbf => evt_lsbf, + i2s_sd_o => i2s_sd_o, + i2s_sck_o => i2s_sck_o, + i2s_ws_o => i2s_ws_o); + +end rtl; + Index: i2s_interface/trunk/rtl/vhdl/i2s_codec.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/i2s_codec.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/i2s_codec.vhd (revision 26) @@ -0,0 +1,458 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S encoder/decoder. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2005/06/03 17:18:08 gedra +-- BugFix: LSB of transmitted word would be set to zero in slave master mode. (Credit: Julien Dumont) +-- +-- Revision 1.2 2004/08/06 18:55:05 gedra +-- Removed conf_inten, and fixed bug in transmitter master mode. +-- +-- Revision 1.1 2004/08/03 18:49:43 gedra +-- I2S encoder/decoder. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2s_codec is + generic (DATA_WIDTH : integer; + ADDR_WIDTH : integer; + IS_MASTER : integer range 0 to 1; + IS_RECEIVER : integer range 0 to 1); + port ( + wb_clk_i : in std_logic; -- wishbone clock + conf_res : in std_logic_vector(5 downto 0); -- sample resolution + conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio + conf_swap : in std_logic; -- left/right sample order + conf_en : in std_logic; -- transmitter/recevier enable + i2s_sd_i : in std_logic; -- I2S serial data input + i2s_sck_i : in std_logic; -- I2S clock input + i2s_ws_i : in std_logic; -- I2S word select input + sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + mem_rdwr : out std_logic; -- sample buffer read/write + sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address + evt_hsbf : out std_logic; -- higher sample buf empty event + evt_lsbf : out std_logic; -- lower sample buf empty event + i2s_sd_o : out std_logic; -- I2S serial data output + i2s_sck_o : out std_logic; -- I2S clock output + i2s_ws_o : out std_logic); -- I2S word select output +end i2s_codec; + +architecture rtl of i2s_codec is + + signal i2s_clk_en, zsck, zzsck, zzzsck, imem_rd : std_logic; + signal clk_cnt : integer range 0 to 255; + signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; + type srx_states is (IDLE, WAIT_CLK, TRX_DATA, RX_WRITE, SYNC); + signal sd_ctrl : srx_states; + signal bit_cnt, bits_to_trx : integer range 0 to 63; + signal toggle, master, neg_edge, ws_pos_edge, ws_neg_edge : std_logic; + signal data_in : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal zws, zzws, zzzws, i2s_ws, new_word, last_bit : std_logic; + signal imem_rdwr, receiver : std_logic; + signal ws_cnt : integer range 0 to 31; + +begin + +-- Create signals that reflect generics + SGM : if IS_MASTER = 1 generate + master <= '1'; + end generate SGM; + SGS : if IS_MASTER = 0 generate + master <= '0'; + end generate SGS; + SGRX : if IS_RECEIVER = 1 generate + receiver <= '1'; + end generate SGRX; + SGTX : if IS_RECEIVER = 0 generate + receiver <= '0'; + end generate SGTX; + +-- I2S clock enable generation, master mode. The clock is a fraction of the +-- Wishbone bus clock, determined by the conf_ratio value. + CGM : if IS_MASTER = 1 generate + CGEN : process (wb_clk_i) + begin + if rising_edge(wb_clk_i) then + if conf_en = '0' then -- disabled + i2s_clk_en <= '0'; + clk_cnt <= 0; + neg_edge <= '0'; + toggle <= '0'; + else -- enabled + if clk_cnt < to_integer(unsigned(conf_ratio)) + 1 then + clk_cnt <= (clk_cnt + 1) mod 256; + i2s_clk_en <= '0'; + else + clk_cnt <= 0; + i2s_clk_en <= '1'; + neg_edge <= not neg_edge; + end if; + toggle <= neg_edge; + end if; + end if; + end process CGEN; + end generate CGM; + +-- I2S clock enable generation, slave mode. The input clock signal is sampeled +-- and the negative edge is located. + CGS : if IS_MASTER = 0 generate + CGEN : process (wb_clk_i) + begin + if rising_edge(wb_clk_i) then + if conf_en = '0' then -- disabled + i2s_clk_en <= '0'; + zsck <= '0'; + zzsck <= '0'; + zzzsck <= '0'; + toggle <= '0'; + neg_edge <= '0'; + else -- enabled + -- synchronize input clock to Wishbone clock domaine + zsck <= i2s_sck_i; + zzsck <= zsck; + zzzsck <= zzsck; + -- look for edges + if zzzsck = '1' and zzsck = '0' then + i2s_clk_en <= '1'; + neg_edge <= '1'; + elsif zzzsck = '0' and zzsck = '1' then + i2s_clk_en <= '1'; + neg_edge <= '0'; + else + i2s_clk_en <= '0'; + end if; + toggle <= neg_edge; + end if; + end if; + end process CGEN; + end generate CGS; + +-- Process to generate word select signal, master mode + WSM : if IS_MASTER = 1 generate + i2s_ws_o <= i2s_ws; + WSG : process (wb_clk_i) + begin + if rising_edge(wb_clk_i) then + if conf_en = '0' then + i2s_ws <= '0'; + ws_cnt <= 0; + ws_pos_edge <= '0'; + ws_neg_edge <= '0'; + else + if i2s_clk_en = '1' and toggle = '1' then + if ws_cnt < bits_to_trx then + ws_cnt <= ws_cnt + 1; + else + i2s_ws <= not i2s_ws; + ws_cnt <= 0; + if i2s_ws = '1' then + ws_neg_edge <= '1'; + else + ws_pos_edge <= '1'; + end if; + end if; + else + ws_pos_edge <= '0'; + ws_neg_edge <= '0'; + end if; + end if; + end if; + end process WSG; + end generate WSM; + +-- Process to detect word select edges, slave mode + WSD : if IS_MASTER = 0 generate + i2s_ws <= i2s_ws_i; + WSDET : process (wb_clk_i) + begin + if rising_edge(wb_clk_i) then + if conf_en = '0' then + ws_pos_edge <= '0'; + ws_neg_edge <= '0'; + zws <= i2s_ws; + zzws <= i2s_ws; + zzzws <= i2s_ws; + else + -- sync i2s_ws_io to our clock domaine + zws <= i2s_ws; + zzws <= zws; + zzzws <= zzws; + -- detect negative edge + if zzzws = '1' and zzws = '0' then + ws_neg_edge <= '1'; + else + ws_neg_edge <= '0'; + end if; + -- detect positive edge + if zzzws = '0' and zzws = '1' then + ws_pos_edge <= '1'; + else + ws_pos_edge <= '0'; + end if; + end if; + end if; + end process WSDET; + end generate WSD; + +-- Logic to generate clock signal, master mode + SCKM : if IS_MASTER = 1 generate + i2s_sck_o <= toggle; + end generate SCKM; + +-- Process to receive data on i2s_sd_i, or transmit data on i2s_sd_o + sample_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1)); + mem_rdwr <= imem_rdwr; + sample_dat_o <= data_in; + + SDRX : process (wb_clk_i) + begin + if rising_edge(wb_clk_i) then + if conf_en = '0' then -- codec disabled + imem_rdwr <= '0'; + sd_ctrl <= IDLE; + data_in <= (others => '0'); + bit_cnt <= 0; + bits_to_trx <= 0; + new_word <= '0'; + last_bit <= '0'; + adr_cnt <= 0; + evt_lsbf <= '0'; + evt_hsbf <= '0'; + i2s_sd_o <= '0'; + else + case sd_ctrl is + when IDLE => + imem_rdwr <= '0'; + if to_integer(unsigned(conf_res)) > 15 and + to_integer(unsigned(conf_res)) < 33 then + bits_to_trx <= to_integer(unsigned(conf_res)) - 1; + else + bits_to_trx <= 15; + end if; + if conf_en = '1' then + if (ws_pos_edge = '1' and conf_swap = '1') or + (ws_neg_edge = '1' and conf_swap = '0') then + if receiver = '1' then -- recevier + sd_ctrl <= WAIT_CLK; + else + imem_rdwr <= '1'; -- read first data if transmitter + sd_ctrl <= TRX_DATA; + end if; + end if; + end if; + when WAIT_CLK => -- wait for first bit after WS + adr_cnt <= 0; + bit_cnt <= 0; + new_word <= '0'; + last_bit <= '0'; + data_in <= (others => '0'); + if i2s_clk_en = '1' and neg_edge = '0' then + sd_ctrl <= TRX_DATA; + end if; + when TRX_DATA => -- transmit/receive serial data + imem_rdwr <= '0'; + evt_hsbf <= '0'; + evt_lsbf <= '0'; + if master = '0' then + if zzzws /= zzws then + new_word <= '1'; + end if; + else + if ws_pos_edge = '1' or ws_neg_edge = '1' then + new_word <= '1'; + end if; + end if; + if new_word = '1' and i2s_clk_en = '1' and neg_edge = '0' then + last_bit <= '1'; + end if; + -- recevier operation + if receiver = '1' then + if i2s_clk_en = '1' and neg_edge = '1' then + if master = '1' then -- master mode + if bit_cnt < bits_to_trx and new_word = '0' then + bit_cnt <= bit_cnt + 1; + data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; + else + imem_rdwr <= '1'; + data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; + sd_ctrl <= RX_WRITE; + end if; + else -- slave mode + if bit_cnt <= bits_to_trx and new_word = '0' then + bit_cnt <= bit_cnt + 1; + data_in(bits_to_trx - bit_cnt) <= i2s_sd_i; + else + imem_rdwr <= '1'; + sd_ctrl <= RX_WRITE; + end if; + end if; + end if; + end if; + -- transmitter operation + if receiver = '0' then + if master = '1' then -- master mode + if i2s_clk_en = '1' and neg_edge = '0' then + if bit_cnt < bits_to_trx and new_word = '0' then + bit_cnt <= bit_cnt + 1; + i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); + else + bit_cnt <= bit_cnt + 1; + if bit_cnt > bits_to_trx then + i2s_sd_o <= '0'; + else + i2s_sd_o <= sample_dat_i(0); + end if; + -- transmitter address counter + imem_rdwr <= '1'; + adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); + if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then + evt_lsbf <= '1'; + else + evt_lsbf <= '0'; + end if; + if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then + evt_hsbf <= '1'; + else + evt_hsbf <= '0'; + end if; + sd_ctrl <= SYNC; + end if; + end if; + else -- slave mode + if i2s_clk_en = '1' and neg_edge = '1' then + if bit_cnt < bits_to_trx and new_word = '0' then + bit_cnt <= bit_cnt + 1; + i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); + else + bit_cnt <= bit_cnt + 1; + if bit_cnt > bits_to_trx then + i2s_sd_o <= '0'; + else + i2s_sd_o <= sample_dat_i(bits_to_trx - bit_cnt); + end if; + if new_word = '1' then -- transmitter address counter + imem_rdwr <= '1'; + adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); + if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then + evt_lsbf <= '1'; + else + evt_lsbf <= '0'; + end if; + if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then + evt_hsbf <= '1'; + else + evt_hsbf <= '0'; + end if; + sd_ctrl <= SYNC; + end if; + end if; + end if; + end if; + end if; + when RX_WRITE => -- write received word to sample buffer + imem_rdwr <= '0'; + adr_cnt <= (adr_cnt + 1) mod 2**(ADDR_WIDTH - 1); + if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then + evt_lsbf <= '1'; + else + evt_lsbf <= '0'; + end if; + if adr_cnt = 2**(ADDR_WIDTH - 1) - 1 then + evt_hsbf <= '1'; + else + evt_hsbf <= '0'; + end if; + sd_ctrl <= SYNC; + when SYNC => -- synchronise with next word + imem_rdwr <= '0'; + evt_hsbf <= '0'; + evt_lsbf <= '0'; + bit_cnt <= 0; + if ws_pos_edge = '1' or ws_neg_edge = '1' then + new_word <= '1'; + end if; + if new_word = '1' and i2s_clk_en = '1' and neg_edge = '0' then + last_bit <= '1'; + end if; + if receiver = '1' then -- receive mode + if master = '1' then + new_word <= '0'; + last_bit <= '0'; + data_in <= (others => '0'); + sd_ctrl <= TRX_DATA; + else + if i2s_clk_en = '1' and neg_edge = '0' and new_word = '1' then + new_word <= '0'; + last_bit <= '0'; + data_in <= (others => '0'); + sd_ctrl <= TRX_DATA; + end if; + end if; + else -- transmit mode + if master = '1' then + new_word <= '0'; + last_bit <= '0'; + data_in <= (others => '0'); + sd_ctrl <= TRX_DATA; + elsif i2s_clk_en = '1' and neg_edge = '0' then + new_word <= '0'; + last_bit <= '0'; + data_in <= (others => '0'); + sd_ctrl <= TRX_DATA; + end if; + end if; + when others => null; + end case; + end if; + end if; + end process SDRX; + +end rtl; Index: i2s_interface/trunk/rtl/vhdl/rx_i2s_tops.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/rx_i2s_tops.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/rx_i2s_tops.vhd (revision 26) @@ -0,0 +1,276 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S receiver. Top level entity for the receiver core, ---- +---- slave mode. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:29:50 gedra +-- Receiver top level, slave mode. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.rx_i2s_pack.all; + +entity rx_i2s_tops is + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sd_i : in std_logic; -- I2S data input + i2s_sck_i : in std_logic; -- I2S clock input + i2s_ws_i : in std_logic; -- I2S word select input + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rx_int_o : out std_logic); -- Interrupt line +end rx_i2s_tops; + +architecture rtl of rx_i2s_tops is + + signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal version_rd : std_logic; + signal config_rd, config_wr, status_rd : std_logic; + signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_rd, intmask_wr : std_logic; + signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_rd, intstat_wr : std_logic; + signal evt_hsbf, evt_lsbf : std_logic; + signal mem_wr, mem_rd : std_logic; + signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0); + signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal conf_res : std_logic_vector(5 downto 0); + signal conf_ratio : std_logic_vector(7 downto 0); + signal conf_rswap, conf_rinten, conf_rxen : std_logic; + signal zero : std_logic; + +begin + +-- Data bus or'ing + data_out <= version_dout or config_dout or intmask_dout or intstat_dout + when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout; + +-- Wishbone bus cycle decoder + WB : rx_i2s_wbd + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH) + port map ( + wb_clk_i => wb_clk_i, + wb_rst_i => wb_rst_i, + wb_sel_i => wb_sel_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + wb_cyc_i => wb_cyc_i, + wb_bte_i => wb_bte_i, + wb_cti_i => wb_cti_i, + wb_adr_i => wb_adr_i, + data_out => data_out, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o, + version_rd => version_rd, + config_rd => config_rd, + config_wr => config_wr, + intmask_rd => intmask_rd, + intmask_wr => intmask_wr, + intstat_rd => intstat_rd, + intstat_wr => intstat_wr, + mem_rd => mem_rd, + mem_addr => sbuf_rd_adr); + +-- TxVersion - Version register + VER : i2s_version + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 0) + port map ( + ver_rd => version_rd, + ver_dout => version_dout); + +-- TxConfig - Configuration register + CG32 : if DATA_WIDTH = 32 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11100000111111111111110000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= config_bits(21 downto 16); + end generate CG32; + CG16 : if DATA_WIDTH = 16 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1110000011111111") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= "010000"; -- 16bit only + end generate CG16; + conf_ratio(7 downto 0) <= config_bits(15 downto 8); + conf_rswap <= config_bits(2); + conf_rinten <= config_bits(1); + conf_rxen <= config_bits(0); + +-- TxIntMask - interrupt mask register + IM32 : if DATA_WIDTH = 32 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11000000000000000000000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM32; + IM16 : if DATA_WIDTH = 16 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1100000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM16; + +-- TxIntStat - interrupt status register + ISTAT : gen_event_reg + generic map ( + DATA_WIDTH => DATA_WIDTH) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + evt_wr => intstat_wr, + evt_rd => intstat_rd, + evt_din => wb_dat_i, + evt_dout => intstat_dout, + event => intstat_events, + evt_mask => intmask_bits, + evt_en => conf_rinten, + evt_irq => rx_int_o); + intstat_events(0) <= evt_lsbf; -- lower sample buffer empty + intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty + intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); + +-- Sample buffer memory + MEM : dpram + generic map ( + DATA_WIDTH => DATA_WIDTH, + RAM_WIDTH => ADDR_WIDTH - 1) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + din => sbuf_din, + wr_en => mem_wr, + rd_en => mem_rd, + wr_addr => sbuf_wr_adr, + rd_addr => sbuf_rd_adr, + dout => sbuf_dout); + +-- Receive decoder + zero <= '0'; + zeros <= (others => '0'); + + DEC : i2s_codec + generic map (DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 0, + IS_RECEIVER => 1) + port map ( + wb_clk_i => wb_clk_i, + conf_res => conf_res, + conf_ratio => conf_ratio, + conf_swap => conf_rswap, + conf_en => conf_rxen, + i2s_sd_i => i2s_sd_i, + i2s_sck_i => i2s_sck_i, + i2s_ws_i => i2s_ws_i, + sample_dat_i => zeros, + sample_dat_o => sbuf_din, + mem_rdwr => mem_wr, + sample_addr => sbuf_wr_adr, + evt_hsbf => evt_hsbf, + evt_lsbf => evt_lsbf, + i2s_sd_o => open, + i2s_sck_o => open, + i2s_ws_o => open); + +end rtl; + Index: i2s_interface/trunk/rtl/vhdl/tx_i2s_tops.vhd =================================================================== --- i2s_interface/trunk/rtl/vhdl/tx_i2s_tops.vhd (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/tx_i2s_tops.vhd (revision 26) @@ -0,0 +1,274 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE I2S Interface IP Core ---- +---- ---- +---- This file is part of the I2S Interface project ---- +---- http://www.opencores.org/cores/i2s_interface/ ---- +---- ---- +---- Description ---- +---- I2S transmitter. Top level entity for the transmitter core, ---- +---- slave mode. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/08/06 18:55:43 gedra +-- De-linting. +-- +-- Revision 1.1 2004/08/04 14:30:28 gedra +-- Transmitter top level, slave mode. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.tx_i2s_pack.all; + +entity tx_i2s_tops is + generic (DATA_WIDTH : integer range 16 to 32; + ADDR_WIDTH : integer range 5 to 32); + port ( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_sel_i : in std_logic; + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_cyc_i : in std_logic; + wb_bte_i : in std_logic_vector(1 downto 0); + wb_cti_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); + i2s_sck_i : in std_logic; + i2s_ws_i : in std_logic; + wb_ack_o : out std_logic; + wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); + tx_int_o : out std_logic; + i2s_sd_o : out std_logic); +end tx_i2s_tops; + +architecture rtl of tx_i2s_tops is + + signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal version_rd : std_logic; + signal config_rd, config_wr, status_rd : std_logic; + signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intmask_rd, intmask_wr : std_logic; + signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal intstat_rd, intstat_wr : std_logic; + signal evt_hsbf, evt_lsbf : std_logic; + signal mem_wr, mem_rd : std_logic; + signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0); + signal sample_data : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal conf_ratio : std_logic_vector(7 downto 0); + signal conf_res : std_logic_vector(5 downto 0); + signal conf_tswap, conf_tinten, conf_txen : std_logic; + signal zero : std_logic; + +begin + +-- Data bus or'ing + data_out <= version_dout or config_dout or intmask_dout or intstat_dout + when wb_adr_i(ADDR_WIDTH - 1) = '0' else (others => '0'); + +-- Wishbone bus cycle decoder + WB : tx_i2s_wbd + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH) + port map ( + wb_clk_i => wb_clk_i, + wb_rst_i => wb_rst_i, + wb_sel_i => wb_sel_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + wb_cyc_i => wb_cyc_i, + wb_bte_i => wb_bte_i, + wb_cti_i => wb_cti_i, + wb_adr_i => wb_adr_i, + data_out => data_out, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o, + version_rd => version_rd, + config_rd => config_rd, + config_wr => config_wr, + intmask_rd => intmask_rd, + intmask_wr => intmask_wr, + intstat_rd => intstat_rd, + intstat_wr => intstat_wr, + mem_wr => mem_wr); + +-- TxVersion - Version register + VER : i2s_version + generic map ( + DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 0) + port map ( + ver_rd => version_rd, + ver_dout => version_dout); + +-- TxConfig - Configuration register + CG32 : if DATA_WIDTH = 32 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11100000111111111111110000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= config_bits(21 downto 16); + end generate CG32; + CG16 : if DATA_WIDTH = 16 generate + CONF : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1110000011111111") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => config_wr, + ctrl_rd => config_rd, + ctrl_din => wb_dat_i, + ctrl_dout => config_dout, + ctrl_bits => config_bits); + conf_res(5 downto 0) <= "010000"; -- 16bit only + end generate CG16; + conf_ratio(7 downto 0) <= config_bits(15 downto 8); + conf_tswap <= config_bits(2); + conf_tinten <= config_bits(1); + conf_txen <= config_bits(0); + +-- TxIntMask - interrupt mask register + IM32 : if DATA_WIDTH = 32 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 32, + ACTIVE_BIT_MASK => "11000000000000000000000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM32; + IM16 : if DATA_WIDTH = 16 generate + IMASK : gen_control_reg + generic map ( + DATA_WIDTH => 16, + ACTIVE_BIT_MASK => "1100000000000000") + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + ctrl_wr => intmask_wr, + ctrl_rd => intmask_rd, + ctrl_din => wb_dat_i, + ctrl_dout => intmask_dout, + ctrl_bits => intmask_bits); + end generate IM16; + +-- TxIntStat - interrupt status register + ISTAT : gen_event_reg + generic map ( + DATA_WIDTH => DATA_WIDTH) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + evt_wr => intstat_wr, + evt_rd => intstat_rd, + evt_din => wb_dat_i, + evt_dout => intstat_dout, + event => intstat_events, + evt_mask => intmask_bits, + evt_en => conf_tinten, + evt_irq => tx_int_o); + intstat_events(0) <= evt_lsbf; -- lower sample buffer empty + intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty + intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0'); + +-- Sample buffer memory + MEM : dpram + generic map ( + DATA_WIDTH => DATA_WIDTH, + RAM_WIDTH => ADDR_WIDTH - 1) + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + din => wb_dat_i(DATA_WIDTH - 1 downto 0), + wr_en => mem_wr, + rd_en => mem_rd, + wr_addr => wb_adr_i(ADDR_WIDTH - 2 downto 0), + rd_addr => sample_addr, + dout => sample_data); + +-- Transmit encoder + zero <= '0'; + + ENC : i2s_codec + generic map (DATA_WIDTH => DATA_WIDTH, + ADDR_WIDTH => ADDR_WIDTH, + IS_MASTER => 0, + IS_RECEIVER => 0) + port map ( + wb_clk_i => wb_clk_i, + conf_res => conf_res, + conf_ratio => conf_ratio, + conf_swap => conf_tswap, + conf_en => conf_txen, + i2s_sd_i => zero, + i2s_sck_i => i2s_sck_i, + i2s_ws_i => i2s_ws_i, + sample_dat_i => sample_data, + sample_dat_o => open, + mem_rdwr => mem_rd, + sample_addr => sample_addr, + evt_hsbf => evt_hsbf, + evt_lsbf => evt_lsbf, + i2s_sd_o => i2s_sd_o, + i2s_sck_o => open, + i2s_ws_o => open); + +end rtl; + Index: i2s_interface/trunk/rtl/vhdl/dpram_rtl.txt =================================================================== --- i2s_interface/trunk/rtl/vhdl/dpram_rtl.txt (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/dpram_rtl.txt (revision 26) @@ -0,0 +1,2 @@ +The VHDL file dpram_rtl.vhd is reused from the SPDIF interface project. +Fetch the file spdif_interface/rtl/vhdl/dpram_rtl.vhd. Index: i2s_interface/trunk/rtl/vhdl/gen_control_reg.txt =================================================================== --- i2s_interface/trunk/rtl/vhdl/gen_control_reg.txt (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/gen_control_reg.txt (revision 26) @@ -0,0 +1,2 @@ +The VHDL file gen_control_reg.vhd is reused from the SPDIF interface project. +Fetch the file spdif_interface/rtl/vhdl/gen_control_reg.vhd. \ No newline at end of file Index: i2s_interface/trunk/rtl/vhdl/gen_event_reg.txt =================================================================== --- i2s_interface/trunk/rtl/vhdl/gen_event_reg.txt (nonexistent) +++ i2s_interface/trunk/rtl/vhdl/gen_event_reg.txt (revision 26) @@ -0,0 +1,2 @@ +The VHDL file gen_event_reg.vhd is reused from the SPDIF interface project. +Fetch the file spdif_interface/rtl/vhdl/gen_event_reg.vhd. \ No newline at end of file Index: i2s_interface/trunk/doc/i2s.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: i2s_interface/trunk/doc/i2s.pdf =================================================================== --- i2s_interface/trunk/doc/i2s.pdf (nonexistent) +++ i2s_interface/trunk/doc/i2s.pdf (revision 26)

i2s_interface/trunk/doc/i2s.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: i2s_interface/trunk/doc/src/i2s.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: i2s_interface/trunk/doc/src/i2s.doc =================================================================== --- i2s_interface/trunk/doc/src/i2s.doc (nonexistent) +++ i2s_interface/trunk/doc/src/i2s.doc (revision 26)

i2s_interface/trunk/doc/src/i2s.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: i2s_interface/trunk/doc/copying.txt =================================================================== --- i2s_interface/trunk/doc/copying.txt (nonexistent) +++ i2s_interface/trunk/doc/copying.txt (revision 26) @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. Index: i2s_interface/trunk =================================================================== --- i2s_interface/trunk (nonexistent) +++ i2s_interface/trunk (revision 26)

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