URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 25 to Rev 26
- ↔ Reverse comparison
Rev 25 → Rev 26
/oms8051mini/trunk/rtl/8051/oc8051_decoder.v
19,6 → 19,8
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 6th Jan 2017 |
//// 1. pc_next logic added |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
1055,10 → 1057,10
end |
`OC8051_LJMP : begin |
ram_rd_sel = `OC8051_RRS_DC; |
pc_wr = `OC8051_PCW_Y; |
pc_sel = `OC8051_PIS_I16; |
comp_sel = `OC8051_CSS_DC; |
rmw = `OC8051_RMW_N; |
pc_wr = `OC8051_PCW_Y; // Write PC |
pc_sel = `OC8051_PIS_I16; // 16 bit immediate |
comp_sel = `OC8051_CSS_DC; // No Compare |
rmw = `OC8051_RMW_N; // Not Read Modify Command |
stb_i = 1'b0; |
bit_addr = 1'b0; |
end |
1366,33 → 1368,6
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
/* `OC8051_ACALL :begin |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCH; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_AJMP : begin |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_LCALL :begin |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCH; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_N; |
end*/ |
`OC8051_DIV : begin |
ram_wr_sel <= #1 `OC8051_RWS_B; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
/oms8051mini/trunk/rtl/8051/oc8051_memory_interface.v
18,6 → 18,8
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 6th Jan 2017 |
//// 1. pc_next logic added |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
100,6 → 102,7
pc_wr_sel, |
pc_wr, |
pc, |
pc_next, |
rd, |
mem_wait, |
mem_act, |
303,8 → 306,9
|
input pc_wr; |
output [15:0] pc; |
output [15:0] pc_next; |
|
reg [15:0] pc; |
reg [15:0] pc,pc_next; |
|
// |
//pc program counter register, save current value |
833,10 → 837,19
pc <= #1 16'h0; |
else if (pc_wr_r2) |
pc <= #1 pc_buf; |
else if (rd & !int_ack_t) |
else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r) |
pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
end |
|
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
pc_next <= #1 16'h0; |
else if (pc_wr_r2) |
pc_next <= #1 pc_buf; |
else if (rd && !int_ack_t) |
pc_next <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
end |
|
always @(posedge clk or negedge resetn) |
begin |
/oms8051mini/trunk/rtl/8051/oc8051_sp.v
18,6 → 18,8
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 6th Jan 2017 |
//// 1. pc_next logic added |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
63,9 → 65,24
|
|
|
module oc8051_sp (clk, resetn, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w); |
module oc8051_sp ( |
// General I/F |
clk, |
resetn, |
|
ram_rd_sel, |
ram_wr_sel, |
|
// SP Reg Write I/F |
wr_addr, |
wr, |
wr_bit, |
data_in, |
|
sp_out, |
sp_w); |
|
|
input clk, resetn, wr, wr_bit; |
input [2:0] ram_rd_sel, ram_wr_sel; |
input [7:0] data_in, wr_addr; |
/oms8051mini/trunk/rtl/8051/oc8051_top.v
19,6 → 19,8
//// 1. External ROM Interface Removed |
//// v0.1 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.2 - Dinesh A, 6th Jan 2017 |
//// 1. pc_next logic added |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
271,7 → 273,7
|
wire [31:0] idat_onchip; |
|
wire [15:0] pc; |
wire [15:0] pc,pc_next; |
|
assign wbd_cyc_o = wbd_stb_o; |
|
440,7 → 442,7
|
.acc (acc ), |
.ram (ram_out ), |
.pc (pc ), |
.pc (pc_next ), |
.dptr ({dptr_hi, dptr_lo} ), |
.op1 (op1_n ), |
.op2 (op2_n ), |
582,6 → 584,7
.pc_wr_sel (pc_wr_sel ), |
.pc_wr (pc_wr & comp_wait ), |
.pc (pc ), |
.pc_next (pc_next ), |
|
// sfr's |
.sp_w (sp_w ), |