URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
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- This comparison shows the changes necessary to convert path
/
- from Rev 25 to Rev 26
- ↔ Reverse comparison
Rev 25 → Rev 26
/opencpu32/trunk/hdl/opencpu32/ControlUnit.vhd
41,28 → 41,44
--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n |
--! unit applies to data path to implement a sequence of register-transfer level operations. |
architecture Behavioral of ControlUnit is |
|
signal currentCpuState : controlUnitStates; -- CPU states |
signal nextCpuState : controlUnitStates; -- CPU states |
|
signal currentExState : executionStates; -- Execution states |
signal nextExState : executionStates; -- Execution states |
|
signal PC : std_logic_vector(n downto 0); -- Program Counter |
signal IR : std_logic_vector(n downto 0); -- Intruction register |
signal currInstruction : std_logic_vector(n downto 0); -- Current Intruction |
begin |
|
-- Next state logic |
-- Next state logic (CPU, fetch, decode, execute states) |
process (clk, reset) |
begin |
if (reset = '1') then |
currentCpuState <= initial; |
MemoryDataAddr <= (others => '0'); |
currentCpuState <= initial; |
elsif rising_edge(clk) then |
currentCpuState <= nextCpuState; |
end if; |
end process; |
|
-- Next state logic (Execution states) |
process (clk, currentCpuState) |
begin |
if (currentCpuState /= execute) and (currentCpuState /= executing) then |
currentExState <= s0; |
elsif rising_edge(clk) then |
currentExState <= nextExState; |
end if; |
end process; |
|
-- States Fetch, decode, execute from the processor |
process (currentCpuState) |
variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction |
variable opcodeIR : std_logic_vector(5 downto 0); |
begin |
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); |
case currentCpuState is |
-- Initial state left from reset ... |
when initial => |
69,9 → 85,10
cyclesExecute := 0; |
PC <= (others => '0'); |
IR <= (others => '0'); |
MemoryDataRead <= (others => '0'); |
MemoryDataWrite <= (others => '0'); |
MemoryDataAddr <= (others => '0'); |
MemoryDataRead <= '0'; |
MemoryDataWrite <= '0'; |
MemoryDataAddr <= (others => '0'); |
nextCpuState <= fetch; |
|
-- Fetch state (Go to memory and get a instruction) |
89,22 → 106,29
MemoryDataWrite <= '0'; |
|
-- The high attribute points to the highes bit position |
case IR((IR'HIGH) downto (IR'HIGH - 5)) is |
case opcodeIR is |
when mov_reg => |
nextCpuState <= execute; |
cyclesExecute := 2; |
currInstruction <= IR; |
-- Invalid instruction (Now will be ignored, but latter shoud rais a trap |
-- Invalid instruction (Now will be ignored, but latter should raise a trap |
when others => |
end case; |
|
-- Wait while the process that handles the execution works.. |
when execute => |
if cyclesExecute > 1 then |
cyclesExecute := cyclesExecute - 1; |
else |
if cyclesExecute = 0 then |
-- Finish the instruction execution get next |
nextCpuState <= fetch; |
end if; |
else |
nextCpuState <= executing; |
end if; |
|
-- Just wait a cycle and back again to execute state which verify if still need to wait some cycles |
when executing => |
cyclesExecute := cyclesExecute - 1; |
nextCpuState <= execute; |
|
when others => |
null; |
end case; |
111,9 → 135,23
end process; |
|
-- Process that handles the execution of each instruction |
process (currInstruction) |
process (currentExState) |
--variable operando1_reg : std_logic_vector(generalRegisters'range); |
variable opcodeIR : std_logic_vector(5 downto 0); |
begin |
|
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); |
case currentExState is |
when s0 => |
case opcodeIR is |
when mov_reg => |
null; |
when others => |
null; |
end case; |
|
when others => |
null; |
end case; |
end process; |
|
end Behavioral; |
/opencpu32/trunk/hdl/opencpu32/pkgOpenCPU32.vhd
26,6 → 26,7
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15); |
type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu); |
type controlUnitStates is (initial, fetch, decode, execute, executing); |
type executionStates is (s0, s1, s2, s3, s4); |
|
function reg2Num (a: generalRegisters) return integer; |
function Num2reg (a: integer) return generalRegisters; |
32,7 → 33,7
function muxPos( a: dpMuxInputs) return std_logic_vector; |
|
-- Opcodes |
subtype opcodes is std_logic_vector(5 downto 0); |
subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max) |
|
-- Each instruction will take 32 bits |
-- Tutorial on using records.. (http://vhdlguru.blogspot.com.br/2010/02/arrays-and-records-in-vhdl.html) |
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
322,12 → 322,10
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1333475710" xil_pn:in_ck="6198982523794963145" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="4317106340405143849" xil_pn:start_ts="1333475702"> |
<transform xil_pn:end_ts="1333643019" xil_pn:in_ck="6198982523794963145" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="4317106340405143849" xil_pn:start_ts="1333643011"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name=".lso"/> |
<outfile xil_pn:name="ControlUnit.lso"/> |
<outfile xil_pn:name="ControlUnit.ngc"/> |