sgmii/trunk/build/OpenCore_MAC/TECH/altera/New Folder Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I_bb.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I_bb.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I_bb.v (revision 26) @@ -0,0 +1,79 @@ +// megafunction wizard: %ALTDDIO_IN%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altddio_in + +// ============================================================ +// File Name: DDR_I.v +// Megafunction Name(s): +// altddio_in +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module DDR_I ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +// Retrieval info: PRIVATE: CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0" +// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: WIDTH NUMERIC "5" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL datain[4..0] +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL dataout_h[4..0] +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL dataout_l[4..0] +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_mux.cnx =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_mux.cnx (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_mux.cnx (revision 26) @@ -0,0 +1,34 @@ +GENERATION: STANDARD +VERSION: WM1.0 +MODULE: altclkctrl + +PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +PRIVATE: clock_inputs NUMERIC "1" + +CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF" +CONSTANT: clock_type STRING "AUTO" + +USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk" +USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk" + +CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0 +CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0 +CONNECT: @inclk 0 0 3 1 GND 0 0 3 0 +CONNECT: @ena 0 0 0 0 VCC 0 0 0 0 + +SYMBOL: BOX 160 64 4 64 Arial,10 +SYMBOL: LINE 72 47 72 17 SOLID THIN +SYMBOL: LINE 72 47 92 31 SOLID THIN +SYMBOL: LINE 72 17 92 33 SOLID THIN +SYMBOL: LINE 0 64 161 64 +SYMBOL: LINE 161 64 161 -1 +SYMBOL: LINE 0 -1 161 -1 +SYMBOL: LINE 0 64 0 -1 +SYMBOL: TEXT "clk" 74 26 HORIZ Arial,7 +SYMBOL: TEXT "AUTO" 132 3 HORIZ Arial,7 +SYMBOL: PINSTUB 0 32 IN inclk 4 32 "inclk" HORIZ Arial,8 +SYMBOL: LINE 0 32 72 32 SOLID THIN +SYMBOL: PINSTUB 160 32 OUT outclk 129 32 "outclk" HORIZ Arial,8 +SYMBOL: LINE 160 32 91 32 SOLID THIN Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.qip =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.qip (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.qip (revision 26) @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTCLKLOCK" +set_global_assignment -name IP_TOOL_VERSION "9.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"] Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.qip =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.qip (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.qip (revision 26) @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ALTCLKCTRL" +set_global_assignment -name IP_TOOL_VERSION "12.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_buf.v"] Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_bb.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_bb.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_bb.v (revision 26) @@ -0,0 +1,82 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altddio_out + +// ============================================================ +// File Name: DDR_O.v +// Megafunction Name(s): +// altddio_out +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module DDR_O ( + datain_h, + datain_l, + outclock, + dataout); + + input [5:0] datain_h; + input [5:0] datain_l; + input outclock; + output [5:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +// Retrieval info: PRIVATE: CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: OE NUMERIC "0" +// Retrieval info: PRIVATE: OE_REG NUMERIC "0" +// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: WIDTH NUMERIC "6" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL datain_h[5..0] +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL datain_l[5..0] +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL dataout[5..0] +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_O_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v.bak (revision 26) @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:20:11 06/01/2010 +// Design Name: +// Module Name: RGMII2GMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module RGMII2GMII( + input [3:0] RGMII_RxD, + input RGMII_RxCtl, + input RGMII_RxClk, + output reg [7:0] RxD, + output reg RxDV, + output reg RxER, + output RxClk, + input ClkEN, + input rst + ); + + wire [3:0] RxDH; + wire [3:0] RxDL; + wire DV, ER; + reg DV1,ERR1; + reg DV2,ERR2; + wire [7:0] RxD1; + reg [3:0] RxD1H; + reg [3:0] RxD1L; + reg [7:0] RxD2; + + wire [4:0] dataout_h; + wire [4:0] dataout_l; + wire [4:0] datain; + + assign RxClk = RGMII_RxClk; + + DDR_I DDR_I_instance( + .datain(datain), + .inclock(RGMII_RxClk), + .dataout_h(dataout_h), + .dataout_l(dataout_l)); + + assign datain = {RGMII_RxCtl,RGMII_RxD}; + assign RxDL = dataout_h[3:0]; + assign RxDH = dataout_l[3:0]; + assign DV = dataout_h[4]; + assign ER = dataout_l[4]; + + + always@(posedge RGMII_RxClk) + begin + RxD1L<=RxDL; + end + + always@(negedge RGMII_RxClk) + begin + RxD1H<=RxDH; + end + + assign RxD1 = {RxD1H, RxD1L}; + + always@(posedge(RGMII_RxClk)) + begin + RxD2 <= RxD1; + RxD <= RxD2; + end + + always@(posedge(RGMII_RxClk)) + begin + DV1 <= DV; + end + always@(negedge(RGMII_RxClk)) + begin + ERR1<= ER; + end + always@(posedge(RGMII_RxClk)) + begin + ERR2 <= ERR1; + DV2 <= DV1; + RxDV <= DV2; + RxER <= (DV2^ERR2); + end + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp/cbx_args.txt =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp/cbx_args.txt (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp/cbx_args.txt (revision 26) @@ -0,0 +1,9 @@ +ENA_REGISTER_MODE="always enabled" +INTENDED_DEVICE_FAMILY="Arria V" +USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=OFF +clock_type=AUTO +DEVICE_FAMILY="Arria V" +ena +inclk +inclk +outclk Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp (revision 26)

sgmii/trunk/build/OpenCore_MAC/TECH/altera/greybox_tmp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v.bak (revision 26) @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:57:12 06/01/2010 +// Design Name: +// Module Name: GMII2RGMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GMII2RGMII( + input [7:0] TxD, + input TxClk, + input TxEn, + input TxErr, + input TxClk90, + output [3:0] RGMII_TxD, + output RGMII_TxCtl, + output RGMII_TxClk, + input ClkEN, + input rst + ); + + reg [3:0] TxHighNib; + reg [3:0] TxHighNib2; + reg [3:0] TxLowNib; + reg TX_EN1; + wire EN_xor_ERR1; + reg EN_xor_ERR2; + reg EN_xor_ERR3; + + wire DDR_R; + reg DDR_S; + wire DDR_CE; + + wire [5:0] dataout; + wire [5:0] datain_h; + wire [5:0] datain_l; + + + initial + begin + DDR_S <= 0; + end + + assign DDR_CE = ClkEN; + assign DDR_R = rst; + + always@(posedge(TxClk)) + begin + TxLowNib <= TxD[3:0]; + TxHighNib <= TxD[7:4]; + end + + always@(posedge(TxClk)) + begin + TX_EN1 <= TxEn; + EN_xor_ERR2 <= EN_xor_ERR1; + end + + assign EN_xor_ERR1 = TxEn^TxErr; + + assign datain_h = {1'b1,TX_EN1,TxLowNib}; + assign datain_l = {1'b0,EN_xor_ERR2,TxHighNib}; + + DDR_O ODDR_inst( .datain_h (datain_h), + .datain_l (datain_l), + .outclock (TxClk), + .dataout (dataout)); + + assign RGMII_TxD = dataout[3:0]; + assign RGMII_TxCtl = dataout[4]; + assign RGMII_TxClk = TxClk90; + + DDR_O_CLK ODDRCLK_inst( .datain_h (1'b1), + .datain_l (1'b0), + .outclock (TxClk90), + .dataout (RGMII_TxClk)); + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/CLK_DIV2.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/CLK_DIV2.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/CLK_DIV2.v (revision 26) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:41 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/GMII2RGMII.v (revision 26) @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:57:12 06/01/2010 +// Design Name: +// Module Name: GMII2RGMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GMII2RGMII( + input [7:0] TxD, + input TxClk, + input TxEn, + input TxErr, + input TxClk90, + output [3:0] RGMII_TxD, + output RGMII_TxCtl, + output RGMII_TxClk, + input ClkEN, + input rst + ); + + reg [3:0] TxHighNib; + reg [3:0] TxHighNib2; + reg [3:0] TxLowNib; + reg TX_EN1; + wire EN_xor_ERR1; + reg EN_xor_ERR2; + reg EN_xor_ERR3; + + wire DDR_R; + reg DDR_S; + wire DDR_CE; + + wire [5:0] dataout; + wire [5:0] datain_h; + wire [5:0] datain_l; + + + initial + begin + DDR_S <= 0; + end + + assign DDR_CE = ClkEN; + assign DDR_R = rst; + + always@(posedge(TxClk)) + begin + TxLowNib <= TxD[3:0]; + TxHighNib <= TxD[7:4]; + end + + always@(posedge(TxClk)) + begin + TX_EN1 <= TxEn; + EN_xor_ERR2 <= EN_xor_ERR1; + end + + assign EN_xor_ERR1 = TxEn^TxErr; + + assign datain_h = {1'b1,TX_EN1,TxLowNib}; + assign datain_l = {1'b0,EN_xor_ERR2,TxHighNib}; + + DDR_O ODDR_inst( .datain_h (datain_h), + .datain_l (datain_l), + .outclock (TxClk), + .dataout (dataout)); + + assign RGMII_TxD = dataout[3:0]; + assign RGMII_TxCtl = dataout[4]; + + DDR_O_CLK ODDRCLK_inst( .datain_h (1'b1), + .datain_l (1'b0), + .outclock (TxClk90), + .dataout (RGMII_TxClk)); + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/RGMII2GMII.v (revision 26) @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:20:11 06/01/2010 +// Design Name: +// Module Name: RGMII2GMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module RGMII2GMII( + input [3:0] RGMII_RxD, + input RGMII_RxCtl, + input RGMII_RxClk, + output reg [7:0] RxD, + output reg RxDV, + output reg RxER, + output RxClk, + input ClkEN, + input rst + ); + + wire [3:0] RxDH; + wire [3:0] RxDL; + wire DV, ER; + reg DV1,ERR1; + reg DV2,ERR2; + wire [7:0] RxD1; + reg [3:0] RxD1H; + reg [3:0] RxD1L; + reg [7:0] RxD2; + + wire [4:0] dataout_h; + wire [4:0] dataout_l; + wire [4:0] datain; + + assign RxClk = RGMII_RxClk; + + DDR_I DDR_I_instance( + .datain(datain), + .inclock(RGMII_RxClk), + .dataout_h(dataout_h), + .dataout_l(dataout_l)); + + assign datain = {RGMII_RxCtl,RGMII_RxD}; + assign RxDL = dataout_h[3:0]; + assign RxDH = dataout_l[3:0]; + assign DV = dataout_h[4]; + assign ER = dataout_l[4]; + + + always@(posedge RGMII_RxClk) + begin + RxD1L<=RxDL; + end + + always@(negedge RGMII_RxClk) + begin + RxD1H<=RxDH; + end + + assign RxD1 = {RxD1H, RxD1L}; + + always@(posedge(RGMII_RxClk)) + begin + RxD2 <= RxD1; + RxD <= RxD2; + end + + always@(posedge(RGMII_RxClk)) + begin + DV1 <= DV; + end + always@(negedge(RGMII_RxClk)) + begin + ERR1<= ER; + end + always@(posedge(RGMII_RxClk)) + begin + ERR2 <= ERR1; + DV2 <= DV1; + RxDV <= DV2; + RxER <= (DV2^ERR2); + end + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_CLK.ppf =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_CLK.ppf (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_O_CLK.ppf (revision 26) @@ -0,0 +1,11 @@ + + + + + + + + + + + Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/clkgen.v (revision 26) @@ -0,0 +1,377 @@ +// megafunction wizard: %ALTCLKLOCK% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkgen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clkgen ( + inclk0, + c0, + c1, + c2, + c3); + + input inclk0; + output c0; + output c1; + output c2; + output c3; + + wire [6:0] sub_wire0; + wire [0:0] sub_wire7 = 1'h0; + wire [3:3] sub_wire4 = sub_wire0[3:3]; + wire [2:2] sub_wire3 = sub_wire0[2:2]; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire c2 = sub_wire3; + wire c3 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .inclk (sub_wire6), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 1, + altpll_component.clk1_phase_shift = "2000", + altpll_component.clk2_divide_by = 5, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 1, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 5, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 1, + altpll_component.clk3_phase_shift = "10000", + altpll_component.inclk0_input_frequency = 8000, + altpll_component.intended_device_family = "Arria II GX", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NO_COMPENSATION", + altpll_component.pll_type = "Left_Right", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_fbout = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clk6 = "PORT_UNUSED", + altpll_component.port_clk7 = "PORT_UNUSED", + altpll_component.port_clk8 = "PORT_UNUSED", + altpll_component.port_clk9 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.using_fbmimicbidir_port = "OFF", + altpll_component.width_clock = 7; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "301.136" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "2.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "90.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "2000" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "10000" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7" +// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I.qip =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I.qip (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/DDR_I.qip (revision 26) @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_IN" +set_global_assignment -name IP_TOOL_VERSION "9.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DDR_I.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "DDR_I_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "DDR_I.ppf"] Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/clk_buf.v (revision 26) @@ -0,0 +1,129 @@ +// megafunction wizard: %ALTCLKCTRL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altclkctrl + +// ============================================================ +// File Name: clk_buf.v +// Megafunction Name(s): +// altclkctrl +// +// Simulation Library Files(s): +// arriav +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 12.0 Build 263 08/02/2012 SP 2.dp9 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2012 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk +//VERSION_BEGIN 12.0SP2 cbx_altclkbuf 2012:10:19:19:48:16:SJ cbx_cycloneii 2012:10:19:19:48:16:SJ cbx_lpm_add_sub 2012:10:19:19:48:16:SJ cbx_lpm_compare 2012:10:19:19:48:16:SJ cbx_lpm_decode 2012:10:19:19:48:16:SJ cbx_lpm_mux 2012:10:19:19:48:16:SJ cbx_mgl 2012:10:19:19:50:12:SJ cbx_stratix 2012:10:19:19:48:17:SJ cbx_stratixii 2012:10:19:19:48:17:SJ cbx_stratixiii 2012:10:19:19:48:17:SJ cbx_stratixv 2012:10:19:19:48:17:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + +//synthesis_resources = arriav_clkena 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module clk_buf_altclkctrl_7mg + ( + ena, + inclk, + outclk) ; + input ena; + input [3:0] inclk; + output outclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 ena; + tri0 [3:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire wire_sd1_outclk; + wire [1:0] clkselect; + + arriav_clkena sd1 + ( + .ena(ena), + .enaout(), + .inclk(inclk[0]), + .outclk(wire_sd1_outclk)); + defparam + sd1.clock_type = "Auto", + sd1.ena_register_mode = "always enabled", + sd1.lpm_type = "arriav_clkena"; + assign + clkselect = {2{1'b0}}, + outclk = wire_sd1_outclk; +endmodule //clk_buf_altclkctrl_7mg +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_buf ( + inclk, + outclk); + + input inclk; + output outclk; + + wire sub_wire0; + wire sub_wire1 = 1'h1; + wire [2:0] sub_wire4 = 3'h0; + wire outclk = sub_wire0; + wire sub_wire2 = inclk; + wire [3:0] sub_wire3 = {sub_wire4, sub_wire2}; + + clk_buf_altclkctrl_7mg clk_buf_altclkctrl_7mg_component ( + .ena (sub_wire1), + .inclk (sub_wire3), + .outclk (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: clock_inputs NUMERIC "1" +// Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V" +// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF" +// Retrieval info: CONSTANT: clock_type STRING "AUTO" +// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk" +// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk" +// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0 +// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf_bb.v FALSE +// Retrieval info: LIB_FILE: arriav Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera/duram.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera/duram.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera/duram.v (revision 26) @@ -0,0 +1,87 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); //synthesis syn_black_box + +parameter DATA_WIDTH = 32; +parameter ADDR_WIDTH = 5; +parameter BLK_RAM_TYPE = "AUTO"; +parameter DURAM_MODE = "BIDIR_DUAL_PORT"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + + + +altsyncram U_altsyncram ( +.wren_a (wren_a), +.wren_b (wren_b), +.data_a (data_a), +.data_b (data_b), +.address_a (address_a), +.address_b (address_b), +.clock0 (clock_a), +.clock1 (clock_b), +.q_a (q_a), +.q_b (q_b), +// synopsys translate_off +.aclr0 (), +.aclr1 (), +.addressstall_a (), +.addressstall_b (), +.byteena_a (), +.byteena_b (), +.clocken0 (), +.clocken1 (), +.rden_b () +// synopsys translate_on +); + defparam + U_altsyncram.intended_device_family = "Stratix", + U_altsyncram.ram_block_type = BLK_RAM_TYPE, + U_altsyncram.operation_mode = DURAM_MODE, + U_altsyncram.width_a = DATA_WIDTH, + U_altsyncram.widthad_a = ADDR_WIDTH, +// U_altsyncram.numwords_a = 256, + U_altsyncram.width_b = DATA_WIDTH, + U_altsyncram.widthad_b = ADDR_WIDTH, +// U_altsyncram.numwords_b = 256, + U_altsyncram.lpm_type = "altsyncram", + U_altsyncram.width_byteena_a = 1, + U_altsyncram.width_byteena_b = 1, + U_altsyncram.outdata_reg_a = "UNREGISTERED", + U_altsyncram.outdata_aclr_a = "NONE", + U_altsyncram.outdata_reg_b = "UNREGISTERED", + U_altsyncram.indata_aclr_a = "NONE", + U_altsyncram.wrcontrol_aclr_a = "NONE", + U_altsyncram.address_aclr_a = "NONE", + U_altsyncram.indata_reg_b = "CLOCK1", + U_altsyncram.address_reg_b = "CLOCK1", + U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1", + U_altsyncram.indata_aclr_b = "NONE", + U_altsyncram.wrcontrol_aclr_b = "NONE", + U_altsyncram.address_aclr_b = "NONE", + U_altsyncram.outdata_aclr_b = "NONE", + U_altsyncram.power_up_uninitialized = "FALSE"; + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/TECH/altera =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/altera (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/altera (revision 26)

sgmii/trunk/build/OpenCore_MAC/TECH/altera Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_DIV2.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_DIV2.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_DIV2.v (revision 26) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:42 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/GMII2RGMII.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/GMII2RGMII.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/GMII2RGMII.v (revision 26) @@ -0,0 +1,131 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:57:12 06/01/2010 +// Design Name: +// Module Name: GMII2RGMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GMII2RGMII( + input [7:0] TxD, + input TxClk, + input TxEn, + input TxErr, + output [3:0] RGMII_TxD, + output RGMII_TxCtl, + output RGMII_TxClk, + input ClkEN, + input rst + ); + +reg [3:0] TxHighNib; +reg [3:0] TxHighNib2; +reg [3:0] TxLowNib; +reg TX_EN1; +wire EN_xor_ERR1; +reg EN_xor_ERR2; +reg EN_xor_ERR3; + +wire DDR_R; +reg DDR_S; +wire DDR_CE; + + + + initial + begin + DDR_S <= 0; + end + + assign DDR_CE = ClkEN; + assign DDR_R = rst; + + always@(posedge(TxClk)) + begin + TxLowNib <= TxD[3:0]; + end + + always@(negedge(TxClk)) + begin + TxHighNib <= TxD[7:4]; + TxHighNib2 <= TxHighNib; + end + + + genvar I; + generate + for (I=0;I<4;I=I+1) + begin: gen_ddr + // ODDR: Output Double Data Rate Output Register with Set, Reset + // and Clock Enable. + // Virtex-4/5 + // Xilinx HDL Language Template, version 10.1 + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) ODDR_inst ( + .Q(RGMII_TxD[I]), // 1-bit DDR output + .C(TxClk), // 1-bit clock input + .CE(DDR_CE), // 1-bit clock enable input + .D1(TxLowNib[I]), // 1-bit data input (positive edge) + .D2(TxHighNib2[I]), // 1-bit data input (negative edge) + .R(DDR_R), // 1-bit reset + .S(DDR_S) // 1-bit set + ); + end + endgenerate + + always@(posedge(TxClk)) + begin + TX_EN1 <= TxEn; + EN_xor_ERR2 <= EN_xor_ERR1; + end + + always@(negedge(TxClk)) + begin + EN_xor_ERR3 <= EN_xor_ERR2; + end + + assign EN_xor_ERR1 = TxEn^TxErr; + + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) ODDR_inst ( + .Q(RGMII_TxCtl), // 1-bit DDR output + .C(TxClk), // 1-bit clock input + .CE(DDR_CE), // 1-bit clock enable input + .D1(TX_EN1), // 1-bit data input (positive edge) + .D2(EN_xor_ERR3), // 1-bit data input (negative edge) + .R(DDR_R), // 1-bit reset + .S(DDR_S) // 1-bit set + ); + + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) ODDR_clk ( + .Q(RGMII_TxClk), // 1-bit DDR output + .C(TxClk), // 1-bit clock input + .CE(DDR_CE), // 1-bit clock enable input + .D1(1), // 1-bit data input (positive edge) + .D2(0), // 1-bit data input (negative edge) + .R(DDR_R), // 1-bit reset + .S(DDR_S) // 1-bit set + ); +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII2GMII.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII2GMII.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII2GMII.v (revision 26) @@ -0,0 +1,116 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:20:11 06/01/2010 +// Design Name: +// Module Name: RGMII2GMII +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module RGMII2GMII( + input [3:0] RGMII_RxD, + input RGMII_RxCtl, + input RGMII_RxClk, + output reg [7:0] RxD, + output reg RxDV, + output reg RxER, + output RxClk, + input ClkEN, + input rst + ); + +wire [3:0] RxDH; +wire [3:0] RxDL; +wire DV, ER; +reg DV1,ERR1; +reg DV2,ERR2; +wire [7:0] RxD1; +reg [3:0] RxD1H; +reg [3:0] RxD1L; +reg [7:0] RxD2; + + assign RxClk = RGMII_RxClk; + + genvar I; + generate + for(I=0;I<4;I=I+1) + begin: genddr + IDDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE" + // or "SAME_EDGE_PIPELINED" + .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) IDDR_inst ( + .Q1(RxDL[I]), // 1-bit output for positive edge of clock + .Q2(RxDH[I]), // 1-bit output for negative edge of clock + .C(RGMII_RxClk), // 1-bit clock input + .CE(ClkEN), // 1-bit clock enable input + .D(RGMII_RxD[I]), // 1-bit DDR data input + .R(rst), // 1-bit reset + .S(1'b0) // 1-bit set + ); + end + endgenerate + + IDDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE" + // or "SAME_EDGE_PIPELINED" + .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) IDDR_inst ( + .Q1(DV), // 1-bit output for positive edge of clock + .Q2(ER), // 1-bit output for negative edge of clock + .C(RGMII_RxClk), // 1-bit clock input + .CE(ClkEN), // 1-bit clock enable input + .D(RGMII_RxCtl), // 1-bit DDR data input + .R(rst), // 1-bit reset + .S(1'b0) // 1-bit set + ); + + always@(posedge RGMII_RxClk) + begin + RxD1L<=RxDL; + end + + always@(negedge RGMII_RxClk) + begin + RxD1H<=RxDH; + end + + assign RxD1 = {RxD1H, RxD1L}; + + always@(posedge(RGMII_RxClk)) + begin + RxD2 <= RxD1; + RxD <= RxD2; + end + + always@(posedge(RGMII_RxClk)) + begin + DV1 <= DV; + end + always@(negedge(RGMII_RxClk)) + begin + ERR1<= ER; + end + always@(posedge(RGMII_RxClk)) + begin + ERR2 <= ERR1; + DV2 <= DV1; + RxDV <= DV2; + RxER <= (DV2^ERR2); + end +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII_GMII_Adaptation.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII_GMII_Adaptation.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/RGMII_GMII_Adaptation.v (revision 26) @@ -0,0 +1,165 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:19:29 06/01/2010 +// Design Name: +// Module Name: RGMII_GMII_Adaptation +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: This implementation follows the recommendations in XAPP692 of Mary Low +// +////////////////////////////////////////////////////////////////////////////////// +module RGMII_GMII_Adaptation( + input [2:0] Speed, + input RxClkPhase,//0: normal, 1 shift 90deg + input [7:0] TxD, + input TxEN, + input TxER, + input TxClk, + output [7:0] RxD, + output RxDV, + output RxER, + output RxClk, + output RxClk_MAC,//for MAC Rx block which works at half Rx Clock in 100/10 mode and at full Rx clk in 1G mode + output [3:0] RGMII_TxD, + output RGMII_TxCtl, + output RGMII_TxClk, + input [3:0] RGMII_RxD, + input RGMII_RxCtl, + input RGMII_RxClk, + output reg [3:0] Status, + input CE, + input rst + ); + +wire RXDVi,RXERi; +wire [7:0] RXDi; + +reg RxSync_Rst,RxSync_Rst1; +reg TxSync_Rst,TxSync_Rst1; + +reg RxCE, RxCE1; +reg TxCE, TxCE1; + +wire RxClkDiv2; +wire CLK0, CLKFB, CLK_RX, CLK_180, CLK_90; + + assign RxDV = RXDVi; + assign RxER = RXERi; + assign RxD = RXDi; + + + +GMII2RGMII TX_Adapter(.TxD(TxD),.TxClk(TxClk),.TxEn(TxEN),.TxErr(TxER), + .RGMII_TxD(RGMII_TxD),.RGMII_TxCtl(RGMII_TxCtl),.RGMII_TxClk(RGMII_TxClk), + .ClkEN(TxCE),.rst(TxSync_Rst)); + + +RGMII2GMII RX_Adapter(.RGMII_RxD(RGMII_RxD),.RGMII_RxCtl(RGMII_RxCtl),.RGMII_RxClk(CLK_RX), + .RxD(RXDi),.RxDV(RXDVi),.RxER(RXERi),.RxClk(RxClk),.ClkEN(RxCE),.rst(RxSync_Rst)); + + always@(posedge(rst) or posedge(CLK_RX)) + begin + if(rst) + begin + Status <= 4'b0; + end + else + begin + if(~(RXDVi|RXERi)) + begin + Status <= RXDi; + end + end + end + + always@(posedge(CLK_RX)) + begin + if(rst) + RxSync_Rst1 <= 1; + else + RxSync_Rst1 <= 0; + RxSync_Rst <= RxSync_Rst1; + RxCE <= RxCE1; + RxCE1 <= CE; + end + + always@(posedge(TxClk)) + begin + if(rst) + TxSync_Rst1 <= 1; + else + TxSync_Rst1 <= 0; + TxSync_Rst <= TxSync_Rst1; + TxCE <= TxCE1; + TxCE1 <= CE; + end + + //DCM for Receiving Path + DCM_BASE #( + .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(2), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_BASE_inst ( + .CLK0(CLK0), // 0 degree DCM CLK output + .CLK180(CLK_180), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(CLK_90), // 90 degree DCM CLK output + .CLKDV(RxClkDiv2), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .CLKFB(CLKFB), // DCM clock feedback + .CLKIN(RGMII_RxClk), // Clock input (from IBUFG, BUFG or DCM) + .RST(rst) // DCM asynchronous reset input + ); + + BUFG BUFG_inst ( + .O(CLKFB), // Clock buffer output + .I(CLK0) // Clock buffer input + ); + //Use this to have the same amount of delay + BUFGMUX BUFGMUX_inst ( + .O(CLK_RX), // Clock MUX output + .I0(CLK0), // Clock0 input + .I1(CLK_90), // Clock1 input + .S(RxClkPhase) // Clock select input + ); + + // BUFG BUFG_RX_inst ( + // .O(CLK_RX), // Clock buffer output + // .I(CLK_90) // Clock buffer input + // ); + //assign CLK_RX = CLKFB; + BUFGMUX RxClkMux( + .I0(RxClkDiv2), + .I1(CLK0), + .O(RxClk_MAC), + .S(Speed[2])); + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/duram.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/duram.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/duram.v (revision 26) @@ -0,0 +1,60 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); + +parameter DATA_WIDTH = 36; +parameter ADDR_WIDTH = 9; +parameter BLK_RAM_TYPE = "AUTO"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + +wire [35:0] do_b; +wire [35:0] din_a; + +assign din_a =data_a; +assign q_b =do_b; + + +RAMB16_S36_S36 U_RAMB16_S36_S36 ( +.DOA ( ), +.DOB (do_b[31:0] ), +.DOPA ( ), +.DOPB (do_b[35:32] ), +.ADDRA (address_a ), +.ADDRB (address_b ), +.CLKA (clock_a ), +.CLKB (clock_b ), +.DIA (din_a[31:0] ), +.DIB ( ), +.DIPA (din_a[35:32] ), +.DIPB ( ), +.ENA (1'b1 ), +.ENB (1'b1 ), +.SSRA (1'b0 ), +.SSRB (1'b0 ), +.WEA (wren_a ), +.WEB (1'b0 )); + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_SWITCH.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_SWITCH.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx/CLK_SWITCH.v (revision 26) @@ -0,0 +1,74 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:42 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +BUFGMUX U_BUFGMUX ( +.O (OUT ), +.I0 (IN_0 ), +.I1 (IN_1 ), +.S (SW )); + +//assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/TECH/xilinx =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/xilinx (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/xilinx (revision 26)

sgmii/trunk/build/OpenCore_MAC/TECH/xilinx Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/TECH/duram.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/duram.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/duram.v (revision 26) @@ -0,0 +1,87 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); //synthesis syn_black_box + +parameter DATA_WIDTH = 32; +parameter ADDR_WIDTH = 5; +parameter BLK_RAM_TYPE = "AUTO"; +parameter DURAM_MODE = "BIDIR_DUAL_PORT"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + + + +altsyncram U_altsyncram ( +.wren_a (wren_a), +.wren_b (wren_b), +.data_a (data_a), +.data_b (data_b), +.address_a (address_a), +.address_b (address_b), +.clock0 (clock_a), +.clock1 (clock_b), +.q_a (q_a), +.q_b (q_b), +// synopsys translate_off +.aclr0 (), +.aclr1 (), +.addressstall_a (), +.addressstall_b (), +.byteena_a (), +.byteena_b (), +.clocken0 (), +.clocken1 (), +.rden_b () +// synopsys translate_on +); + defparam + U_altsyncram.intended_device_family = "Stratix", + U_altsyncram.ram_block_type = BLK_RAM_TYPE, + U_altsyncram.operation_mode = DURAM_MODE, + U_altsyncram.width_a = DATA_WIDTH, + U_altsyncram.widthad_a = ADDR_WIDTH, +// U_altsyncram.numwords_a = 256, + U_altsyncram.width_b = DATA_WIDTH, + U_altsyncram.widthad_b = ADDR_WIDTH, +// U_altsyncram.numwords_b = 256, + U_altsyncram.lpm_type = "altsyncram", + U_altsyncram.width_byteena_a = 1, + U_altsyncram.width_byteena_b = 1, + U_altsyncram.outdata_reg_a = "UNREGISTERED", + U_altsyncram.outdata_aclr_a = "NONE", + U_altsyncram.outdata_reg_b = "UNREGISTERED", + U_altsyncram.indata_aclr_a = "NONE", + U_altsyncram.wrcontrol_aclr_a = "NONE", + U_altsyncram.address_aclr_a = "NONE", + U_altsyncram.indata_reg_b = "CLOCK1", + U_altsyncram.address_reg_b = "CLOCK1", + U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1", + U_altsyncram.indata_aclr_b = "NONE", + U_altsyncram.wrcontrol_aclr_b = "NONE", + U_altsyncram.address_aclr_b = "NONE", + U_altsyncram.outdata_aclr_b = "NONE", + U_altsyncram.power_up_uninitialized = "FALSE"; + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/TECH/CLK_SWITCH.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH/CLK_SWITCH.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH/CLK_SWITCH.v (revision 26) @@ -0,0 +1,65 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/TECH =================================================================== --- sgmii/trunk/build/OpenCore_MAC/TECH (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/TECH (revision 26)

sgmii/trunk/build/OpenCore_MAC/TECH Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/phy_int_bug.bmp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sgmii/trunk/build/OpenCore_MAC/phy_int_bug.bmp =================================================================== --- sgmii/trunk/build/OpenCore_MAC/phy_int_bug.bmp (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/phy_int_bug.bmp (revision 26)

sgmii/trunk/build/OpenCore_MAC/phy_int_bug.bmp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/MAC_top.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_top.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_top.v (revision 26) @@ -0,0 +1,515 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_top.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// Due to CycloneIV starter board uses SGMII interface +// It's possible to remove the Phy_int module, and use PCS/PMA of Cyclone GxB +// Added Clk_MACTx and remove clock module as not necessary anymore + +module MAC_top( + //system signals +input Reset , +input Clk_user , +input Clk_reg , + + +output [2:0] Speed , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //pkg_lgth fifo +input Pkg_lgth_fifo_rd , +output Pkg_lgth_fifo_ra , +output [15:0] Pkg_lgth_fifo_data , + //Phy interface + //Phy interface +output Gtx_clk_d ,//shifted clock +output Gtx_clk ,//used only in GMII mode +input GMII_Tx_clk , +input GMII_Rx_clk , +input Rx_clk , +input Tx_clk ,//used only in MII mode +output Tx_er , +output Tx_en , +output [7:0] Txd , +input Rx_er , +input Rx_dv , +input [7:0] Rxd , +input Crs , +input Col , + //host interface +input CSB , +input WRB , +input [15:0] CD_in , +output [15:0] CD_out , +input [7:0] CA , + +output [23:0] Monitoring , + //mdx +output Mdo, // MII Management Data Output +output MdoEn, // MII Management Data Output Enable +input Mdi, +output Mdc // MII Management Data Clock + +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //RMON interface +wire [15:0] Rx_pkt_length_rmon ; +wire Rx_apply_rmon ; +wire [2:0] Rx_pkt_err_type_rmon ; +wire [2:0] Rx_pkt_type_rmon ; +wire [2:0] Tx_pkt_type_rmon ; +wire [15:0] Tx_pkt_length_rmon ; +wire Tx_apply_rmon ; +wire [2:0] Tx_pkt_err_type_rmon ; + //PHY interface +wire MCrs_dv ; +wire [7:0] MRxD ; +wire MRxErr ; + //flow_control signals +wire [15:0] pause_quanta ; +wire pause_quanta_val ; + //PHY interface +wire [7:0] MTxD ; +wire MTxEn ; +wire MCRS ; + //interface clk signals +wire MAC_tx_clk ; +wire MAC_rx_clk ; +wire MAC_tx_clk_div ; +wire MAC_rx_clk_div ; + //reg signals +wire [4:0] Tx_Hwmark ; +wire [4:0] Tx_Lwmark ; +wire pause_frame_send_en ; +wire [15:0] pause_quanta_set ; +wire MAC_tx_add_en ; +wire FullDuplex ; +wire [3:0] MaxRetry ; +wire [5:0] IFGset ; +wire [7:0] MAC_tx_add_prom_data ; +wire [2:0] MAC_tx_add_prom_add ; +wire MAC_tx_add_prom_wr ; +wire tx_pause_en ; +wire xoff_cpu ; +wire xon_cpu ; + //Rx host interface +wire MAC_rx_add_chk_en ; +wire [7:0] MAC_rx_add_prom_data ; +wire [2:0] MAC_rx_add_prom_add ; +wire MAC_rx_add_prom_wr ; +wire broadcast_filter_en ; +wire [15:0] broadcast_MAX ; +wire RX_APPEND_CRC ; +wire [4:0] Rx_Hwmark ; +wire [4:0] Rx_Lwmark ; +wire CRC_chk_en ; +wire [5:0] RX_IFG_SET ; +wire [15:0] RX_MAX_LENGTH ; +wire [6:0] RX_MIN_LENGTH ; + //RMON host interface +wire [5:0] CPU_rd_addr ; +wire CPU_rd_apply ; +wire CPU_rd_grant ; +wire [31:0] CPU_rd_dout ; + //Phy int host interface +wire Line_loop_en ; + //MII to CPU +wire [7:0] Divider ; +wire [15:0] CtrlData ; +wire [4:0] Rgad ; +wire [4:0] Fiad ; +wire NoPre ; +wire WCtrlData ; +wire RStat ; +wire ScanStat ; +wire Busy ; +wire LinkFail ; +wire Nvalid ; +wire [15:0] Prsd ; +wire WCtrlDataStart ; +wire RStatStart ; +wire UpdateMIIRX_DATAReg ; +wire [15:0] broadcast_bucket_depth ; +wire [15:0] broadcast_bucket_interval ; +wire Pkg_lgth_fifo_empty; + +reg rx_pkg_lgth_fifo_wr_tmp; +reg rx_pkg_lgth_fifo_wr_tmp_pl1; +reg rx_pkg_lgth_fifo_wr; + +//****************************************************************************** +//internal signals +//****************************************************************************** +MAC_rx U_MAC_rx( +.Monitoring (Monitoring), +.Reset (Reset ), +.Clk_user (Clk_user ), +.Clk (MAC_rx_clk_div ), + //RMII interface (//PHY interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_eop (Rx_mac_eop ), + //CPU (//CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_rx_add_prom_data ), +.MAC_add_prom_add (MAC_rx_add_prom_add ), +.MAC_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON interface (//RMON interface ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ) +); + +MAC_tx U_MAC_tx( +.Reset (Reset ), +.Clk (MAC_tx_clk_div ), +.Clk_user (Clk_user ), + //PHY interface (//PHY interface ), +.TxD (MTxD ), +.TxEn (MTxEn ), +.CRS (MCRS ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //user interface (//user interface ), +.Tx_mac_wa (Tx_mac_wa ), +.Tx_mac_wr (Tx_mac_wr ), +.Tx_mac_data (Tx_mac_data ), +.Tx_mac_BE (Tx_mac_BE ), +.Tx_mac_sop (Tx_mac_sop ), +.Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_add_prom_data (MAC_tx_add_prom_data ), +.MAC_add_prom_add (MAC_tx_add_prom_add ), +.MAC_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //MAC_rx_flow (//MAC_rx_flow ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ) +); + + +assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty; +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr_tmp <=0; + else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100) + rx_pkg_lgth_fifo_wr_tmp <=1; + else + rx_pkg_lgth_fifo_wr_tmp <=0; + +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr_tmp_pl1 <=0; + else + rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp; + +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr <=0; + else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1) + rx_pkg_lgth_fifo_wr <=1; + else + rx_pkg_lgth_fifo_wr <=0; + +afifo U_rx_pkg_lgth_fifo ( +.din (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4), +.wr_en (rx_pkg_lgth_fifo_wr ), +.wr_clk (MAC_rx_clk_div ), +.rd_en (Pkg_lgth_fifo_rd ), +.rd_clk (Clk_user ), +.ainit (Reset ), +.dout (Pkg_lgth_fifo_data ), +.full ( ), +.almost_full ( ), +.empty (Pkg_lgth_fifo_empty ), +.wr_count ( ), +.rd_count ( ), +.rd_ack ( ), +.wr_ack ( )); + + +RMON U_RMON( +.Clk (Clk_reg ), +.Reset (Reset ), + //Tx_RMON (//Tx_RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Tx_RMON (//Tx_RMON ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ) +); + + + +//Instead, tie signals from Tx/Rx statemachine directly to top +assign Tx_er = 1'b0; +assign Tx_en = MTxEn; +assign Txd = MTxD; +assign MRxErr = Rx_er; +assign MCrs_dv= Rx_dv; +assign MRxD = Rxd; + +/* This module is disable */ +//Phy_int U_Phy_int( +//.Reset (Reset ), +//.MAC_rx_clk (MAC_rx_clk ), +//.MAC_tx_clk (MAC_tx_clk ), +// //Rx interface (//Rx interface ), +//.MCrs_dv (MCrs_dv ), +//.MRxD (MRxD ), +//.MRxErr (MRxErr ), +// //Tx interface (//Tx interface ), +//.MTxD (MTxD ), +//.MTxEn (MTxEn ), +//.MCRS (MCRS ), +// //Phy interface (//Phy interface ), +//.Tx_er (Tx_er ), +//.Tx_en (Tx_en ), +//.Txd (Txd ), +//.Rx_er (Rx_er ), +//.Rx_dv (Rx_dv ), +//.Rxd (Rxd ), +//.Crs (Crs ), +//.Col (Col ), +// //host interface (//host interface ), +//.Line_loop_en (Line_loop_en ), +//.Speed (Speed ) +//); + + assign MAC_tx_clk_div = GMII_Tx_clk; + assign MAC_rx_clk_div = GMII_Rx_clk; + + +/* This block is no longer necessary */ +/* +Clk_ctrl U_Clk_ctrl( +.Reset (Reset ), +.Clk_125M (Clk_125M ), +.Clk_25M (Clk_25M), +.Clk_125M_90 (Clk_125M_90), +.Clk_25M_90 (Clk_25M_90), + //host interface (//host interface ), +.Speed (Speed ), + //Phy interface (//Phy interface ), +.Gtx_clk (Gtx_clk ), +.Rx_clk (Rx_clk ), +//.Tx_clk (Tx_clk ), + //interface clk (//interface clk ), +.MAC_tx_clk_d (Gtx_clk_d), +.MAC_tx_clk (MAC_tx_clk ), +.MAC_rx_clk (MAC_rx_clk ), +.MAC_tx_clk_div (MAC_tx_clk_div ), +.MAC_rx_clk_div (MAC_rx_clk_div) +);*/ + +eth_miim U_eth_miim( +.Clk (Clk_reg ), +.Reset (Reset ), +.Divider (Divider ), +.NoPre (NoPre ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Mdo (Mdo ), +.MdoEn (MdoEn ), +.Mdi (Mdi ), +.Mdc (Mdc ), +.Busy (Busy ), +.Prsd (Prsd ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )); + +Reg_int U_Reg_int( +.Reset (Reset ), +.Clk_reg (Clk_reg ), +.CSB (CSB ), +.WRB (WRB ), +.CD_in (CD_in ), +.CD_out (CD_out ), +.CA (CA ), + //Tx host interface (//Tx host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_tx_add_prom_data (MAC_tx_add_prom_data ), +.MAC_tx_add_prom_add (MAC_tx_add_prom_add ), +.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //Rx host interface (//Rx host interface ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_rx_add_prom_data (MAC_rx_add_prom_data ), +.MAC_rx_add_prom_add (MAC_rx_add_prom_add ), +.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON host interface (//RMON host interface ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ), + //Phy int host interface (//Phy int host interface ), +.Line_loop_en (Line_loop_en ), +.Speed (Speed ), + //MII to CPU (//MII to CPU ), +.Divider (Divider ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.NoPre (NoPre ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Busy (Busy ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.Prsd (Prsd ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ) +); + +endmodule + + + + + + + + + + + + + + + + + Index: sgmii/trunk/build/OpenCore_MAC/reg_int.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/reg_int.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/reg_int.v.bak (revision 26) @@ -0,0 +1,178 @@ +module Reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/header.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/header.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/header.v.bak (revision 26) @@ -0,0 +1,5 @@ + `define MAC_SOURCE_REPLACE_EN 1 + `define MAC_TARGET_CHECK_EN 1 + `define MAC_BROADCAST_FILTER_EN 1 +`define MAC_TX_FF_DEPTH 11 +`define MAC_RX_FF_DEPTH 11 Index: sgmii/trunk/build/OpenCore_MAC/reg_int.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/reg_int.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/reg_int.v (revision 26) @@ -0,0 +1,178 @@ +module Reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0020,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/header.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/header.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/header.v (revision 26) @@ -0,0 +1,5 @@ + `define MAC_SOURCE_REPLACE_EN 1 + `define MAC_TARGET_CHECK_EN 1 + `define MAC_BROADCAST_FILTER_EN 1 +`define MAC_TX_FF_DEPTH 10 +`define MAC_RX_FF_DEPTH 10 Index: sgmii/trunk/build/OpenCore_MAC/CLK_SWITCH.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/CLK_SWITCH.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/CLK_SWITCH.v (revision 26) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + + //assign OUT=SW?IN_1:IN_0; + BUFGMUX BUFGMUX_inst ( + .O(OUT), // Clock MUX output + .I0(IN_0), // Clock0 input + .I1(IN_1), // Clock1 input + .S(SW) // Clock select input + ); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/eth_miim.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/eth_miim.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/eth_miim.v (revision 26) @@ -0,0 +1,479 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_miim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// Revision 1.4 2005/08/16 12:07:57 Administrator +// no message +// +// Revision 1.3 2005/05/19 07:04:29 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2003/05/16 10:08:27 mohor +// Busy was set 2 cycles too late. Reported by Dennis Scott. +// +// Revision 1.4 2002/08/14 18:32:10 mohor +// - Busy signal was not set on time when scan status operation was performed +// and clock was divided with more than 2. +// - Nvalid remains valid two more clocks (was previously cleared too soon). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + + +module eth_miim +( + Clk, + Reset, + Divider, + NoPre, + CtrlData, + Rgad, + Fiad, + WCtrlData, + RStat, + ScanStat, + Mdo, + MdoEn, + Mdi, + Mdc, + Busy, + Prsd, + LinkFail, + Nvalid, + WCtrlDataStart, + RStatStart, + UpdateMIIRX_DATAReg +); + + + +input Clk; // Host Clock +input Reset; // General Reset +input [7:0] Divider; // Divider for the host clock +input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) +input [4:0] Rgad; // Register Address (within the PHY) +input [4:0] Fiad; // PHY Address +input NoPre; // No Preamble (no 32-bit preamble) +input WCtrlData; // Write Control Data operation +input RStat; // Read Status operation +input ScanStat; // Scan Status operation +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable +input Mdi; + +output Mdc; // MII Management Data Clock + +output Busy; // Busy Signal +output LinkFail; // Link Integrity Signal +output Nvalid; // Invalid Status (qualifier for the valid scan result) + +output [15:0] Prsd; // Read Status Data (data read from the PHY) + +output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +parameter Tp = 1; + + +reg Nvalid; +reg EndBusy_d; // Pre-end Busy signal +reg EndBusy; // End Busy signal (stops the operation in progress) + +reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle +reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles +reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles +reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) +reg WCtrlDataStart_q; +reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle +reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles + +reg RStat_q1; // Read Status operation delayed 1 Clk cycle +reg RStat_q2; // Read Status operation delayed 2 Clk cycles +reg RStat_q3; // Read Status operation delayed 3 Clk cycles +reg RStatStart; // Start Read Status Command (positive edge detected) +reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle +reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles + +reg ScanStat_q1; // Scan Status operation delayed 1 cycle +reg ScanStat_q2; // Scan Status operation delayed 2 cycles +reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn + +wire WriteDataOp; // Write Data Operation (positive edge detected) +wire ReadStatusOp; // Read Status Operation (positive edge detected) +wire ScanStatusOp; // Scan Status Operation (positive edge detected) +wire StartOp; // Start Operation (start of any of the preceding operations) +wire EndOp; // End of Operation + +reg InProgress; // Operation in progress +reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle +reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles +reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles + +reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +reg [6:0] BitCounter; // Bit Counter + + +wire MdcFrame; // Frame window for limiting the Mdc +wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. +wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. +wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal + + +wire LatchByte1_d2; +wire LatchByte0_d2; +reg LatchByte1_d; +reg LatchByte0_d; +reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register + +reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + + + +/* +assign Mdi=Mdio; +assign Mdio=MdoEn?Mdo:1'bz; +*/ + + + +// Generation of the EndBusy signal. It is used for ending the MII Management operation. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + EndBusy_d <= #Tp 1'b0; + EndBusy <= #Tp 1'b0; + end + else + begin + EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; + EndBusy <= #Tp EndBusy_d; + end +end + + +// Update MII RX_DATA register +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + UpdateMIIRX_DATAReg <= #Tp 0; + else + if(EndBusy & ~WCtrlDataStart_q) + UpdateMIIRX_DATAReg <= #Tp 1; + else + UpdateMIIRX_DATAReg <= #Tp 0; +end + + + +// Generation of the delayed signals used for positive edge triggering. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlData_q1 <= #Tp 1'b0; + WCtrlData_q2 <= #Tp 1'b0; + WCtrlData_q3 <= #Tp 1'b0; + + RStat_q1 <= #Tp 1'b0; + RStat_q2 <= #Tp 1'b0; + RStat_q3 <= #Tp 1'b0; + + ScanStat_q1 <= #Tp 1'b0; + ScanStat_q2 <= #Tp 1'b0; + SyncStatMdcEn <= #Tp 1'b0; + end + else + begin + WCtrlData_q1 <= #Tp WCtrlData; + WCtrlData_q2 <= #Tp WCtrlData_q1; + WCtrlData_q3 <= #Tp WCtrlData_q2; + + RStat_q1 <= #Tp RStat; + RStat_q2 <= #Tp RStat_q1; + RStat_q3 <= #Tp RStat_q2; + + ScanStat_q1 <= #Tp ScanStat; + ScanStat_q2 <= #Tp ScanStat_q1; + if(MdcEn) + SyncStatMdcEn <= #Tp ScanStat_q2; + end +end + + +// Generation of the Start Commands (Write Control Data or Read Status) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart <= #Tp 1'b0; + WCtrlDataStart_q <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(EndBusy) + begin + WCtrlDataStart <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(WCtrlData_q2 & ~WCtrlData_q3) + WCtrlDataStart <= #Tp 1'b1; + if(RStat_q2 & ~RStat_q3) + RStatStart <= #Tp 1'b1; + WCtrlDataStart_q <= #Tp WCtrlDataStart; + end + end +end + + +// Generation of the Nvalid signal (indicates when the status is invalid) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Nvalid <= #Tp 1'b0; + else + begin + if(~InProgress_q2 & InProgress_q3) + begin + Nvalid <= #Tp 1'b0; + end + else + begin + if(ScanStat_q2 & ~SyncStatMdcEn) + Nvalid <= #Tp 1'b1; + end + end +end + +// Signals used for the generation of the Operation signals (positive edge) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart_q1 <= #Tp 1'b0; + WCtrlDataStart_q2 <= #Tp 1'b0; + + RStatStart_q1 <= #Tp 1'b0; + RStatStart_q2 <= #Tp 1'b0; + + InProgress_q1 <= #Tp 1'b0; + InProgress_q2 <= #Tp 1'b0; + InProgress_q3 <= #Tp 1'b0; + + LatchByte0_d <= #Tp 1'b0; + LatchByte1_d <= #Tp 1'b0; + + LatchByte <= #Tp 2'b00; + end + else + begin + if(MdcEn) + begin + WCtrlDataStart_q1 <= #Tp WCtrlDataStart; + WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; + + RStatStart_q1 <= #Tp RStatStart; + RStatStart_q2 <= #Tp RStatStart_q1; + + LatchByte[0] <= #Tp LatchByte0_d; + LatchByte[1] <= #Tp LatchByte1_d; + + LatchByte0_d <= #Tp LatchByte0_d2; + LatchByte1_d <= #Tp LatchByte1_d2; + + InProgress_q1 <= #Tp InProgress; + InProgress_q2 <= #Tp InProgress_q1; + InProgress_q3 <= #Tp InProgress_q2; + end + end +end + + +// Generation of the Operation signals +assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; +assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; +assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; +assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; + +// Busy +reg Busy; +always @ (posedge Clk or posedge Reset) + if (Reset) + Busy <=0; + else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) + Busy <=1; + else + Busy <=0; + +//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; + + +// Generation of the InProgress signal (indicates when an operation is in progress) +// Generation of the WriteOp signal (indicates when a write is in progress) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + else + begin + if(MdcEn) + begin + if(StartOp) + begin + if(~InProgress) + WriteOp <= #Tp WriteDataOp; + InProgress <= #Tp 1'b1; + end + else + begin + if(EndOp) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + end + end + end +end + + + +// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + BitCounter[6:0] <= #Tp 7'h0; + else + begin + if(MdcEn) + begin + if(InProgress) + begin + if(NoPre & ( BitCounter == 7'h0 )) + BitCounter[6:0] <= #Tp 7'h21; + else + BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; + end + else + BitCounter[6:0] <= #Tp 7'h0; + end + end +end + + +// Operation ends when the Bit Counter reaches 63 +assign EndOp = BitCounter==63; + +assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); +assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); +assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); +assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); + + +// Latch Byte selects which part of Read Status Data is updated from the shift register +assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; +assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; + + +// Connecting the Clock Generator Module +eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) + ); + +// Connecting the Shift Register Module +eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), + .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), + .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) + ); + +// Connecting the Output Control Module +eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), + .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), + .Mdo(Mdo), .MdoEn(MdoEn) + ); + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/MAC_tx_Ctrl.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_tx_Ctrl.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_tx_Ctrl.v (revision 26) @@ -0,0 +1,643 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:38 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_ctrl ( +Reset , +Clk , +//CRC_gen Interface +CRC_init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out , +//Ramdon_gen interfac +Random_init , +RetryCnt , +Random_time_meet , +//flow control +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete , +//MAC_tx_FF +Fifo_data , +Fifo_rd , +Fifo_eop , +Fifo_da , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//RMII +TxD , +TxEn , +CRS , +//MAC_tx_addr_add +MAC_tx_addr_rd , +MAC_tx_addr_data , +MAC_tx_addr_init , +//RMON +Tx_pkt_type_rmon , +Tx_pkt_length_rmon , +Tx_apply_rmon , +Tx_pkt_err_type_rmon, +//CPU +pause_frame_send_en , +pause_quanta_set , +MAC_tx_add_en , +FullDuplex , +MaxRetry , +IFGset +); + +input Reset ; +input Clk ; + //CRC_gen Interface +output CRC_init ; +output [7:0] Frame_data ; +output Data_en ; +output CRC_rd ; +input CRC_end ; +input [7:0] CRC_out ; + //Ramdon_gen interface +output Random_init ; +output [3:0] RetryCnt ; +input Random_time_meet ;//levle hight indicate random time passed away + //flow control +input pause_apply ; +output pause_quanta_sub ; +input xoff_gen ; +output xoff_gen_complete ; +input xon_gen ; +output xon_gen_complete ; + //MAC_rx_FF +input [7:0] Fifo_data ; +output Fifo_rd ; +input Fifo_eop ; +input Fifo_da ; +output Fifo_rd_finish ; +output Fifo_rd_retry ; +input Fifo_ra ; +input Fifo_data_err_empty ; +input Fifo_data_err_full ; + //RMII +output [7:0] TxD ; +output TxEn ; +input CRS ; + //MAC_tx_addr_add +output MAC_tx_addr_init ; +output MAC_tx_addr_rd ; +input [7:0] MAC_tx_addr_data ; + //RMON +output [2:0] Tx_pkt_type_rmon ; +output [15:0] Tx_pkt_length_rmon ; +output Tx_apply_rmon ; +output [2:0] Tx_pkt_err_type_rmon; + //CPU +input pause_frame_send_en ; +input [15:0] pause_quanta_set ; +input MAC_tx_add_en ; +input FullDuplex ; +input [3:0] MaxRetry ; +input [5:0] IFGset ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd00; +parameter StatePreamble =4'd01; +parameter StateSFD =4'd02; +parameter StateData =4'd03; +parameter StatePause =4'd04; +parameter StatePAD =4'd05; +parameter StateFCS =4'd06; +parameter StateIFG =4'd07; +parameter StateJam =4'd08; +parameter StateBackOff =4'd09; +parameter StateJamDrop =4'd10; +parameter StateFFEmptyDrop =4'd11; +parameter StateSwitchNext =4'd12; +parameter StateDefer =4'd13; +parameter StateSendPauseFrame =4'd14; + +reg [3:0] Current_state /*synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [5:0] IFG_counter; +reg [4:0] Preamble_counter;// +reg [7:0] TxD_tmp ; +reg TxEn_tmp ; +reg [15:0] Tx_pkt_length_rmon ; +reg Tx_apply_rmon ; +reg Tx_apply_rmon_tmp ; +reg Tx_apply_rmon_tmp_pl1; +reg [2:0] Tx_pkt_err_type_rmon; +reg [3:0] RetryCnt ; +reg Random_init ; +reg Fifo_rd_finish ; +reg Fifo_rd_retry ; +reg [7:0] TxD ; +reg TxEn ; +reg CRC_init ; +reg Data_en ; +reg CRC_rd ; +reg Fifo_rd ; +reg MAC_tx_addr_rd ; +reg MAC_header_slot ; +reg MAC_header_slot_tmp ; +reg [2:0] Tx_pkt_type_rmon ; +wire Collision ; +reg MAC_tx_addr_init ; +reg Src_MAC_ptr ; +reg [7:0] IPLengthCounter ;//for pad append +reg [1:0] PADCounter ; +reg [7:0] JamCounter ; +reg PktDrpEvenPtr ; +reg [7:0] pause_counter ; +reg pause_quanta_sub ; +reg pause_frame_send_en_dl1 ; +reg [15:0] pause_quanta_set_dl1 ; +reg xoff_gen_complete ; +reg xon_gen_complete ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + begin + pause_frame_send_en_dl1 <=0; + pause_quanta_set_dl1 <=0; + end + else + begin + pause_frame_send_en_dl1 <=pause_frame_send_en ; + pause_quanta_set_dl1 <=pause_quanta_set ; + end +//****************************************************************************** +//state machine +//****************************************************************************** +assign Collision=TxEn&CRS; + +always @(posedge Clk or posedge Reset) + if (Reset) + pause_counter <=0; + else if (Current_state!=StatePause) + pause_counter <=0; + else + pause_counter <=pause_counter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + IPLengthCounter <=0; + else if (Current_state==StateDefer) + IPLengthCounter <=0; + else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)) + IPLengthCounter <=IPLengthCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + PADCounter <=0; + else if (Current_state!=StatePAD) + PADCounter <=0; + else + PADCounter <=PADCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + Current_state <=StateDefer; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + StateDefer: + if ((FullDuplex)||(!FullDuplex&&!CRS)) + Next_state=StateIFG; + else + Next_state=Current_state; + StateIFG: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time + Next_state=StateIdle; + else + Next_state=Current_state; + StateIdle: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if (pause_apply) + Next_state=StatePause; + else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))) + Next_state=StatePreamble; + else + Next_state=Current_state; + StatePause: + if (pause_counter==512/8) + Next_state=StateDefer; + else + Next_state=Current_state; + StatePreamble: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6)) + Next_state=StateSFD; + else + Next_state=Current_state; + StateSFD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) + Next_state=StateSendPauseFrame; + else + Next_state=StateData; + StateSendPauseFrame: + if (IPLengthCounter==17) + Next_state=StatePAD; + else + Next_state=Current_state; + StateData: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (Fifo_data_err_empty) + Next_state=StateFFEmptyDrop; + else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0 + Next_state=StateFCS; + else if (Fifo_eop) + Next_state=StatePAD; + else + Next_state=StateData; + StatePAD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (IPLengthCounter>=59) + Next_state=StateFCS; + else + Next_state=Current_state; + StateJam: + if (RetryCnt<=MaxRetry&&JamCounter==16) + Next_state=StateBackOff; + else if (RetryCnt>MaxRetry) + Next_state=StateJamDrop; + else + Next_state=Current_state; + StateBackOff: + if (Random_time_meet) + Next_state =StateDefer; + else + Next_state =Current_state; + StateFCS: + if (!FullDuplex&&Collision) + Next_state =StateJam; + else if (CRC_end) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateFFEmptyDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateJamDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateSwitchNext: + Next_state =StateDefer; + default: + Next_state =StateDefer; + endcase + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + JamCounter <=0; + else if (Current_state!=StateJam) + JamCounter <=0; + else if (Current_state==StateJam) + JamCounter <=JamCounter+1; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + RetryCnt <=0; + else if (Current_state==StateSwitchNext) + RetryCnt <=0; + else if (Current_state==StateJam&&Next_state==StateBackOff) + RetryCnt <=RetryCnt + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + IFG_counter <=0; + else if (Current_state!=StateIFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Preamble_counter <=0; + else if (Current_state!=StatePreamble) + Preamble_counter <=0; + else + Preamble_counter <=Preamble_counter+ 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + PktDrpEvenPtr <=0; + else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop) + PktDrpEvenPtr <=~PktDrpEvenPtr; +//****************************************************************************** +//generate output signals +//****************************************************************************** +//CRC related +always @(Current_state) + if (Current_state==StateSFD) + CRC_init =1; + else + CRC_init =0; + +assign Frame_data=TxD_tmp; + +always @(Current_state) + if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD) + Data_en =1; + else + Data_en =0; + +always @(Current_state) + if (Current_state==StateFCS) + CRC_rd =1; + else + CRC_rd =0; + +//Ramdon_gen interface +always @(Current_state or Next_state) + if (Current_state==StateJam&&Next_state==StateBackOff) + Random_init =1; + else + Random_init =0; + +//MAC_rx_FF +//data have one cycle delay after fifo read signals +always @ (*) + if (Current_state==StateData || + Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) || + Current_state==StateJamDrop&&PktDrpEvenPtr|| + Current_state==StateFFEmptyDrop&&PktDrpEvenPtr ) + Fifo_rd =1; + else + Fifo_rd =0; + +always @ (Current_state) + if (Current_state==StateSwitchNext) + Fifo_rd_finish =1; + else + Fifo_rd_finish =0; + +always @ (Current_state) + if (Current_state==StateJam) + Fifo_rd_retry =1; + else + Fifo_rd_retry =0; +//RMII +always @(Current_state) + if (Current_state==StatePreamble||Current_state==StateSFD|| + Current_state==StateData||Current_state==StateSendPauseFrame|| + Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam) + TxEn_tmp =1; + else + TxEn_tmp =0; + +//gen txd data +always @(*) + case (Current_state) + StatePreamble: + TxD_tmp =8'h55; + StateSFD: + TxD_tmp =8'hd5; + StateData: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + TxD_tmp =Fifo_data; + StateSendPauseFrame: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + case (IPLengthCounter) + 7'd0: TxD_tmp =8'h01; + 7'd1: TxD_tmp =8'h80; + 7'd2: TxD_tmp =8'hc2; + 7'd3: TxD_tmp =8'h00; + 7'd4: TxD_tmp =8'h00; + 7'd5: TxD_tmp =8'h01; + 7'd12: TxD_tmp =8'h88;//type + 7'd13: TxD_tmp =8'h08;// + 7'd14: TxD_tmp =8'h00;//opcode + 7'd15: TxD_tmp =8'h01; + 7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8]; + 7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0]; +// 7'd60: TxD_tmp =8'h26; +// 7'd61: TxD_tmp =8'h6b; +// 7'd62: TxD_tmp =8'hae; +// 7'd63: TxD_tmp =8'h0a; + default:TxD_tmp =0; + endcase + + StatePAD: + TxD_tmp =8'h00; + StateJam: + TxD_tmp =8'h01; //jam sequence + StateFCS: + TxD_tmp =CRC_out; + default: + TxD_tmp =2'b0; + endcase +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + TxD <=0; + TxEn <=0; + end + else + begin + TxD <=TxD_tmp; + TxEn <=TxEn_tmp; + end +//RMON + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateSFD) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS) + Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon_tmp <=1; + else + Tx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp_pl1 <=0; + else + Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon <=1; + else if (Tx_apply_rmon_tmp_pl1) + Tx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_err_type_rmon <=0; + else if(Fifo_eop&&Current_state==StateJamDrop) + Tx_pkt_err_type_rmon <=3'b001;// + else if(Fifo_eop&&Current_state==StateFFEmptyDrop) + Tx_pkt_err_type_rmon <=3'b010;//underflow + else if(Fifo_eop&&Fifo_data_err_full) + Tx_pkt_err_type_rmon <=3'b011;//overflow + else if(CRC_end) + Tx_pkt_err_type_rmon <=3'b100;//normal + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot_tmp <=0; + else if(Current_state==StateSFD&&Next_state==StateData) + MAC_header_slot_tmp <=1; + else + MAC_header_slot_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot <=0; + else + MAC_header_slot <=MAC_header_slot_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_type_rmon <=0; + else if (Current_state==StateSendPauseFrame) + Tx_pkt_type_rmon <=3'b100; + else if(MAC_header_slot) + Tx_pkt_type_rmon <={1'b0,TxD[7:6]}; + + +always @(Tx_pkt_length_rmon) + if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11) + Src_MAC_ptr =1; + else + Src_MAC_ptr =0; + +//MAC_tx_addr_add +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_tx_addr_rd <=0; + else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame)) + MAC_tx_addr_rd <=1; + else + MAC_tx_addr_rd <=0; + +always @ (Tx_pkt_length_rmon or Fifo_rd) + if ((Tx_pkt_length_rmon==3)&&Fifo_rd) + MAC_tx_addr_init=1; + else + MAC_tx_addr_init=0; + +//flow control +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_sub <=0; + else if(pause_counter==512/8) + pause_quanta_sub <=1; + else + pause_quanta_sub <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen_complete <=0; + else if(Current_state==StateDefer&&xoff_gen) + xoff_gen_complete <=1; + else + xoff_gen_complete <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen_complete <=0; + else if(Current_state==StateDefer&&xon_gen) + xon_gen_complete <=1; + else + xon_gen_complete <=0; + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/CRC_gen.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/CRC_gen.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/CRC_gen.v (revision 26) @@ -0,0 +1,165 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_gen ( +Reset , +Clk , +Init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] Frame_data ; +input Data_en ; +input CRC_rd ; +output [7:0] CRC_out ; +output CRC_end ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] CRC_out ; +reg [31:0] CRC_reg; +reg CRC_end; +reg [3:0] Counter; +//****************************************************************************** +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction +//****************************************************************************** + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (Init) + CRC_reg <=32'hffffffff; + else if (Data_en) + CRC_reg <=NextCRC(Frame_data,CRC_reg); + else if (CRC_rd) + CRC_reg <={CRC_reg[23:0],8'hff}; + +always @ (CRC_rd or CRC_reg) + if (CRC_rd) + CRC_out <=~{ + CRC_reg[24], + CRC_reg[25], + CRC_reg[26], + CRC_reg[27], + CRC_reg[28], + CRC_reg[29], + CRC_reg[30], + CRC_reg[31] + }; + else + CRC_out <=0; + +//caculate CRC out length ,4 cycles +//CRC_end aligned to last CRC checksum data +always @(posedge Clk or posedge Reset) + if (Reset) + Counter <=0; + else if (!CRC_rd) + Counter <=0; + else + Counter <=Counter + 1; + +always @ (Counter) + if (Counter==3) + CRC_end=1; + else + CRC_end=0; + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/icon_xst_example.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/icon_xst_example.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/icon_xst_example.v (revision 26) @@ -0,0 +1,56 @@ +//----------------------------------------------------------------------------- +// Copyright (c) 1999-2006 Xilinx Inc. All rights reserved. +//----------------------------------------------------------------------------- +// Title : ICON Core Xilinx XST Usage Example +// Project : ChipScope +//----------------------------------------------------------------------------- +// File : icon_xst_example.v +// Company : Xilinx Inc. +// Created : 2002/03/27 +//----------------------------------------------------------------------------- +// Description: Example of how to instantiate the ICON core in a Verilog +// design for use with the Xilinx XST synthesis tool. +//----------------------------------------------------------------------------- + +module icon_xst_example + ( + ); + + + //----------------------------------------------------------------- + // + // ICON core wire declarations + // + //----------------------------------------------------------------- + wire [35:0] control0; + wire [35:0] control1; + + + //----------------------------------------------------------------- + // + // ICON core instance + // + //----------------------------------------------------------------- + icon i_icon + ( + .control0(control0), + .control1(control1) + ); + + +endmodule + + +//------------------------------------------------------------------- +// +// ICON core module declaration +// +//------------------------------------------------------------------- +module icon + ( + control0, + control1 + ); + output [35:0] control0; + output [35:0] control1; +endmodule Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v.bak (revision 26) @@ -0,0 +1,153 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_add_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_add_chk ( +Reset , +Clk , +Init , +data , +MAC_add_en , +MAC_rx_add_chk_err , +//From CPU +MAC_rx_add_chk_en , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] data ; +input MAC_add_en ; +output MAC_rx_add_chk_err ; + //From CPU +input MAC_rx_add_chk_en ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] addr_rd; +wire[2:0] addr_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; + +reg MAC_rx_add_chk_err; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +reg [7:0] data_dl1 ; +reg MAC_add_en_dl1 ; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + data_dl1 <=0; + MAC_add_en_dl1 <=0; + end + else + begin + data_dl1 <=data; + MAC_add_en_dl1 <=MAC_add_en; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + +assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign addr_wr =MAC_add_prom_add; +assign din =MAC_add_prom_data; + +//****************************************************************************** +//mac add verify +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + addr_rd <=0; + else if (Init) + addr_rd <=0; + else if (MAC_add_en) + addr_rd <=addr_rd + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_rx_add_chk_err <=0; + else if (Init) + MAC_rx_add_chk_err <=0; + else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1) + MAC_rx_add_chk_err <=1; + + +//****************************************************************************** +//a port for read ,b port for write . +//****************************************************************************** +duram #(8,3,"M512","DUAL_PORT") U_duram( +.data_a (din ), +.wren_a (wr_en ), +.address_a (addr_wr ), +.address_b (addr_rd ), +.clock_a (Clk ), +.clock_b (Clk ), +.q_b (dout )); + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/Phy_int.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Phy_int.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Phy_int.v.bak (revision 26) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_int.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:36 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Phy_int ( +Reset , +MAC_rx_clk , +MAC_tx_clk , +//Rx interface , +MCrs_dv , +MRxD , +MRxErr , +//Tx interface , +MTxD , +MTxEn , +MCRS , +//Phy interface , +Tx_er , +Tx_en , +Txd , +Rx_er , +Rx_dv , +Rxd , +Crs , +Col , +//host interface , +Line_loop_en , +Speed + +); +input Reset ; +input MAC_rx_clk ; +input MAC_tx_clk ; + //Rx interface +output MCrs_dv ; +output [7:0] MRxD ; +output MRxErr ; + //Tx interface +input [7:0] MTxD ; +input MTxEn ; +output MCRS ; + //Phy interface +output Tx_er ; +output Tx_en ; +output [7:0] Txd ; +input Rx_er ; +input Rx_dv ; +input [7:0] Rxd ; +input Crs ; +input Col ; + //host interface +input Line_loop_en ; +input [2:0] Speed ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] MTxD_dl1 ; +reg MTxEn_dl1 ; +reg Tx_odd_data_ptr ; +reg Rx_odd_data_ptr ; +reg Tx_en ; +reg [7:0] Txd ; +reg MCrs_dv ; +reg [7:0] MRxD ; +reg Rx_er_dl1 ; +reg Rx_dv_dl1 ; +reg Rx_dv_dl2 ; +reg [7:0] Rxd_dl1 ; +reg [7:0] Rxd_dl2 ; +reg Crs_dl1 ; +reg Col_dl1 ; +//****************************************************************************** +//Tx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + begin + MTxD_dl1 <=0; + MTxEn_dl1 <=0; + end + else + begin + MTxD_dl1 <=MTxD ; + MTxEn_dl1 <=MTxEn ; + end + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_odd_data_ptr <=0; + else if (!MTxD_dl1) + Tx_odd_data_ptr <=0; + else + Tx_odd_data_ptr <=!Tx_odd_data_ptr; + + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Txd <=0; + else if(Speed[2]&&MTxEn_dl1) + Txd <=MTxD_dl1; + else if(MTxEn_dl1&&!Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[3:0]}; + else if(MTxEn_dl1&&Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[7:4]}; + else + Txd <=0; + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_en <=0; + else if(MTxEn_dl1) + Tx_en <=1; + else + Tx_en <=0; + +assign Tx_er=0; + +//****************************************************************************** +//Rx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + begin + Rx_er_dl1 <=0; + Rx_dv_dl1 <=0; + Rx_dv_dl2 <=0 ; + Rxd_dl1 <=0; + Rxd_dl2 <=0; + Crs_dl1 <=0; + Col_dl1 <=0; + end + else + begin + Rx_er_dl1 <=Rx_er ; + Rx_dv_dl1 <=Rx_dv ; + Rx_dv_dl2 <=Rx_dv_dl1 ; + Rxd_dl1 <=Rxd ; + Rxd_dl2 <=Rxd_dl1 ; + Crs_dl1 <=Crs ; + Col_dl1 <=Col ; + end + +assign MRxErr =Rx_er_dl1 ; +assign MCRS =Crs_dl1 ; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MCrs_dv <=0; + else if(Line_loop_en) + MCrs_dv <=Tx_en; + else if(Rx_dv_dl2) + MCrs_dv <=1; + else + MCrs_dv <=0; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + Rx_odd_data_ptr <=0; + else if (!Rx_dv_dl1) + Rx_odd_data_ptr <=0; + else + Rx_odd_data_ptr <=!Rx_odd_data_ptr; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MRxD <=0; + else if(Line_loop_en) + MRxD <=Txd; + else if(Speed[2]&&Rx_dv_dl2) + MRxD <=Rxd_dl2; + else if(Rx_dv_dl1&&Rx_odd_data_ptr) + MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]}; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_add_chk.v (revision 26) @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_add_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_add_chk ( +Reset , +Clk , +Init , +data , +MAC_add_en , +MAC_rx_add_chk_err , +//From CPU +MAC_rx_add_chk_en , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] data ; +input MAC_add_en ; +output MAC_rx_add_chk_err ; + //From CPU +input MAC_rx_add_chk_en ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] addr_rd; +wire[2:0] addr_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; + +reg MAC_rx_add_chk_err; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +reg [7:0] data_dl1 ; +reg MAC_add_en_dl1 ; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + data_dl1 <=0; + MAC_add_en_dl1 <=0; + end + else + begin + data_dl1 <=data; + MAC_add_en_dl1 <=MAC_add_en; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + +assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign addr_wr =MAC_add_prom_add; +assign din =MAC_add_prom_data; + +//****************************************************************************** +//mac add verify +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + addr_rd <=0; + else if (Init) + addr_rd <=0; + else if (MAC_add_en) + addr_rd <=addr_rd + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_rx_add_chk_err <=0; + else if (Init) + MAC_rx_add_chk_err <=0; + else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1) + MAC_rx_add_chk_err <=1; + + + + reg [7:0] MacAddr[0:7]; + + always@(posedge Clk or posedge Reset) + if(Reset) + begin + MacAddr[0]<=8'h00; + MacAddr[1]<=8'h1F; + MacAddr[2]<=8'h02; + MacAddr[3]<=8'h03; + MacAddr[4]<=8'hAA; + MacAddr[5]<=8'hBB; + MacAddr[6]<=8'h00; + MacAddr[7]<=8'h00; + end + else + if(wr_en) + MacAddr[addr_wr]<=din; + reg [7:0] MacData; + always@(posedge Clk) + MacData <= MacAddr[addr_rd]; + assign dout = MacData; + +//****************************************************************************** +//a port for read ,b port for write . +//****************************************************************************** +//duram #(8,3,"M512","DUAL_PORT") U_duram( +//.data_a (din ), +//.wren_a (wr_en ), +//.address_a (addr_wr ), +//.address_b (addr_rd ), +//.clock_a (Clk ), +//.clock_b (Clk ), +//.q_b (dout )); + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/Ramdon_gen.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Ramdon_gen.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Ramdon_gen.v (revision 26) @@ -0,0 +1,120 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Ramdon_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module Ramdon_gen( +Reset , +Clk , +Init , +RetryCnt , +Random_time_meet +); +input Reset ; +input Clk ; +input Init ; +input [3:0] RetryCnt ; +output Random_time_meet; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [9:0] Random_sequence ; +reg [9:0] Ramdom ; +reg [9:0] Ramdom_counter ; +reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time +reg Random_time_meet; + +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_sequence <=0; + else + Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])}; + +always @ (RetryCnt or Random_sequence) + case (RetryCnt) + 4'h0 : Ramdom={9'b0,Random_sequence[0]}; + 4'h1 : Ramdom={8'b0,Random_sequence[1:0]}; + 4'h2 : Ramdom={7'b0,Random_sequence[2:0]}; + 4'h3 : Ramdom={6'b0,Random_sequence[3:0]}; + 4'h4 : Ramdom={5'b0,Random_sequence[4:0]}; + 4'h5 : Ramdom={4'b0,Random_sequence[5:0]}; + 4'h6 : Ramdom={3'b0,Random_sequence[6:0]}; + 4'h7 : Ramdom={2'b0,Random_sequence[7:0]}; + 4'h8 : Ramdom={1'b0,Random_sequence[8:0]}; + 4'h9 : Ramdom={ Random_sequence[9:0]}; + default : Ramdom={ Random_sequence[9:0]}; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + Slot_time_counter <=0; + else if(Init) + Slot_time_counter <=0; + else if(!Random_time_meet) + Slot_time_counter <=Slot_time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Ramdom_counter <=0; + else if (Init) + Ramdom_counter <=Ramdom; + else if (Ramdom_counter!=0&&Slot_time_counter==255) + Ramdom_counter <=Ramdom_counter -1 ; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_time_meet <=1; + else if (Init) + Random_time_meet <=0; + else if (Ramdom_counter==0) + Random_time_meet <=1; + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/Phy_int.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Phy_int.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Phy_int.v (revision 26) @@ -0,0 +1,231 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_int.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:36 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// 2011/04/01 Jeff Changes #1 + +module Phy_int ( +Reset , +MAC_rx_clk , +MAC_tx_clk , +//Rx interface , +MCrs_dv , +MRxD , +MRxErr , +//Tx interface , +MTxD , +MTxEn , +MCRS , +//Phy interface , +Tx_er , +Tx_en , +Txd , +Rx_er , +Rx_dv , +Rxd , +Crs , +Col , +//host interface , +Line_loop_en , +Speed + +); +input Reset ; +input MAC_rx_clk ; +input MAC_tx_clk ; + //Rx interface +output MCrs_dv ; +output [7:0] MRxD ; +output MRxErr ; + //Tx interface +input [7:0] MTxD ; +input MTxEn ; +output MCRS ; + //Phy interface +output Tx_er ; +output Tx_en ; +output [7:0] Txd ; +input Rx_er ; +input Rx_dv ; +input [7:0] Rxd ; +input Crs ; +input Col ; + //host interface +input Line_loop_en ; +input [2:0] Speed ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] MTxD_dl1 ; +reg MTxEn_dl1 ; +reg Tx_odd_data_ptr ; +reg Rx_odd_data_ptr ; +reg Tx_en ; +reg [7:0] Txd ; +reg MCrs_dv ; +reg [7:0] MRxD ; +reg Rx_er_dl1 ; +reg Rx_er_dl3 ; +reg Rx_er_dl2 ; +reg Rx_dv_dl1 ; +reg Rx_dv_dl2 ; +reg [7:0] Rxd_dl1 ; +reg [7:0] Rxd_dl2 ; +reg Crs_dl1 ; +reg Col_dl1 ; +//****************************************************************************** +//Tx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + begin + MTxD_dl1 <=0; + MTxEn_dl1 <=0; + end + else + begin + MTxD_dl1 <=MTxD ; + MTxEn_dl1 <=MTxEn ; + end + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_odd_data_ptr <=0; + else if (!MTxD_dl1) + Tx_odd_data_ptr <=0; + else + Tx_odd_data_ptr <=!Tx_odd_data_ptr; + + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Txd <=0; + else if(Speed[2]&&MTxEn_dl1) + Txd <=MTxD_dl1; + else if(MTxEn_dl1&&!Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[3:0]}; + else if(MTxEn_dl1&&Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[7:4]}; + else + Txd <=0; + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_en <=0; + else if(MTxEn_dl1) + Tx_en <=1; + else + Tx_en <=0; + +assign Tx_er=0; + +//****************************************************************************** +//Rx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + begin + Rx_er_dl1 <=0; + Rx_dv_dl1 <=0; + Rx_dv_dl2 <=0 ; + Rxd_dl1 <=0; + Rxd_dl2 <=0; + Crs_dl1 <=0; + Col_dl1 <=0; + end + else + begin + Rx_er_dl1 <=Rx_er ; + //Jeff Changes #1 + Rx_er_dl2 <=Rx_er_dl1; + Rx_er_dl3 <=Rx_er_dl2&Rx_dv_dl2; + Rx_dv_dl1 <=Rx_dv ; + Rx_dv_dl2 <=Rx_dv_dl1 ; + Rxd_dl1 <=Rxd ; + Rxd_dl2 <=Rxd_dl1 ; + Crs_dl1 <=Crs ; + Col_dl1 <=Col ; + end + +//assign MRxErr =Rx_er_dl1 ; +assign MRxErr = Rx_er_dl3; +assign MCRS =Crs_dl1 ; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MCrs_dv <=0; + else if(Line_loop_en) + MCrs_dv <=Tx_en; + else if(Rx_dv_dl2) + MCrs_dv <=1; + else + MCrs_dv <=0; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + Rx_odd_data_ptr <=0; + else if (!Rx_dv_dl1) + Rx_odd_data_ptr <=0; + else + Rx_odd_data_ptr <=!Rx_odd_data_ptr; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MRxD <=0; + else if(Line_loop_en) + MRxD <=Txd; + else if(Speed[2]&&Rx_dv_dl2) + MRxD <=Rxd_dl2; + else if(Rx_dv_dl1&&Rx_odd_data_ptr) + MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]}; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/eth_shiftreg.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/eth_shiftreg.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/eth_shiftreg.v (revision 26) @@ -0,0 +1,161 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:47 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= #Tp 8'h0; + Prsd[15:0] <= #Tp 16'h0; + LinkFail <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) + 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; + default : ShiftReg[7:0] <= #Tp 8'h0; + endcase + end + else + begin + ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/Clk_ctrl_V4port.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Clk_ctrl_V4port.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Clk_ctrl_V4port.v (revision 26) @@ -0,0 +1,168 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clk_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Clk_ctrl_V4port( +Reset , +Clk_125M , +//host interface, +Speed , +//Phy interface , +Gtx_clk , +Rx_clk , +Tx_clk , +//interface clk , +MAC_tx_clk , +MAC_rx_clk , +MAC_tx_clk_div , +MAC_rx_clk_div +); +input Reset ; +input Clk_125M ; + //host interface +input [2:0] Speed ; + //Phy interface +output Gtx_clk ;//used only in GMII mode +input Rx_clk ; +input Tx_clk ;//used only in MII mode + //interface clk signals +output MAC_tx_clk ; +output MAC_rx_clk ; +output MAC_tx_clk_div ; +output MAC_rx_clk_div ; + + +//****************************************************************************** +//internal signals +//****************************************************************************** +wire Rx_clk_div2 ; +wire Tx_clk_div2 ; + +wire Clk125i, Clk125; +wire Clk25i, Clk25; +//****************************************************************************** +// +//****************************************************************************** +assign Gtx_clk =Clk_125M ; +assign MAC_rx_clk =Rx_clk ; + +DCM_BASE #( + .CLKDV_DIVIDE(5.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(5), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(1), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_BASE_TX125M ( + .CLK0(Clk125), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(Clk25), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .CLKFB(Clk125i), // DCM clock feedback + .CLKIN(Clk_125M), // Clock input (from IBUFG, BUFG or DCM) + .RST(rst) // DCM asynchronous reset input + ); + + BUFG + + +//pragma synthesis_off +CLK_DIV2_Wrapper U_0_CLK_DIV2( +.Reset (Reset ), +.IN (Rx_clk ), +.OUT (Rx_clk_div2 ) +); + +CLK_DIV2_Wrapper U_1_CLK_DIV2( +.Reset (Reset ), +.IN (Tx_clk ), +.OUT (Tx_clk_div2 ) +); + +CLK_SWITCH U_0_CLK_SWITCH( +.IN_0 (Rx_clk_div2 ), +.IN_1 (Rx_clk ), +.SW (Speed[2] ), +.OUT (MAC_rx_clk_div ) +); + +CLK_SWITCH U_1_CLK_SWITCH( +.IN_0 (Tx_clk ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk ) +); + + +CLK_SWITCH U_2_CLK_SWITCH( +.IN_0 (Tx_clk_div2 ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_div ) +); + +//pragma synthesis_on + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/ila_xst_example.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/ila_xst_example.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/ila_xst_example.v (revision 26) @@ -0,0 +1,73 @@ +//----------------------------------------------------------------------------- +// Copyright (c) 1999-2006 Xilinx Inc. All rights reserved. +//----------------------------------------------------------------------------- +// Title : ILA Core Xilinx XST Usage Example +// Project : ChipScope +//----------------------------------------------------------------------------- +// File : ila_xst_example.v +// Company : Xilinx Inc. +// Created : 2002/03/27 +//----------------------------------------------------------------------------- +// Description: Example of how to instantiate the ILA core in a Verilog +// design for use with the Xilinx XST synthesis tool. +//----------------------------------------------------------------------------- + +module ila_xst_example + ( + ); + + + //----------------------------------------------------------------- + // + // ILA Core wire declarations + // + //----------------------------------------------------------------- + wire [35:0] control; + wire clk; + wire [63:0] data; + wire [0:0] trig0; + wire [0:0] trig1; + wire [0:0] trig2; + + + //----------------------------------------------------------------- + // + // ILA core instance + // + //----------------------------------------------------------------- + ila i_ila + ( + .control(control), + .clk(clk), + .data(data), + .trig0(trig0), + .trig1(trig1), + .trig2(trig2) + ); + + +endmodule + + +//------------------------------------------------------------------- +// +// ILA core module declaration +// +//------------------------------------------------------------------- +module ila + ( + control, + clk, + data, + trig0, + trig1, + trig2 + ); + input [35:0] control; + input clk; + input [63:0] data; + input [0:0] trig0; + input [0:0] trig1; + input [0:0] trig2; +endmodule + Index: sgmii/trunk/build/OpenCore_MAC/Clocks.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Clocks.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Clocks.v (revision 26) @@ -0,0 +1,126 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:13:01 06/02/2010 +// Design Name: +// Module Name: Clocks +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Clocks( + input V4_Clk_125M, + input V4_Clk_27M, + input V4_Clk_13M5, + input V4_Clk_66M, + input [2:0] Speed, + output Clk_125M, + output Clk_27M, + output Clk_13M5, + output Clk_25M, + output Clk_66M, + output Clk_125M_90, + output TxClk, + output TxClk_MAC, + input rst + ); + +reg Clk2m5; +reg Clk2m5div2; +reg Clk25div2; +wire Clk25div2i; +wire Clk2m5i; + +wire ClkTx; +wire ClkTxdiv2; + +wire Clk25, Clk25i; +wire Clk125, Clk125i; +wire Clk125_90; + // DCM_BASE: Base Digital Clock Manager Circuit + // Virtex-4/5 + // Xilinx HDL Language Template, version 10.1 + + DCM_BASE #( + .CLKDV_DIVIDE(5.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(5), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(8.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_BASE_125M ( + .CLK0(Clk125), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(Clk125_90), // 90 degree DCM CLK output + .CLKDV(Clk25), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .CLKFB(Clk125i), // DCM clock feedback + .CLKIN(V4_Clk_125M), // Clock input (from IBUFG, BUFG or DCM) + .RST(rst) // DCM asynchronous reset input + ); + + BUFG BUFG_inst ( + .O(Clk125i), // Clock buffer output + .I(Clk125) // Clock buffer input + ); + + assign Clk_125M = Clk125i; + + BUFG BUFG25_inst ( + .O(Clk25i), // Clock buffer output + .I(Clk25) // Clock buffer input + ); + + BUFG BUF125_90( + .O(Clk_125M_90), + .I(Clk125_90)); + + assign Clk_25M = Clk25i; + + // End of DCM_BASE_inst instantiation + +// always@(posedge Clk25i or posedge rst) +// if(rst) +// begin +// cntr <= 0; +// Clk2m5 <= 0; +// Clk2m5div2 <= 0; +// Clk25div2 <= 0; +// end +// else +// begin +// if(cntr==9) cntr<=0; else cntr<=cntr+1; +// if(cntr==0 || cntr==5) Clk2m5 <= ~Clk2m5; +// if(cntr==0) Clk2m5div2 <= ~Clk2m5div2; +// Clk25div2 <= ~Clk25div2; +// end + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v.bak (revision 26) @@ -0,0 +1,729 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2008/08/17 11:41:30 maverickist +// no message +// +// Revision 1.5 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_FF ( +Reset , +Clk_MAC , +Clk_SYS , +//MAC_rx_ctrl interface +Fifo_data , +Fifo_data_en , +Fifo_full , +Fifo_data_err , +Fifo_data_end , +//CPU +Rx_Hwmark, +Rx_Lwmark, +RX_APPEND_CRC, +//user interface +Rx_mac_ra , +Rx_mac_rd , +Rx_mac_data , +Rx_mac_BE , +Rx_mac_sop , +Rx_mac_pa, +Rx_mac_eop +); +input Reset ; +input Clk_MAC ; +input Clk_SYS ; + //MAC_rx_ctrl interface +input [7:0] Fifo_data ; +input Fifo_data_en ; +output Fifo_full ; +input Fifo_data_err ; +input Fifo_data_end ; + //CPU +input RX_APPEND_CRC ; +input [4:0] Rx_Hwmark ; +input [4:0] Rx_Lwmark ; + //user interface +output Rx_mac_ra ;// +input Rx_mac_rd ; +output [31:0] Rx_mac_data ; +output [1:0] Rx_mac_BE ; +output Rx_mac_pa ; +output Rx_mac_sop ; +output Rx_mac_eop ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_byte3 =4'd0; +parameter State_byte2 =4'd1; +parameter State_byte1 =4'd2; +parameter State_byte0 =4'd3; +parameter State_be0 =4'd4; +parameter State_be3 =4'd5; +parameter State_be2 =4'd6; +parameter State_be1 =4'd7; +parameter State_err_end =4'd8; +parameter State_idle =4'd9; + +parameter SYS_read =3'd0; +parameter SYS_pause =3'd1; +parameter SYS_wait_end =3'd2; +parameter SYS_idle =3'd3; +parameter FF_emtpy_err =3'd4; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray; +reg [35:0] Din; +reg [35:0] Din_tmp; +reg [35:0] Din_tmp_reg; +wire[35:0] Dout; +reg Wr_en; +reg Wr_en_tmp; +reg Wr_en_ptr; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2; +reg Full; +reg Almost_full; +reg Empty /* synthesis syn_keep=1 */; +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [7:0] Fifo_data_byte0; +reg [7:0] Fifo_data_byte1; +reg [7:0] Fifo_data_byte2; +reg [7:0] Fifo_data_byte3; +reg Fifo_data_en_dl1; +reg [7:0] Fifo_data_dl1; +reg Rx_mac_sop_tmp ; +reg Rx_mac_sop ; +reg Rx_mac_ra ; +reg Rx_mac_pa ; + + + +reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */; +reg [2:0] Next_state_SYS ; +reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; +reg Packet_number_sub ; +wire Packet_number_add_edge; +reg Packet_number_add_dl1; +reg Packet_number_add_dl2; +reg Packet_number_add ; +reg Packet_number_add_tmp ; +reg Packet_number_add_tmp_dl1; +reg Packet_number_add_tmp_dl2; + +reg Rx_mac_sop_tmp_dl1; +reg [35:0] Dout_dl1; +reg [4:0] Fifo_data_count; +reg Rx_mac_pa_tmp ; +reg Add_wr_jump_tmp ; +reg Add_wr_jump_tmp_pl1 ; +reg Add_wr_jump ; +reg Add_wr_jump_rd_pl1 ; +reg [4:0] Rx_Hwmark_pl ; +reg [4:0] Rx_Lwmark_pl ; +reg Addr_freshed_ptr ; +integer i ; +//****************************************************************************** +//domain Clk_MAC,write data to dprom.a-port for write +//****************************************************************************** +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end) + case (Current_state) + State_idle: + if (Fifo_data_en) + Next_state =State_byte3; + else + Next_state =Current_state; + State_byte3: + if (Fifo_data_en) + Next_state =State_byte2; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be1; + else + Next_state =Current_state; + State_byte2: + if (Fifo_data_en) + Next_state =State_byte1; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be2; + else + Next_state =Current_state; + State_byte1: + if (Fifo_data_en) + Next_state =State_byte0; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be3; + else + Next_state =Current_state; + State_byte0: + if (Fifo_data_en) + Next_state =State_byte3; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be0; + else + Next_state =Current_state; + State_be1: + Next_state =State_idle; + State_be2: + Next_state =State_idle; + State_be3: + Next_state =State_idle; + State_be0: + Next_state =State_idle; + State_err_end: + Next_state =State_idle; + default: + Next_state =State_idle; + endcase + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_reg <=0; + else if (Current_state==State_idle) + Add_wr_reg <=Add_wr; + +// + + +always @ (posedge Reset or posedge Clk_MAC) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else + begin + Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end +assign Add_wr_pluse=Add_wr+1; +assign Add_wr_pluse4=Add_wr+4; +assign Add_wr_pluse3=Add_wr+3; +assign Add_wr_pluse2=Add_wr+2; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Full <=0; + else if (Add_wr_pluse==Add_rd_ungray) + Full <=1; + else + Full <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Almost_full <=0; + else if (Add_wr_pluse4==Add_rd_ungray|| + Add_wr_pluse3==Add_rd_ungray|| + Add_wr_pluse2==Add_rd_ungray|| + Add_wr_pluse==Add_rd_ungray + ) + Almost_full <=1; + else + Almost_full <=0; + +assign Fifo_full =Almost_full; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr <=0; + else if (Current_state==State_err_end) + Add_wr <=Add_wr_reg; + else if (Wr_en&&!Full) + Add_wr <=Add_wr +1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp <=0; + else if (Current_state==State_err_end) + Add_wr_jump_tmp <=1; + else + Add_wr_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp_pl1 <=0; + else + Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump <=0; + else if (Current_state==State_err_end) + Add_wr_jump <=1; + else if (Add_wr_jump_tmp_pl1) + Add_wr_jump <=0; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_en_dl1 <=0; + else + Fifo_data_en_dl1 <=Fifo_data_en; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_dl1 <=0; + else + Fifo_data_dl1 <=Fifo_data; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte3 <=0; + else if (Current_state==State_byte3&&Fifo_data_en_dl1) + Fifo_data_byte3 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte2 <=0; + else if (Current_state==State_byte2&&Fifo_data_en_dl1) + Fifo_data_byte2 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte1 <=0; + else if (Current_state==State_byte1&&Fifo_data_en_dl1) + Fifo_data_byte1 <=Fifo_data_dl1; + +always @ (* ) + case (Current_state) + State_be0: + Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + State_be1: + Din_tmp ={4'b1001,Fifo_data_byte3,24'h0}; + State_be2: + Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0}; + State_be3: + Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0}; + default: + Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + endcase + +always @ (*) + if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3|| + (Current_state==State_byte0&&Fifo_data_en)) + Wr_en_tmp =1; + else + Wr_en_tmp =0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Din_tmp_reg <=0; + else if(Wr_en_tmp) + Din_tmp_reg <=Din_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Wr_en_ptr <=0; + else if(Current_state==State_idle) + Wr_en_ptr <=0; + else if(Wr_en_tmp) + Wr_en_ptr <=1; + +//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Wr_en <=0; + Din <=0; + end + else if(RX_APPEND_CRC) + begin + Wr_en <=Wr_en_tmp; + Din <=Din_tmp; + end + else + begin + Wr_en <=Wr_en_tmp&&Wr_en_ptr; + Din <={Din_tmp[35:32],Din_tmp_reg[31:0]}; + end + +//this signal for read side to handle the packet number in fifo +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add_tmp <=0; + else if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3) + Packet_number_add_tmp <=1; + else + Packet_number_add_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Packet_number_add_tmp_dl1 <=0; + Packet_number_add_tmp_dl2 <=0; + end + else + begin + Packet_number_add_tmp_dl1 <=Packet_number_add_tmp; + Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1; + end + +//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram. +//expand to two cycles long almost=16 ns +//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2) + Packet_number_add <=1; + else + Packet_number_add <=0; + + + + + + + + + + + + + + + + + + + + + + + + +//****************************************************************************** +//domain Clk_SYS,read data from dprom.b-port for read +//****************************************************************************** + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty) + case (Current_state_SYS) + SYS_idle: + if (Rx_mac_rd&&Rx_mac_ra&&!Empty) + Next_state_SYS =SYS_read; + else if(Rx_mac_rd&&Rx_mac_ra&&Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_read: + if (Dout[35]) + Next_state_SYS =SYS_wait_end; + else if (!Rx_mac_rd) + Next_state_SYS =SYS_pause; + else if (Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_pause: + if (Rx_mac_rd) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + FF_emtpy_err: + if (!Empty) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + SYS_wait_end: + if (!Rx_mac_rd) + Next_state_SYS =SYS_idle; + else + Next_state_SYS =Current_state_SYS; + default: + Next_state_SYS =SYS_idle; + endcase + + +//gen Rx_mac_ra +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_add_dl1 <=0; + Packet_number_add_dl2 <=0; + end + else + begin + Packet_number_add_dl1 <=Packet_number_add; + Packet_number_add_dl2 <=Packet_number_add_dl1; + end +assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2; + +always @ (Current_state_SYS or Next_state_SYS) + if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end) + Packet_number_sub =1; + else + Packet_number_sub =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add_edge&&!Packet_number_sub) + Packet_number_inFF <=Packet_number_inFF + 1; + else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0) + Packet_number_inFF <=Packet_number_inFF - 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else + Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_Hwmark_pl <=0; + Rx_Lwmark_pl <=0; + end + else + begin + Rx_Hwmark_pl <=Rx_Hwmark; + Rx_Lwmark_pl <=Rx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_ra <=0; + else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl) + Rx_mac_ra <=0; + else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl) + Rx_mac_ra <=1; + + +//control Add_rd signal; +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Add_rd <=Add_rd + 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_pl1 <=0; + else + Add_rd_pl1 <=Add_rd; + +always @(Add_rd_pl1,Add_rd) + if (Add_rd_pl1==Add_rd) + Addr_freshed_ptr =0; + else + Addr_freshed_ptr =1; + +// +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_rd_gray <=0; + else + begin + Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_jump_rd_pl1 <=0; + else + Add_wr_jump_rd_pl1 <=Add_wr_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else if (!Add_wr_jump_rd_pl1) + begin + Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end +//empty signal gen +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Dout_dl1 <=0; + else + Dout_dl1 <=Dout; + +assign Rx_mac_data =Dout_dl1[31:0]; +assign Rx_mac_BE =Dout_dl1[33:32]; +assign Rx_mac_eop =Dout_dl1[35]; + +//aligned to Addr_rd +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa_tmp <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Rx_mac_pa_tmp <=1; + else + Rx_mac_pa_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa <=0; + else + Rx_mac_pa <=Rx_mac_pa_tmp; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_sop_tmp <=0; + else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read) + Rx_mac_sop_tmp <=1; + else + Rx_mac_sop_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_mac_sop_tmp_dl1 <=0; + Rx_mac_sop <=0; + end + else + begin + Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp; + Rx_mac_sop <=Rx_mac_sop_tmp_dl1; + end + + + +//****************************************************************************** + +duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram( +.data_a (Din ), +.wren_a (Wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (Clk_MAC ), +.clock_b (Clk_SYS ), +.q_b (Dout )); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/New Folder =================================================================== --- sgmii/trunk/build/OpenCore_MAC/New Folder (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/New Folder (revision 26)

sgmii/trunk/build/OpenCore_MAC/New Folder Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/afifo.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/afifo.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/afifo.v (revision 26) @@ -0,0 +1,285 @@ +module afifo( +din, +wr_en, +wr_clk, +rd_en, +rd_clk, +ainit, +dout, +full, +almost_full, +empty, +wr_count, +rd_count, +rd_ack, +wr_ack); + +////////////////////////////////////////////////////// +parameter DATA_WIDTH =16; +parameter ADDR_WIDTH =8; +parameter COUNT_DATA_WIDTH =8; +parameter ALMOST_FULL_DEPTH =8; +////////////////////////////////////////////////////// +input [DATA_WIDTH-1:0] din; +input wr_en; +input wr_clk; +input rd_en; +input rd_clk; +input ainit; +output [DATA_WIDTH-1:0] dout; +output full; +output almost_full; +output empty; +output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */; +output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */; +output rd_ack; +output wr_ack; +////////////////////////////////////////////////////// +//local signals +////////////////////////////////////////////////////// +reg [ADDR_WIDTH-1:0] Add_wr; +reg [ADDR_WIDTH-1:0] Add_wr_ungray; +reg [ADDR_WIDTH-1:0] Add_wr_gray; +reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1; + +reg [ADDR_WIDTH-1:0] Add_rd; +wire [ADDR_WIDTH-1:0] Add_rd_pluse; +reg [ADDR_WIDTH-1:0] Add_rd_gray; +reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1; +reg [ADDR_WIDTH-1:0] Add_rd_ungray; +wire [ADDR_WIDTH-1:0] Add_wr_pluse; +integer i; +reg full /* synthesis syn_keep=1 */; +reg empty; +wire [ADDR_WIDTH-1:0] ff_used_wr; +wire [ADDR_WIDTH-1:0] ff_used_rd; +reg rd_ack; +reg rd_ack_tmp; +reg almost_full; +wire [DATA_WIDTH-1:0] dout_tmp; + +////////////////////////////////////////////////////// +//Write clock domain +////////////////////////////////////////////////////// +assign wr_ack =0; +assign ff_used_wr =Add_wr-Add_rd_ungray; + +assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH]; + + + + +always @ (posedge ainit or posedge wr_clk) + if (ainit) + Add_wr_gray <=0; + else + begin + Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +//��ַ��з�gray��. + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_rd_ungray =0; + else + begin + Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end + +assign Add_wr_pluse=Add_wr+1; + + +/* +always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + full =1; + else + full =0; + +*/ +always @ (posedge wr_clk or posedge ainit) + if (ainit) + full <=0; + else if(Add_wr_pluse==Add_rd_ungray&&wr_en) + full <=1; + else if(Add_wr!=Add_rd_ungray) + full <=0; + + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + almost_full <=0; + else if (wr_count>=ALMOST_FULL_DEPTH) + almost_full <=1; + else + almost_full <=0; + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_wr <=0; + else if (wr_en&&!full) + Add_wr <=Add_wr +1; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//****************************************************************************** +//read clock domain +//****************************************************************************** +always @ (posedge rd_clk or posedge ainit) + if (ainit) + rd_ack <=0; + else if (rd_en&&!empty) + rd_ack <=1; + else + rd_ack <=0; + + + +assign ff_used_rd =Add_wr_ungray-Add_rd; +assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH]; +assign Add_rd_pluse =Add_rd+1; + + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_rd <=0; + else if (rd_en&&!empty) //��EOP��Ͳ��ˡ� + Add_rd <=Add_rd + 1; + +//��ַ��gray��任. +always @ (posedge ainit or posedge rd_clk) + if (ainit) + Add_rd_gray <=0; + else + begin + Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +/* Add_rd_gray <={ Add_rd[8], + Add_rd[8]^Add_rd[7], + Add_rd[7]^Add_rd[6], + Add_rd[6]^Add_rd[5], + Add_rd[5]^Add_rd[4], + Add_rd[4]^Add_rd[3], + Add_rd[3]^Add_rd[2], + Add_rd[2]^Add_rd[1], + Add_rd[1]^Add_rd[0]}; +*/ +//д��ַ��з�gray��. + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_wr_ungray =0; + else + begin + Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end + +/* Add_wr_ungray <={ + Add_wr_gray_dl1[8], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] }; +*/ +//empty�źŲ�� +/* +always @ (Add_rd or Add_wr_ungray) + if (Add_rd==Add_wr_ungray) + empty =1; + else + empty =0; +*/ +always @ (posedge rd_clk or posedge ainit) + if (ainit) + empty <=1; + else if (Add_rd_pluse==Add_wr_ungray&&rd_en) + empty <=1; + else if (Add_rd!=Add_wr_ungray) + empty <=0; + + + +////////////////////////////////////////////////////// +//instant need change for your own dpram +////////////////////////////////////////////////////// +duram #( +DATA_WIDTH, +ADDR_WIDTH +) +U_duram ( +.data_a (din ), +.wren_a (wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (wr_clk ), +.clock_b (rd_clk ), +.q_b (dout )); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_FF.v (revision 26) @@ -0,0 +1,752 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2008/08/17 11:41:30 maverickist +// no message +// +// Revision 1.5 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +//I'm afraid that the synchronization chain is not good enough +//add addr_rd_gray_dl2 + +module MAC_rx_FF ( +Reset , +Clk_MAC , +Clk_SYS , +//MAC_rx_ctrl interface +Fifo_data , +Fifo_data_en , +Fifo_full , +Fifo_data_err , +Fifo_data_end , +//CPU +Rx_Hwmark, +Rx_Lwmark, +RX_APPEND_CRC, +//user interface +Rx_mac_ra , +Rx_mac_rd , +Rx_mac_data , +Rx_mac_BE , +Rx_mac_sop , +Rx_mac_pa, +Rx_mac_eop +); +input Reset ; +input Clk_MAC ; +input Clk_SYS ; + //MAC_rx_ctrl interface +input [7:0] Fifo_data ; +input Fifo_data_en ; +output Fifo_full ; +input Fifo_data_err ; +input Fifo_data_end ; + //CPU +input RX_APPEND_CRC ; +input [4:0] Rx_Hwmark ; +input [4:0] Rx_Lwmark ; + //user interface +output Rx_mac_ra ;// +input Rx_mac_rd ; +output [31:0] Rx_mac_data ; +output [1:0] Rx_mac_BE ; +output Rx_mac_pa ; +output Rx_mac_sop ; +output Rx_mac_eop ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_byte3 =4'd0; +parameter State_byte2 =4'd1; +parameter State_byte1 =4'd2; +parameter State_byte0 =4'd3; +parameter State_be0 =4'd4; +parameter State_be3 =4'd5; +parameter State_be2 =4'd6; +parameter State_be1 =4'd7; +parameter State_err_end =4'd8; +parameter State_idle =4'd9; + +parameter SYS_read =3'd0; +parameter SYS_pause =3'd1; +parameter SYS_wait_end =3'd2; +parameter SYS_idle =3'd3; +parameter FF_emtpy_err =3'd4; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl2; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl2; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray; +reg [35:0] Din; +reg [35:0] Din_tmp; +reg [35:0] Din_tmp_reg; +wire[35:0] Dout; +reg Wr_en; +reg Wr_en_tmp; +reg Wr_en_ptr; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2; +reg Full; +reg Almost_full; +reg Empty /* synthesis syn_keep=1 */; +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [7:0] Fifo_data_byte0; +reg [7:0] Fifo_data_byte1; +reg [7:0] Fifo_data_byte2; +reg [7:0] Fifo_data_byte3; +reg Fifo_data_en_dl1; +reg [7:0] Fifo_data_dl1; +reg Rx_mac_sop_tmp ; +reg Rx_mac_sop ; +reg Rx_mac_ra ; +reg Rx_mac_pa ; + + + +reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */; +reg [2:0] Next_state_SYS ; +reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; +reg Packet_number_sub ; +wire Packet_number_add_edge; +reg Packet_number_add_dl1; +reg Packet_number_add_dl2; +reg Packet_number_add ; +reg Packet_number_add_tmp ; +reg Packet_number_add_tmp_dl1; +reg Packet_number_add_tmp_dl2; + +reg Rx_mac_sop_tmp_dl1; +reg [35:0] Dout_dl1; +reg [4:0] Fifo_data_count; +reg Rx_mac_pa_tmp ; +reg Add_wr_jump_tmp ; +reg Add_wr_jump_tmp_pl1 ; +reg Add_wr_jump ; +reg Add_wr_jump_rd_pl1 ; +reg [4:0] Rx_Hwmark_pl ; +reg [4:0] Rx_Lwmark_pl ; +reg Addr_freshed_ptr ; +integer i ; +//****************************************************************************** +//domain Clk_MAC,write data to dprom.a-port for write +//****************************************************************************** +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end) + case (Current_state) + State_idle: + if (Fifo_data_en) + Next_state =State_byte3; + else + Next_state =Current_state; + State_byte3: + if (Fifo_data_en) + Next_state =State_byte2; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be1; + else + Next_state =Current_state; + State_byte2: + if (Fifo_data_en) + Next_state =State_byte1; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be2; + else + Next_state =Current_state; + State_byte1: + if (Fifo_data_en) + Next_state =State_byte0; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be3; + else + Next_state =Current_state; + State_byte0: + if (Fifo_data_en) + Next_state =State_byte3; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be0; + else + Next_state =Current_state; + State_be1: + Next_state =State_idle; + State_be2: + Next_state =State_idle; + State_be3: + Next_state =State_idle; + State_be0: + Next_state =State_idle; + State_err_end: + Next_state =State_idle; + default: + Next_state =State_idle; + endcase + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_reg <=0; + else if (Current_state==State_idle) + Add_wr_reg <=Add_wr; + +// + + +always @ (posedge Reset or posedge Clk_MAC) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) begin + Add_rd_gray_dl1 <=0; + Add_rd_gray_dl2 <=0; + end + else begin + Add_rd_gray_dl1 <=Add_rd_gray; + Add_rd_gray_dl2 <=Add_rd_gray_dl1; + end + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else + begin + //Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; + Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl2[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + //Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl2[i]; + end +assign Add_wr_pluse=Add_wr+1; +assign Add_wr_pluse4=Add_wr+4; +assign Add_wr_pluse3=Add_wr+3; +assign Add_wr_pluse2=Add_wr+2; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Full <=0; + else if (Add_wr_pluse==Add_rd_ungray) + Full <=1; + else + Full <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Almost_full <=0; + else if (Add_wr_pluse4==Add_rd_ungray|| + Add_wr_pluse3==Add_rd_ungray|| + Add_wr_pluse2==Add_rd_ungray|| + Add_wr_pluse==Add_rd_ungray + ) + Almost_full <=1; + else + Almost_full <=0; + +assign Fifo_full =Almost_full; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr <=0; + else if (Current_state==State_err_end) + Add_wr <=Add_wr_reg; + else if (Wr_en&&!Full) + Add_wr <=Add_wr +1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp <=0; + else if (Current_state==State_err_end) + Add_wr_jump_tmp <=1; + else + Add_wr_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp_pl1 <=0; + else + Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump <=0; + else if (Current_state==State_err_end) + Add_wr_jump <=1; + else if (Add_wr_jump_tmp_pl1) + Add_wr_jump <=0; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_en_dl1 <=0; + else + Fifo_data_en_dl1 <=Fifo_data_en; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_dl1 <=0; + else + Fifo_data_dl1 <=Fifo_data; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte3 <=0; + else if (Current_state==State_byte3&&Fifo_data_en_dl1) + Fifo_data_byte3 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte2 <=0; + else if (Current_state==State_byte2&&Fifo_data_en_dl1) + Fifo_data_byte2 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte1 <=0; + else if (Current_state==State_byte1&&Fifo_data_en_dl1) + Fifo_data_byte1 <=Fifo_data_dl1; + +always @ (* ) + case (Current_state) + State_be0: + Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + State_be1: + Din_tmp ={4'b1001,Fifo_data_byte3,24'h0}; + State_be2: + Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0}; + State_be3: + Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0}; + default: + Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + endcase + +always @ (*) + if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3|| + (Current_state==State_byte0&&Fifo_data_en)) + Wr_en_tmp =1; + else + Wr_en_tmp =0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Din_tmp_reg <=0; + else if(Wr_en_tmp) + Din_tmp_reg <=Din_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Wr_en_ptr <=0; + else if(Current_state==State_idle) + Wr_en_ptr <=0; + else if(Wr_en_tmp) + Wr_en_ptr <=1; + +//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Wr_en <=0; + Din <=0; + end + else if(RX_APPEND_CRC) + begin + Wr_en <=Wr_en_tmp; + Din <=Din_tmp; + end + else + begin + Wr_en <=Wr_en_tmp&&Wr_en_ptr; + Din <={Din_tmp[35:32],Din_tmp_reg[31:0]}; + end + +//this signal for read side to handle the packet number in fifo +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add_tmp <=0; + else if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3) + Packet_number_add_tmp <=1; + else + Packet_number_add_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Packet_number_add_tmp_dl1 <=0; + Packet_number_add_tmp_dl2 <=0; + end + else + begin + Packet_number_add_tmp_dl1 <=Packet_number_add_tmp; + Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1; + end + +//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram. +//expand to two cycles long almost=16 ns +//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2) + Packet_number_add <=1; + else + Packet_number_add <=0; + + + + + + + + + + + + + + + + + + + + + + + + +//****************************************************************************** +//domain Clk_SYS,read data from dprom.b-port for read +//****************************************************************************** + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty) + case (Current_state_SYS) + SYS_idle: + if (Rx_mac_rd&&Rx_mac_ra&&!Empty) + Next_state_SYS =SYS_read; + else if(Rx_mac_rd&&Rx_mac_ra&&Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_read: + if (Dout[35]) + Next_state_SYS =SYS_wait_end; + else if (!Rx_mac_rd) + Next_state_SYS =SYS_pause; + else if (Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_pause: + if (Rx_mac_rd) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + FF_emtpy_err: + if (!Empty) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + SYS_wait_end: + if (!Rx_mac_rd) + Next_state_SYS =SYS_idle; + else + Next_state_SYS =Current_state_SYS; + default: + Next_state_SYS =SYS_idle; + endcase + + +//gen Rx_mac_ra +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_add_dl1 <=0; + Packet_number_add_dl2 <=0; + end + else + begin + Packet_number_add_dl1 <=Packet_number_add; + Packet_number_add_dl2 <=Packet_number_add_dl1; + end +assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2; + +always @ (Current_state_SYS or Next_state_SYS) + if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end) + Packet_number_sub =1; + else + Packet_number_sub =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add_edge&&!Packet_number_sub) + Packet_number_inFF <=Packet_number_inFF + 1; + else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0) + Packet_number_inFF <=Packet_number_inFF - 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else + Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_Hwmark_pl <=0; + Rx_Lwmark_pl <=0; + end + else + begin + Rx_Hwmark_pl <=Rx_Hwmark; + Rx_Lwmark_pl <=Rx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_ra <=0; + else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl) + Rx_mac_ra <=0; + else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl) + Rx_mac_ra <=1; + + +//control Add_rd signal; +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Add_rd <=Add_rd + 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_pl1 <=0; + else + Add_rd_pl1 <=Add_rd; + +always @(Add_rd_pl1,Add_rd) + if (Add_rd_pl1==Add_rd) + Addr_freshed_ptr =0; + else + Addr_freshed_ptr =1; + +// +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_rd_gray <=0; + else + begin + Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) begin + Add_wr_gray_dl1 <=0; + Add_wr_gray_dl2 <=0; + end + else begin + Add_wr_gray_dl1 <=Add_wr_gray; + Add_wr_gray_dl2 <=Add_wr_gray_dl1; + end + +//Jeff added second synchronizer +reg Add_wr_jump_rd_pl2; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) begin + Add_wr_jump_rd_pl1 <=0; + Add_wr_jump_rd_pl2 <=0; end + else begin + Add_wr_jump_rd_pl1 <=Add_wr_jump; + Add_wr_jump_rd_pl2 <= Add_wr_jump_rd_pl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_ungray =0; + //else if (!Add_wr_jump_rd_pl1) + else if (!Add_wr_jump_rd_pl2) + begin + //Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1]; + Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl2[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + //Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl2[i]; + end +//empty signal gen +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Dout_dl1 <=0; + else + Dout_dl1 <=Dout; + +assign Rx_mac_data =Dout_dl1[31:0]; +assign Rx_mac_BE =Dout_dl1[33:32]; +assign Rx_mac_eop =Dout_dl1[35]; + +//aligned to Addr_rd +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa_tmp <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Rx_mac_pa_tmp <=1; + else + Rx_mac_pa_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa <=0; + else + Rx_mac_pa <=Rx_mac_pa_tmp; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_sop_tmp <=0; + else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read) + Rx_mac_sop_tmp <=1; + else + Rx_mac_sop_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_mac_sop_tmp_dl1 <=0; + Rx_mac_sop <=0; + end + else + begin + Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp; + Rx_mac_sop <=Rx_mac_sop_tmp_dl1; + end + + + +//****************************************************************************** + +duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram( +.data_a (Din ), +.wren_a (Wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (Clk_MAC ), +.clock_b (Clk_SYS ), +.q_b (Dout )); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/eth_clockgen.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/eth_clockgen.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/eth_clockgen.v (revision 26) @@ -0,0 +1,140 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clockgen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:55 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + +module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) + +output Mdc; // Output clock +output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. +output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. + +reg Mdc; +reg [7:0] Counter; + +wire CountEq0; +wire [7:0] CounterPreset; +wire [7:0] TempDivider; + + +assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 +assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period + + +// Counter counts half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Counter[7:0] <= #Tp 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= #Tp CounterPreset[7:0]; + end + else + Counter[7:0] <= #Tp Counter - 8'h1; + end +end + + +// Mdc is asserted every other half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Mdc <= #Tp 1'b0; + else + begin + if(CountEq0) + Mdc <= #Tp ~Mdc; + end +end + + +assign CountEq0 = Counter == 8'h0; +assign MdcEn = CountEq0 & ~Mdc; +assign MdcEn_n = CountEq0 & Mdc; + +endmodule + + Index: sgmii/trunk/build/OpenCore_MAC/MAC_tx_FF.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_tx_FF.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_tx_FF.v (revision 26) @@ -0,0 +1,794 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:39 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +`include "header.v" + +module MAC_tx_FF ( +Reset , +Clk_MAC , +Clk_SYS , +//MAC_rx_ctrl interface +Fifo_data , +Fifo_rd , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_eop , +Fifo_da , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//user interface +Tx_mac_wa , +Tx_mac_wr , +Tx_mac_data , +Tx_mac_BE , +Tx_mac_sop , +Tx_mac_eop , +//host interface +FullDuplex , +Tx_Hwmark , +Tx_Lwmark + +); +input Reset ; +input Clk_MAC ; +input Clk_SYS ; + //MAC_tx_ctrl +output [7:0] Fifo_data ; +input Fifo_rd ; +input Fifo_rd_finish ; +input Fifo_rd_retry ; +output Fifo_eop ; +output Fifo_da ; +output Fifo_ra ; +output Fifo_data_err_empty ; +output Fifo_data_err_full ; + //user interface +output Tx_mac_wa ; +input Tx_mac_wr ; +input [31:0] Tx_mac_data ; +input [1:0] Tx_mac_BE ;//big endian +input Tx_mac_sop ; +input Tx_mac_eop ; + //host interface +input FullDuplex ; +input [4:0] Tx_Hwmark ; +input [4:0] Tx_Lwmark ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter MAC_byte3 =4'd00; +parameter MAC_byte2 =4'd01; +parameter MAC_byte1 =4'd02; +parameter MAC_byte0 =4'd03; +parameter MAC_wait_finish =4'd04; +parameter MAC_retry =4'd08; +parameter MAC_idle =4'd09; +parameter MAC_FFEmpty =4'd10; +parameter MAC_FFEmpty_drop =4'd11; +parameter MAC_pkt_sub =4'd12; +parameter MAC_FF_Err =4'd13; + + +reg [3:0] Current_state_MAC /* synthesis syn_preserve =1 */ ; +reg [3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */ ; +reg [3:0] Next_state_MAC ; + + +parameter SYS_idle =4'd0; +parameter SYS_WaitSop =4'd1; +parameter SYS_SOP =4'd2; +parameter SYS_MOP =4'd3; +parameter SYS_DROP =4'd4; +parameter SYS_EOP_ok =4'd5; +parameter SYS_FFEmpty =4'd6; +parameter SYS_EOP_err =4'd7; +parameter SYS_SOP_err =4'd8; + +reg [3:0] Current_state_SYS /* synthesis syn_preserve =1 */; +reg [3:0] Next_state_SYS; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1 ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_tmp ; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1 ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_tmp ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray ; +wire[35:0] Din ; +wire[35:0] Dout ; +reg Wr_en ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse_pluse; +wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_pluse ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg_dl1 ; +reg Full /* synthesis syn_keep=1 */; +reg AlmostFull /* synthesis syn_keep=1 */; +reg Empty /* synthesis syn_keep=1 */; + +reg Tx_mac_wa ; +reg Tx_mac_wr_dl1 ; +reg [31:0] Tx_mac_data_dl1 ; +reg [1:0] Tx_mac_BE_dl1 ; +reg Tx_mac_sop_dl1 ; +reg Tx_mac_eop_dl1 ; +reg FF_FullErr ; +wire[1:0] Dout_BE ; +wire Dout_eop ; +wire Dout_err ; +wire[31:0] Dout_data ; +reg [35:0] Dout_reg /* synthesis syn_preserve=1 */; +reg Packet_number_sub_dl1 ; +reg Packet_number_sub_dl2 ; +reg Packet_number_sub_edge /* synthesis syn_preserve=1 */; +reg Packet_number_add /* synthesis syn_preserve=1 */; +reg [4:0] Fifo_data_count ; +reg Fifo_ra /* synthesis syn_keep=1 */; +reg [7:0] Fifo_data ; +reg Fifo_da ; +reg Fifo_data_err_empty /* synthesis syn_preserve=1 */; +reg Fifo_eop ; +reg Fifo_rd_dl1 ; +reg Fifo_ra_tmp ; +reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; +reg [5:0] Packet_number_inFF_reg /* synthesis syn_preserve=1 */; +reg Pkt_sub_apply_tmp ; +reg Pkt_sub_apply ; +reg Add_rd_reg_rdy_tmp ; +reg Add_rd_reg_rdy ; +reg Add_rd_reg_rdy_dl1 ; +reg Add_rd_reg_rdy_dl2 ; +reg [4:0] Tx_Hwmark_pl ; +reg [4:0] Tx_Lwmark_pl ; +reg Add_rd_jump_tmp ; +reg Add_rd_jump_tmp_pl1 ; +reg Add_rd_jump ; +reg Add_rd_jump_wr_pl1 ; + +integer i ; +//****************************************************************************** +//write data to from FF . +//domain Clk_SYS +//****************************************************************************** +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull + or Tx_mac_eop ) + case (Current_state_SYS) + SYS_idle: + if (Tx_mac_wr&&Tx_mac_sop&&!Full) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =Current_state_SYS ; + SYS_SOP: + Next_state_SYS =SYS_MOP; + SYS_MOP: + if (AlmostFull) + Next_state_SYS =SYS_DROP; + else if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP_err; + else if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_ok; + else + Next_state_SYS =Current_state_SYS ; + SYS_EOP_ok: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_EOP_err: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_SOP_err: + Next_state_SYS =SYS_DROP; + SYS_DROP: //FIFO overflow + if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_err; + else + Next_state_SYS =Current_state_SYS ; + default: + Next_state_SYS =SYS_idle; + endcase + +//delay signals +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_mac_wr_dl1 <=0; + Tx_mac_data_dl1 <=0; + Tx_mac_BE_dl1 <=0; + Tx_mac_sop_dl1 <=0; + Tx_mac_eop_dl1 <=0; + end + else + begin + Tx_mac_wr_dl1 <=Tx_mac_wr ; + Tx_mac_data_dl1 <=Tx_mac_data ; + Tx_mac_BE_dl1 <=Tx_mac_BE ; + Tx_mac_sop_dl1 <=Tx_mac_sop ; + Tx_mac_eop_dl1 <=Tx_mac_eop ; + end + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err) + FF_FullErr =1; + else + FF_FullErr =0; + +reg Tx_mac_eop_gen; + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok) + Tx_mac_eop_gen =1; + else + Tx_mac_eop_gen =0; + +assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1}; + +always @(Current_state_SYS or Tx_mac_wr_dl1) + if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok|| + Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1) + Wr_en = 1; + else + Wr_en = 0; + + +// + + +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +// + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_jump_wr_pl1 <=0; + else + Add_rd_jump_wr_pl1 <=Add_rd_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else if (!Add_rd_jump_wr_pl1) + begin + Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end +assign Add_wr_pluse =Add_wr+1; +assign Add_wr_pluse_pluse =Add_wr+4; + +always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + Full =1; + else + Full =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + AlmostFull <=0; + else if (Add_wr_pluse_pluse==Add_rd_ungray) + AlmostFull <=1; + else + AlmostFull <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr <= 0; + else if (Wr_en&&!Full) + Add_wr <= Add_wr +1; + + +// +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_sub_dl1 <=0; + Packet_number_sub_dl2 <=0; + end + else + begin + Packet_number_sub_dl1 <=Pkt_sub_apply; + Packet_number_sub_dl2 <=Packet_number_sub_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_sub_edge <=0; + else if (Packet_number_sub_dl1&!Packet_number_sub_dl2) + Packet_number_sub_edge <=1; + else + Packet_number_sub_edge <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err) + Packet_number_add <=1; + else + Packet_number_add <=0; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add&&!Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF + 1'b1; + else if (!Packet_number_add&&Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF - 1'b1; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF_reg <=0; + else + Packet_number_inFF_reg <=Packet_number_inFF; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Add_rd_reg_rdy_dl1 <=0; + Add_rd_reg_rdy_dl2 <=0; + end + else + begin + Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy; + Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_reg_dl1 <=0; + else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2) + Add_rd_reg_dl1 <=Add_rd_reg; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else if (FullDuplex) + Fifo_data_count <=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; + else + Fifo_data_count <=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_reg_dl1[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; //for half duplex backoff requirement + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_ra_tmp <=0; + else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark) + Fifo_ra_tmp <=1; + else + Fifo_ra_tmp <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_Hwmark_pl <=0; + Tx_Lwmark_pl <=0; + end + else + begin + Tx_Hwmark_pl <=Tx_Hwmark; + Tx_Lwmark_pl <=Tx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Tx_mac_wa <=0; + else if (Fifo_data_count>=Tx_Hwmark_pl) + Tx_mac_wa <=0; + else if (Fifo_data_count=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else + begin + Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end +//empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + +//ra +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_ra <=0; + else + Fifo_ra <=Fifo_ra_tmp; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply_tmp <=0; + else if (Current_state_MAC==MAC_pkt_sub) + Pkt_sub_apply_tmp <=1; + else + Pkt_sub_apply_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply <=0; + else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp) + Pkt_sub_apply <=1; + else + Pkt_sub_apply <=0; + +//reg Add_rd for collison retry +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg <=0; + else if (Fifo_rd_finish) + Add_rd_reg <=Add_rd; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy_tmp <=0; + else if (Fifo_rd_finish) + Add_rd_reg_rdy_tmp <=1; + else + Add_rd_reg_rdy_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy <=0; + else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp) + Add_rd_reg_rdy <=1; + else + Add_rd_reg_rdy <=0; + +reg Add_rd_add /* synthesis syn_keep=1 */; + +always @ (Current_state_MAC or Next_state_MAC) + if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3) + Add_rd_add =1; + else + Add_rd_add =0; + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd <= Add_rd_reg; + else if (Add_rd_add) + Add_rd <= Add_rd + 1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump_tmp <=1; + else + Add_rd_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp_pl1 <=0; + else + Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump <=1; + else if (Add_rd_jump_tmp_pl1) + Add_rd_jump <=0; + +//gen Fifo_data + + +always @ (Dout_data or Current_state_MAC) + case (Current_state_MAC) + MAC_byte3: + Fifo_data =Dout_data[31:24]; + MAC_byte2: + Fifo_data =Dout_data[23:16]; + MAC_byte1: + Fifo_data =Dout_data[15:8]; + MAC_byte0: + Fifo_data =Dout_data[7:0]; + default: + Fifo_data =0; + endcase +//gen Fifo_da +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_rd_dl1 <=0; + else + Fifo_rd_dl1 <=Fifo_rd; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_da <=0; + else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1|| + Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop) + Fifo_da <=1; + else + Fifo_da <=0; + +//gen Fifo_data_err_empty +assign Fifo_data_err_full=Dout_err; +//gen Fifo_data_err_empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state_MAC_reg <=0; + else + Current_state_MAC_reg <=Current_state_MAC; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_err_empty <=0; + else if (Current_state_MAC_reg==MAC_FFEmpty) + Fifo_data_err_empty <=1; + else + Fifo_data_err_empty <=0; + +//pragma synthesis_off +always @ (posedge Clk_MAC) + if (Current_state_MAC_reg==MAC_FF_Err) + begin + //$finish(2); + //$display("mac_tx_FF meet error status at time :%t",$time); + end +//pragma synthesis_on + +//gen Fifo_eop aligned to last valid data byte�� +always @ (Current_state_MAC or Dout_eop) + if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00|| + Current_state_MAC==MAC_byte1&&Dout_BE==2'b11|| + Current_state_MAC==MAC_byte2&&Dout_BE==2'b10|| + Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop)) + Fifo_eop =1; + else + Fifo_eop =0; +//****************************************************************************** +//****************************************************************************** + +duram #(36,`MAC_TX_FF_DEPTH,"M4K") U_duram( +.data_a (Din ), +.wren_a (Wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (Clk_SYS ), +.clock_b (Clk_MAC ), +.q_b (Dout )); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v.bak (revision 26) @@ -0,0 +1,533 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_ctrl ( +Reset , +Clk , +//RMII interface +MCrs_dv , // +MRxD , // +MRxErr , // +//CRC_chk interface +CRC_en , +CRC_init , +CRC_err , +//MAC_rx_add_chk interface +MAC_add_en , +MAC_rx_add_chk_err , +//broadcast_filter +broadcast_ptr , +broadcast_drop , +//flow_control signals +pause_quanta , +pause_quanta_val , +//MAC_rx_FF interface +Fifo_data , +Fifo_data_en , +Fifo_data_err , +Fifo_data_end , +Fifo_full , +//RMON interface +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon , +//CPU +RX_IFG_SET , +RX_MAX_LENGTH, +RX_MIN_LENGTH +); + +input Reset ; +input Clk ; + //RMII interface +input MCrs_dv ; +input [7:0] MRxD ; +input MRxErr ; + //CRC_chk interface +output CRC_en ; +output CRC_init; +input CRC_err ; + //MAC_rx_add_chk interface +output MAC_add_en ; +input MAC_rx_add_chk_err ; + //broadcast_filter +output broadcast_ptr ; +input broadcast_drop ; + //flow_control signals +output [15:0] pause_quanta ; +output pause_quanta_val ; + //MAC_rx_FF interface +output [7:0] Fifo_data ; +output Fifo_data_en ; +output Fifo_data_err ; +output Fifo_data_end ; +input Fifo_full; + //RMON interface +output [15:0] Rx_pkt_length_rmon ; +output Rx_apply_rmon ; +output [2:0] Rx_pkt_err_type_rmon ; +output [2:0] Rx_pkt_type_rmon ; + //CPU +input [5:0] RX_IFG_SET ; +input [15:0] RX_MAX_LENGTH ;// 1518 +input [6:0] RX_MIN_LENGTH ;// 64 + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_idle =4'd00; +parameter State_preamble =4'd01; +parameter State_SFD =4'd02; +parameter State_data =4'd03; +parameter State_checkCRC =4'd04; +parameter State_OkEnd =4'd07; +parameter State_drop =4'd08; +parameter State_ErrEnd =4'd09; +parameter State_CRCErrEnd =4'd10; +parameter State_FFFullDrop =4'd11; +parameter State_FFFullErrEnd =4'd12; +parameter State_IFG =4'd13; + +parameter Pause_idle =4'd0; +parameter Pause_pre_syn =4'd1; +parameter Pause_quanta_hi =4'd2; +parameter Pause_quanta_lo =4'd3; +parameter Pause_syn =4'd4; + +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [3:0] Pause_current /* synthesis syn_keep=1 */; +reg [3:0] Pause_next; +reg [5:0] IFG_counter; +reg Crs_dv ; +reg [7:0] RxD ; +reg [7:0] RxD_dl1 ; +reg RxErr ; +reg [15:0] Frame_length_counter; +reg Too_long; +reg Too_short; +reg Fifo_data_en; +reg Fifo_data_end; +reg Fifo_data_err; +reg CRC_en; +reg CRC_init; +reg Rx_apply_rmon; +reg Rx_apply_rmon_tmp; +reg Rx_apply_rmon_tmp_pl1; +reg [2:0] Rx_pkt_err_type_rmon; +reg MAC_add_en; +reg [2:0] Rx_pkt_type_rmon; +reg [7:0] pause_quanta_h ; +reg [15:0] pause_quanta ; +reg pause_quanta_val ; +reg pause_quanta_val_tmp; +reg pause_frame_ptr ; +reg broadcast_ptr ; +//****************************************************************************** +//delay signals +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + begin + Crs_dv <=0; + RxD <=0; + RxErr <=0; + end + else + begin + Crs_dv <=MCrs_dv ; + RxD <=MRxD ; + RxErr <=MRxErr ; + end + +always @ (posedge Reset or posedge Clk) + if (Reset) + RxD_dl1 <=0; + else + RxD_dl1 <=RxD; + +//****************************************************************************** +//State_machine +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + State_idle: + if (Crs_dv&&RxD==8'h55) + Next_state =State_preamble; + else + Next_state =Current_state; + State_preamble: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else if (RxD==8'hd5) + Next_state =State_SFD; + else if (RxD==8'h55) + Next_state =Current_state; + else + Next_state =State_drop; + State_SFD: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else + Next_state =State_data; + State_data: + if (!Crs_dv&&!Too_short&&!Too_long) + Next_state =State_checkCRC; + else if (!Crs_dv&&(Too_short||Too_long)) + Next_state =State_ErrEnd; + else if (Fifo_full) + Next_state =State_FFFullErrEnd; + else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop) + Next_state =State_drop; + else + Next_state =State_data; + State_checkCRC: + if (CRC_err) + Next_state =State_CRCErrEnd; + else + Next_state =State_OkEnd; + State_drop: + if (!Crs_dv) + Next_state =State_ErrEnd; + else + Next_state =Current_state; + State_OkEnd: + Next_state =State_IFG; + State_ErrEnd: + Next_state =State_IFG; + + State_CRCErrEnd: + Next_state =State_IFG; + State_FFFullDrop: + if (!Crs_dv) + Next_state =State_IFG; + else + Next_state =Current_state; + State_FFFullErrEnd: + Next_state =State_FFFullDrop; + State_IFG: + if (IFG_counter==RX_IFG_SET-4) //remove some additional time + Next_state =State_idle; + else + Next_state =Current_state; + + default: + Next_state =State_idle; + endcase + + +always @ (posedge Reset or posedge Clk) + if (Reset) + IFG_counter <=0; + else if (Current_state!=State_IFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; +//****************************************************************************** +//gen fifo interface signals +//****************************************************************************** + +assign Fifo_data =RxD_dl1; + +always @(Current_state) + if (Current_state==State_data) + Fifo_data_en =1; + else + Fifo_data_en =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_OkEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_end =1; + else + Fifo_data_end =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_err =1; + else + Fifo_data_err =0; + +//****************************************************************************** +//CRC_chk interface +//****************************************************************************** + +always @(Current_state) + if (Current_state==State_data) + CRC_en =1; + else + CRC_en =0; + +always @(Current_state) + if (Current_state==State_SFD) + CRC_init =1; + else + CRC_init =0; + +//****************************************************************************** +//gen rmon signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Frame_length_counter <=0; + else if (Current_state==State_SFD) + Frame_length_counter <=1; + else if (Current_state==State_data) + Frame_length_counter <=Frame_length_counter+ 1'b1; + +always @ (Frame_length_counter or RX_MIN_LENGTH) + if (Frame_length_counterRX_MAX_LENGTH) + Too_long =1; + else + Too_long =0; + +assign Rx_pkt_length_rmon=Frame_length_counter-1'b1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon_tmp <=1; + else + Rx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp_pl1 <=0; + else + Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon <=1; + else if (Rx_apply_rmon_tmp_pl1) + Rx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_err_type_rmon <=0; + else if (Current_state==State_CRCErrEnd) + Rx_pkt_err_type_rmon <=3'b001 ;// + else if (Current_state==State_FFFullErrEnd) + Rx_pkt_err_type_rmon <=3'b010 ;// + else if (Current_state==State_ErrEnd) + Rx_pkt_err_type_rmon <=3'b011 ;// + else if(Current_state==State_OkEnd) + Rx_pkt_err_type_rmon <=3'b100 ; + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_type_rmon <=0; + else if (Current_state==State_OkEnd&&pause_frame_ptr) + Rx_pkt_type_rmon <=3'b100 ;// + else if(Current_state==State_SFD&&Next_state==State_data) + Rx_pkt_type_rmon <={1'b0,MRxD[7:6]}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_ptr <=0; + else if(Current_state==State_IFG) + broadcast_ptr <=0; + else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11) + broadcast_ptr <=1; + + + +//****************************************************************************** +//MAC add checker signals +//****************************************************************************** +always @ (Frame_length_counter or Fifo_data_en) + if(Frame_length_counter>=1&&Frame_length_counter<=6) + MAC_add_en <=Fifo_data_en; + else + MAC_add_en <=0; + +//****************************************************************************** +//flow control signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Pause_current <=Pause_idle; + else + Pause_current <=Pause_next; + +always @ (*) + case (Pause_current) + Pause_idle : + if(Current_state==State_SFD) + Pause_next =Pause_pre_syn; + else + Pause_next =Pause_current; + Pause_pre_syn: + case (Frame_length_counter) + 16'd1: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd2: if (RxD_dl1==8'h80) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd3: if (RxD_dl1==8'hc2) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd4: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd5: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd6: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd13: if (RxD_dl1==8'h88) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd14: if (RxD_dl1==8'h08) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd15: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd16: if (RxD_dl1==8'h01) + Pause_next =Pause_quanta_hi; + else + Pause_next =Pause_idle; + default: Pause_next =Pause_current; + endcase + Pause_quanta_hi : + Pause_next =Pause_quanta_lo; + Pause_quanta_lo : + Pause_next =Pause_syn; + Pause_syn : + if (Current_state==State_IFG) + Pause_next =Pause_idle; + else + Pause_next =Pause_current; + default + Pause_next =Pause_idle; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_h <=0; + else if(Pause_current==Pause_quanta_hi) + pause_quanta_h <=RxD_dl1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta <=0; + else if(Pause_current==Pause_quanta_lo) + pause_quanta <={pause_quanta_h,RxD_dl1}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val_tmp <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn) + pause_quanta_val_tmp <=1; + else + pause_quanta_val_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp) + pause_quanta_val <=1; + else + pause_quanta_val <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_frame_ptr <=0; + else if(Pause_current==Pause_syn) + pause_frame_ptr <=1; + else + pause_frame_ptr <=0; + +endmodule + + \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v.bak (revision 26) @@ -0,0 +1,162 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clk_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Clk_ctrl( +Reset , +Clk_125M , +Clk_25M, +Clk_125M_90, +Clk_25M_90, +//host interface, +Speed , +//Phy interface , +Gtx_clk , +Rx_clk , +//Tx_clk , //Replace this clock by Clk_25M +//interface clk , +MAC_tx_clk_d , +MAC_tx_clk , +MAC_rx_clk , +MAC_tx_clk_div , +MAC_rx_clk_div +); +input Reset ; +input Clk_125M ; +input Clk_25M; +input Clk_125M_90; +input Clk_25M_90; + + //host interface +input [2:0] Speed ; + //Phy interface +output Gtx_clk ;//used only in GMII mode +input Rx_clk ; +//input Tx_clk ;//used only in MII mode + //interface clk signals +output MAC_tx_clk ; +output MAC_rx_clk ; +output MAC_tx_clk_div ; +output MAC_rx_clk_div ; +output MAC_tx_clk_d; + +//****************************************************************************** +//internal signals +//****************************************************************************** +wire Rx_clk_div2 ; +wire Tx_clk_div2 ; +wire transmit_clk; +wire clk_125_0; +wire clk_125_90; +wire clk_25_0; +wire clk_25_90; + +assign clk_125_0 = Clk_125M; +assign clk_25_0 = Clk_25M; +assign clk_125_90 = Clk_125M_90; +assign clk_25_90 = Clk_25M_90; + +//****************************************************************************** +// +//****************************************************************************** + +assign MAC_rx_clk = Rx_clk; +assign MAC_tx_clk = transmit_clk; +assign Gtx_clk = transmit_clk; + + + + +CLK_DIV2 U_0_CLK_DIV2( +.Reset (Reset ), +.IN (Rx_clk ), +.OUT (Rx_clk_div2 ) +); +// +CLK_DIV2 U_1_CLK_DIV2( +.Reset (Reset ), +.IN (clk_25_0 ), +.OUT (Tx_clk_div2 ) +); +// + +CLK_SWITCH U_0_CLK_SWITCH( +.IN_0 (Rx_clk_div2 ), +.IN_1 (Rx_clk ), +.SW (Speed[2] ), +.OUT (MAC_rx_clk_div ) +); + +// +CLK_SWITCH U_2_CLK_SWITCH( +.IN_0 (Tx_clk_div2 ), +.IN_1 (clk_125_0 ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_div ) +); + +CLK_SWITCH U_1_CLK_SWITCH( +.IN_0 (clk_25_0 ), +.IN_1 (clk_125_0 ), +.SW (Speed[2] ), +.OUT (transmit_clk ) +); + + +// +CLK_SWITCH U_3_CLK_SWITCH( +.IN_0 (clk_25_90 ), +.IN_1 (clk_125_90 ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_d) +); + + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/flow_ctrl.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/flow_ctrl.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/flow_ctrl.v (revision 26) @@ -0,0 +1,200 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// flow_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module flow_ctrl +( +Reset , +Clk , +//host processor , +tx_pause_en , +xoff_cpu , +xon_cpu , +//MAC_rx_flow , +pause_quanta , +pause_quanta_val , +//MAC_tx_ctrl , +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete + +); + +input Reset ; +input Clk ; + //host processor ; +input tx_pause_en ; +input xoff_cpu ; +input xon_cpu ; + //MAC_rx_flow ; +input [15:0] pause_quanta ; +input pause_quanta_val ; + //MAC_tx_ctrl ; +output pause_apply ; +input pause_quanta_sub ; +output xoff_gen ; +input xoff_gen_complete ; +output xon_gen ; +input xon_gen_complete ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg xoff_cpu_dl1 ; +reg xoff_cpu_dl2 ; +reg xon_cpu_dl1 ; +reg xon_cpu_dl2 ; +reg [15:0] pause_quanta_dl1 ; +reg pause_quanta_val_dl1 ; +reg pause_quanta_val_dl2 ; +reg pause_apply ; +reg xoff_gen ; +reg xon_gen ; +reg [15:0] pause_quanta_counter ; +reg tx_pause_en_dl1 ; +reg tx_pause_en_dl2 ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xoff_cpu_dl1 <=0; + xoff_cpu_dl2 <=0; + end + else + begin + xoff_cpu_dl1 <=xoff_cpu; + xoff_cpu_dl2 <=xoff_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xon_cpu_dl1 <=0; + xon_cpu_dl2 <=0; + end + else + begin + xon_cpu_dl1 <=xon_cpu; + xon_cpu_dl2 <=xon_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_dl1 <=0; + end + else + begin + pause_quanta_dl1 <=pause_quanta; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_val_dl1 <=0; + pause_quanta_val_dl2 <=0; + end + else + begin + pause_quanta_val_dl1 <=pause_quanta_val; + pause_quanta_val_dl2 <=pause_quanta_val_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + tx_pause_en_dl1 <=0; + tx_pause_en_dl2 <=0; + end + else + begin + tx_pause_en_dl1 <=tx_pause_en; + tx_pause_en_dl2 <=tx_pause_en_dl1; + end + +//****************************************************************************** +//gen output signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen <=0; + else if (xoff_gen_complete) + xoff_gen <=0; + else if (xoff_cpu_dl1&&!xoff_cpu_dl2) + xoff_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen <=0; + else if (xon_gen_complete) + xon_gen <=0; + else if (xon_cpu_dl1&&!xon_cpu_dl2) + xon_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_counter <=0; + else if(pause_quanta_val_dl1&&!pause_quanta_val_dl2) + pause_quanta_counter <=pause_quanta_dl1; + else if(pause_quanta_sub&&pause_quanta_counter!=0) + pause_quanta_counter <=pause_quanta_counter-1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_apply <=0; + else if(pause_quanta_counter==0) + pause_apply <=0; + else if (tx_pause_en_dl2) + pause_apply <=1; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/CRC_chk.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/CRC_chk.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/CRC_chk.v (revision 26) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_chk( +Reset , +Clk , +CRC_data , +CRC_init , +CRC_en , +//From CPU +CRC_chk_en , +CRC_err +); +input Reset ; +input Clk ; +input[7:0] CRC_data ; +input CRC_init ; +input CRC_en ; + //From CPU +input CRC_chk_en ; +output CRC_err ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [31:0] CRC_reg; +wire[31:0] Next_CRC; +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (CRC_init) + CRC_reg <=32'hffffffff; + else if (CRC_en) + CRC_reg <=NextCRC(CRC_data,CRC_reg); + +assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Clk_ctrl.v (revision 26) @@ -0,0 +1,166 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clk_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Clk_ctrl( +Reset , +Clk_125M , +Clk_25M, +Clk_125M_90, +Clk_25M_90, +//host interface, +Speed , +//Phy interface , +Gtx_clk , +Rx_clk , +//Tx_clk , //Replace this clock by Clk_25M +//interface clk , +MAC_tx_clk_d , +MAC_tx_clk , +MAC_rx_clk , +MAC_tx_clk_div , +MAC_rx_clk_div +); +input Reset ; +input Clk_125M ; +input Clk_25M; +input Clk_125M_90; +input Clk_25M_90; + + //host interface +input [2:0] Speed ; + //Phy interface +output Gtx_clk ;//used only in GMII mode +input Rx_clk ; +//input Tx_clk ;//used only in MII mode + //interface clk signals +output MAC_tx_clk ; +output MAC_rx_clk ; +output MAC_tx_clk_div ; +output MAC_rx_clk_div ; +output MAC_tx_clk_d; + +//****************************************************************************** +//internal signals +//****************************************************************************** +wire Rx_clk_div2 ; +wire Tx_clk_div2 ; +wire transmit_clk; +wire clk_125_0; +wire clk_125_90; +wire clk_25_0; +wire clk_25_90; + +assign clk_125_0 = Clk_125M; +assign clk_25_0 = Clk_25M; +assign clk_125_90 = Clk_125M_90; +assign clk_25_90 = Clk_25M_90; + +//****************************************************************************** +// +//****************************************************************************** + +assign MAC_rx_clk = Rx_clk; +assign MAC_tx_clk = transmit_clk; +assign Gtx_clk = transmit_clk; + + + + +CLK_DIV2 U_0_CLK_DIV2( +.Reset (Reset ), +.IN (Rx_clk ), +.OUT (Rx_clk_div2 ) +); +// +CLK_DIV2 U_1_CLK_DIV2( +.Reset (Reset ), +.IN (clk_25_0 ), +.OUT (Tx_clk_div2 ) +); +// + +CLK_SWITCH_ALT2 U_0_CLK_SWITCH( +.IN_0 (Rx_clk_div2 ), +.IN_1 (Rx_clk ), +.SW (Speed[2] ), +.OUT (MAC_rx_clk_div ) +); + +// +//CLK_SWITCH_ALT2 U_2_CLK_SWITCH( +//.IN_0 (Tx_clk_div2 ), +//.IN_1 (clk_125_0 ), +//.SW (Speed[2] ), +//.OUT ( ) +//); + +assign MAC_tx_clk_div = clk_125_0; + +//CLK_SWITCH_ALT2 U_1_CLK_SWITCH( +//.IN_0 (clk_25_0 ), +//.IN_1 (clk_125_0 ), +//.SW (Speed[2] ), +//.OUT (transmit_clk ) +//); + +assign transmit_clk = clk_125_0; + + +// +CLK_SWITCH_ALT2 U_3_CLK_SWITCH( +.IN_0 (clk_25_90 ), +.IN_1 (clk_125_90 ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_d) +); + + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/GbMAC_verify.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/GbMAC_verify.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/GbMAC_verify.v (revision 26) @@ -0,0 +1,401 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:49:28 06/15/2010 +// Design Name: +// Module Name: GbMAC_verify +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GbMAC_verify( + input PhyA_RxClk, + input PhyA_RxCtl, + input [3:0] PhyA_RxD, + output PhyA_TxClk, + output PhyA_TxCtl, + output [3:0] PhyA_TxD, + + + + output PhyB_TxClk, + output PhyB_TxCtl, + output [3:0] PhyB_TxD, + + input PhyC_RxClk, + input PhyC_RxCtl, + input [3:0] PhyC_RxD, + + output PhyC_TxClk, + output PhyC_TxCtl, + output [3:0] PhyC_TxD, + + + input V4_PCIXClk, + + output V4_Uart_Tx, + input V4_Uart_Rx, + + input V4_CLK_125M, + input V4_CLK_Sys, + input V4_rst_n +); + +// OPB BUS +wire [0:0] OPB_CS_n; +wire [11:0] OPB_Addr; +wire OPB_ADS; +wire [1:0] OPB_BE; +wire OPB_RnW; +wire OPB_Rd_n; +wire OPB_Wr_n; +wire OPB_Burst; +reg OPB_Rdy; +wire [15:0] OPB_Din; +wire [15:0] OPB_Dout; +wire [0:31] OPB_outD; +wire [0:31] OPB_inD; + + //MAC Module signals + wire [2:0] gEMAC_Speed; + //user interface RX + wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop; + reg Tx_wr; + reg Rx_rd; + wire [31:0] Rx_data, Tx_data; + wire [1:0] Rx_BE, Tx_BE; + wire pkt_length_fifo_rd, pkt_length_fifo_ra; + wire [15:0] pkt_length_fifo_data; + wire Carrier_Sense, Colision_Detect; + + //host interface + wire RxClk_MAC;//For MAC Receiver block + wire MAC_RegSelect; + wire MAC_RdnWr; + wire [15:0] MAC_RegDin; + wire [15:0] MAC_RegDout; + wire [7:0] MAC_RegAddr; + +//RGMII-GMII adaptation module + wire [7:0] GMII_TxD; + wire GMII_TxEN, GMII_TxER, GTx_Clk; + wire [7:0] GMII_RxD; + wire GMII_RxDV, GMII_RxER, GRx_Clk; + reg CE, Sync_Rst; + + wire [3:0] RGMII_RxD; + wire [3:0] RGMII_TxD; + wire RGMII_RxCtl, RGMII_RxClk; + wire RGMII_TxCtl, RGMII_TxClk; + + wire [3:0] RxPhyA_Stat; + + wire CLK_125M90; + wire CLK_125M; + wire CLK_25M; + wire V4_rst; + wire uB_rst; + reg pwr_on_rst; + wire MAC_Sysclk; + wire MAC_Regclk; + + reg one_sec_pulse; + reg [27:0] one_sec; + reg [31:0] rx_rate; + reg [31:0] rx_rate_reg; + + wire [0:0] ila_trig0, ila_trig1, ila_trig2; + wire [63:0] ila_data_bus; + wire [35:0] ila_control; + wire [23:0] MAC_Monitoring; + + wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout; + wire LoopbackFIFO_empty; + wire LoopbackFIFO_full; + wire LoopbackFIFO_wren; + reg LoopbackFIFO_rden; + + assign PhyA_TxD = 0;//RGMII_TxD; + assign PhyA_TxClk = 0;//RGMII_TxClk; + assign PhyA_TxCtl = 0;//RGMII_TxCtl; + assign PhyB_TxD = 0;//RGMII_TxD; + assign PhyB_TxClk = 0;//RGMII_TxClk; + assign PhyB_TxCtl = 0;//RGMII_TxCtl; + + assign PhyC_TxD = RGMII_TxD; + assign PhyC_TxClk = RGMII_TxClk; + assign PhyC_TxCtl = RGMII_TxCtl; + + assign RGMII_RxD = PhyC_RxD; + assign RGMII_RxCtl= PhyC_RxCtl; + assign RGMII_RxClk= PhyC_RxClk; + + assign CLK_66M = V4_PCIXClk; + + always@(posedge(CLK_125M)) + begin + if(!V4_rst_n) + begin + Sync_Rst <= 1; + CE <= 0; + end + else + begin + Sync_Rst <= 0; + CE <= 1; + end + end + + assign V4_rst = (~V4_rst_n)|pwr_on_rst; + assign uB_rst = ~ V4_rst; + +Clocks Clockings(.V4_Clk_125M(V4_CLK_125M),.V4_Clk_27M(),.V4_Clk_13M5(), + .Clk_125M(CLK_125M),.Clk_27M(),.Clk_13M5(),.Clk_25M(CLK_25M), + .Clk_125M_90(CLK_125M90), + .rst(0)); + + reg [3:0] pwr_on_cnt; + initial + begin + pwr_on_rst <= 1; + pwr_on_cnt <= 0; + end + always@(posedge CLK_125M) + begin + if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1; + if (pwr_on_cnt<15 && pwr_on_cnt>9) + pwr_on_rst <= 1; + else + pwr_on_rst <= 0; + end + + assign RxClkPhase = 0; + RGMII_GMII_Adaptation RGMIIAdp( + .Speed(gEMAC_Speed),.RxClkPhase(RxClkPhase), + .TxD(GMII_TxD), .TxEN(GMII_TxEN), .TxER(GMII_TxER), .TxClk(GTx_Clk), + .RxD(GMII_RxD), .RxDV(GMII_RxDV), .RxER(GMII_RxER), .RxClk(GRx_Clk), + .RGMII_TxD(RGMII_TxD), + .RGMII_TxCtl(RGMII_TxCtl), + .RGMII_TxClk(RGMII_TxClk), + .RGMII_RxD(RGMII_RxD), + .RGMII_RxCtl(RGMII_RxCtl), + .RGMII_RxClk(RGMII_RxClk), + .Status(RxPhyA_Stat), + .RxClk_MAC(RxClk_MAC), + .CE(CE), + .rst(V4_rst) + ); + + assign MAC_Sysclk = CLK_125M; +assign MAC_Regclk = CLK_66M; +//MAC Module +MAC_top gMAC( //system signals +.Reset(V4_rst), +.Clk_125M(CLK_125M), +.Clk_user(MAC_Sysclk), +.Clk_reg(MAC_Regclk), +.Clk_MACRx(RxClk_MAC), +.Speed(gEMAC_Speed), +//user interface RX +.Rx_mac_ra(Rx_ra), +.Rx_mac_rd(Rx_rd), +.Rx_mac_data(Rx_data), +.Rx_mac_BE(Rx_BE), +.Rx_mac_pa(Rx_pa), +.Rx_mac_sop(Rx_sop), +.Rx_mac_eop(Rx_eop), +//user interface +.Tx_mac_wa(Tx_wa), +.Tx_mac_wr(Tx_wr), +.Tx_mac_data(Tx_data), +.Tx_mac_BE(Tx_BE),//big endian +.Tx_mac_sop(Tx_sop), +.Tx_mac_eop(Tx_eop), +//pkg_lgth fifo +.Pkg_lgth_fifo_rd(pkt_length_fifo_rd), +.Pkg_lgth_fifo_ra(pkt_length_fifo_ra), +.Pkg_lgth_fifo_data(pkt_length_fifo_data), +//Phy interface +//Phy interface +.Gtx_clk(GTx_Clk),//used only in GMII mode +.Rx_clk(GRx_Clk), +.Tx_clk(CLK_25M),//used only in MII mode +.Tx_er(GMII_TxER), +.Tx_en(GMII_TxEN), +.Txd(GMII_TxD), +.Rx_er(GMII_RxER), +.Rx_dv(GMII_RxDV), +.Rxd(GMII_RxD), +.Crs(Carrier_Sense), +.Col(Colision_Detect), +//host interface +.CSB(MAC_RegSelect), +.WRB(MAC_RdnWr), +.CD_in(MAC_RegDin), +.CD_out(MAC_RegDout), +.CA(MAC_RegAddr), +.Monitoring(MAC_Monitoring), +//mdx +.Mdo(), // MII Management Data Output +.MdoEn(), // MII Management Data Output Enable +.Mdi(0), +.Mdc() // MII Management Data Clock +); + + LoopbackFIFO lpbff( + .clk(CLK_125M), + .din(LoopbackFIFO_din), + .rd_en(LoopbackFIFO_rden), + .wr_en(LoopbackFIFO_wren), + .dout(LoopbackFIFO_dout), + .empty(), + .full(), + .almost_empty(LoopbackFIFO_empty), + .almost_full(LoopbackFIFO_full)); + + assign LoopbackFIFO_din = {Rx_BE,Rx_sop,Rx_eop,Rx_data}; + assign LoopbackFIFO_wren= Rx_pa; + + //Route packet back to transmitter + assign Tx_data = LoopbackFIFO_dout[31:0]; + assign Tx_sop = LoopbackFIFO_dout[33]; + assign Tx_eop = LoopbackFIFO_dout[32]; + assign Tx_BE = LoopbackFIFO_dout[35:34]; + + assign MAC_RegSelect = OPB_CS_n; + assign MAC_RegDin = OPB_outD[0:15]; + assign OPB_inD = {MAC_RegDout,16'h0000}; + assign MAC_RegAddr = OPB_Addr[7:0]; + assign MAC_RdnWr = OPB_RnW; + + //Initializing machine + always@(posedge MAC_Regclk or posedge V4_rst) + begin + if(V4_rst) + begin + OPB_Rdy <= 0; + end + else + begin + OPB_Rdy <= ~OPB_CS_n; + end + end + + assign Carrier_Sense = 1; + assign Colision_Detect = 0; + + wire one_sec_pulse_long; + + assign one_sec_pulse_long = (one_sec>0 && one_sec<256)?1:0; + + always@(posedge MAC_Sysclk or posedge V4_rst) + if(V4_rst) + begin + one_sec <=0; + one_sec_pulse <= 0; + Rx_rd <= 0; + Tx_wr <= 0; + LoopbackFIFO_rden <= 0; + end + else + begin + if(one_sec == 125000000) one_sec <= 1; else one_sec <= one_sec+1; + if(one_sec == 125000000) one_sec_pulse <= 1; else one_sec_pulse <= 0; + if(one_sec_pulse) + begin + rx_rate <= 0; + rx_rate_reg <= rx_rate; + end + else + begin + if(Rx_sop) rx_rate <= rx_rate+1; + end + //start to read whenever data is available; + Rx_rd <= Rx_ra & (~LoopbackFIFO_full); + LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty); + Tx_wr <= LoopbackFIFO_rden; + end + + //Microblaze + uBlaze microBlaze + ( .uBlaze_Int(one_sec_pulse_long), + .fpga_0_RS232_req_to_send_pin(), + .fpga_0_RS232_RX_pin(V4_Uart_Rx), + .fpga_0_RS232_TX_pin(V4_Uart_Tx), + .sys_clk_pin(CLK_66M), + .sys_rst_pin(uB_rst), + .PRH_Clk_pin(CLK_66M), + .PRH_Rst_pin(V4_rst), + .PRH_CS_n_pin(OPB_CS_n), + .PRH_Addr_pin(OPB_Addr), + .PRH_ADS_pin(OPB_ADS), + .PRH_BE_pin(OPB_BE), + .PRH_RNW_pin(OPB_RnW), + .PRH_Rd_n_pin(OPB_Rd_n), + .PRH_Wr_n_pin(OPB_Wr_n), + .PRH_Burst_pin(OPB_Burst), + .PRH_Rdy_pin(OPB_Rdy), + .PRH_Data_I_pin(OPB_inD), + .PRH_Data_O_pin(OPB_outD), + .PRH_Data_T_pin()); + + //Monitoring + ila i_ila + ( + .control(ila_control), + .clk(CLK_125M), + .data(ila_data_bus), + .trig0(ila_trig0), + .trig1(ila_trig1), + .trig2(ila_trig2) + ); + + + + assign ila_data_bus[31:0] = {0,gEMAC_Speed,MAC_Monitoring}; + assign ila_data_bus[47:32] = {GMII_TxEN,GMII_TxER,GMII_TxD}; + assign ila_data_bus[63:48] = {0,LoopbackFIFO_empty,LoopbackFIFO_full,Tx_wr,Tx_wa,Rx_ra,Rx_pa,Rx_rd}; + assign ila_trig0 = Rx_rd; + assign ila_trig1 = Tx_wr; + assign ila_trig2 = LoopbackFIFO_full; + + icon i_icon + ( + .control0(ila_control) + ); + +endmodule + +module icon + ( + control0 + ); + output [35:0] control0; +endmodule + +module ila + ( + control, + clk, + data, + trig0, + trig1, + trig2 + ); + input [35:0] control; + input clk; + input [63:0] data; + input [0:0] trig0; + input [0:0] trig1; + input [0:0] trig2; +endmodule Index: sgmii/trunk/build/OpenCore_MAC/CLK_DIV2.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/CLK_DIV2.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/CLK_DIV2.v (revision 26) @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:42 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2_Wrapper ( +input Reset, +input IN, +output OUT +); + +// CLK_DIV2R CLK_DIV2R_inst ( +// .CLKDV(OUT), // Divided clock output +// .CDRST(Reset), // Synchronous reset input +// .CLKIN(IN) // Clock input +// ); + +reg clki; + + always@(posedge IN or posedge Reset) + begin + if(Reset) + clki <= 0; + else + clki <= ~clki; + end + + assign OUT = clki; + + + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx_ctrl.v (revision 26) @@ -0,0 +1,536 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Jeff Changes #1 + +module MAC_rx_ctrl ( +Reset , +Clk , +//RMII interface +MCrs_dv , // +MRxD , // +MRxErr , // +//CRC_chk interface +CRC_en , +CRC_init , +CRC_err , +//MAC_rx_add_chk interface +MAC_add_en , +MAC_rx_add_chk_err , +//broadcast_filter +broadcast_ptr , +broadcast_drop , +//flow_control signals +pause_quanta , +pause_quanta_val , +//MAC_rx_FF interface +Fifo_data , +Fifo_data_en , +Fifo_data_err , +Fifo_data_end , +Fifo_full , +//RMON interface +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon , +//CPU +RX_IFG_SET , +RX_MAX_LENGTH, +RX_MIN_LENGTH +); + +input Reset ; +input Clk ; + //RMII interface +input MCrs_dv ; +input [7:0] MRxD ; +input MRxErr ; + //CRC_chk interface +output CRC_en ; +output CRC_init; +input CRC_err ; + //MAC_rx_add_chk interface +output MAC_add_en ; +input MAC_rx_add_chk_err ; + //broadcast_filter +output broadcast_ptr ; +input broadcast_drop ; + //flow_control signals +output [15:0] pause_quanta ; +output pause_quanta_val ; + //MAC_rx_FF interface +output [7:0] Fifo_data ; +output Fifo_data_en ; +output Fifo_data_err ; +output Fifo_data_end ; +input Fifo_full; + //RMON interface +output [15:0] Rx_pkt_length_rmon ; +output Rx_apply_rmon ; +output [2:0] Rx_pkt_err_type_rmon ; +output [2:0] Rx_pkt_type_rmon ; + //CPU +input [5:0] RX_IFG_SET ; +input [15:0] RX_MAX_LENGTH ;// 1518 +input [6:0] RX_MIN_LENGTH ;// 64 + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_idle =4'd00; +parameter State_preamble =4'd01; +parameter State_SFD =4'd02; +parameter State_data =4'd03; +parameter State_checkCRC =4'd04; +parameter State_OkEnd =4'd07; +parameter State_drop =4'd08; +parameter State_ErrEnd =4'd09; +parameter State_CRCErrEnd =4'd10; +parameter State_FFFullDrop =4'd11; +parameter State_FFFullErrEnd =4'd12; +parameter State_IFG =4'd13; + +parameter Pause_idle =4'd0; +parameter Pause_pre_syn =4'd1; +parameter Pause_quanta_hi =4'd2; +parameter Pause_quanta_lo =4'd3; +parameter Pause_syn =4'd4; + +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [3:0] Pause_current /* synthesis syn_keep=1 */; +reg [3:0] Pause_next; +reg [5:0] IFG_counter; +reg Crs_dv ; +reg [7:0] RxD ; +reg [7:0] RxD_dl1 ; +reg RxErr ; +reg [15:0] Frame_length_counter; +reg Too_long; +reg Too_short; +reg Fifo_data_en; +reg Fifo_data_end; +reg Fifo_data_err; +reg CRC_en; +reg CRC_init; +reg Rx_apply_rmon; +reg Rx_apply_rmon_tmp; +reg Rx_apply_rmon_tmp_pl1; +reg [2:0] Rx_pkt_err_type_rmon; +reg MAC_add_en; +reg [2:0] Rx_pkt_type_rmon; +reg [7:0] pause_quanta_h ; +reg [15:0] pause_quanta ; +reg pause_quanta_val ; +reg pause_quanta_val_tmp; +reg pause_frame_ptr ; +reg broadcast_ptr ; +//****************************************************************************** +//delay signals +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + begin + Crs_dv <=0; + RxD <=0; + RxErr <=0; + end + else + begin + Crs_dv <=MCrs_dv ; + RxD <=MRxD ; + RxErr <=MRxErr ; + end + +always @ (posedge Reset or posedge Clk) + if (Reset) + RxD_dl1 <=0; + else + RxD_dl1 <=RxD; + +//****************************************************************************** +//State_machine +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + State_idle: + if (Crs_dv&&RxD==8'h55) + Next_state =State_preamble; + else + Next_state =Current_state; + State_preamble: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else if (RxD==8'hd5) + Next_state =State_SFD; + else if (RxD==8'h55) + Next_state =Current_state; + else + Next_state =State_drop; + State_SFD: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else + Next_state =State_data; + State_data: + if (!Crs_dv&&!Too_short&&!Too_long) + Next_state =State_checkCRC; + else if (!Crs_dv&&(Too_short||Too_long)) + Next_state =State_ErrEnd; + else if (Fifo_full) + Next_state =State_FFFullErrEnd; + //else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop) + //Jeff Changes #1 + else if ((Crs_dv&&RxErr)||MAC_rx_add_chk_err||Too_long||broadcast_drop) + Next_state =State_drop; + else + Next_state =State_data; + State_checkCRC: + if (CRC_err) + Next_state =State_CRCErrEnd; + else + Next_state =State_OkEnd; + State_drop: + if (!Crs_dv) + Next_state =State_ErrEnd; + else + Next_state =Current_state; + State_OkEnd: + Next_state =State_IFG; + State_ErrEnd: + Next_state =State_IFG; + + State_CRCErrEnd: + Next_state =State_IFG; + State_FFFullDrop: + if (!Crs_dv) + Next_state =State_IFG; + else + Next_state =Current_state; + State_FFFullErrEnd: + Next_state =State_FFFullDrop; + State_IFG: + if (IFG_counter==RX_IFG_SET-4) //remove some additional time + Next_state =State_idle; + else + Next_state =Current_state; + + default: + Next_state =State_idle; + endcase + + +always @ (posedge Reset or posedge Clk) + if (Reset) + IFG_counter <=0; + else if (Current_state!=State_IFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; +//****************************************************************************** +//gen fifo interface signals +//****************************************************************************** + +assign Fifo_data =RxD_dl1; + +always @(Current_state) + if (Current_state==State_data) + Fifo_data_en =1; + else + Fifo_data_en =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_OkEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_end =1; + else + Fifo_data_end =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_err =1; + else + Fifo_data_err =0; + +//****************************************************************************** +//CRC_chk interface +//****************************************************************************** + +always @(Current_state) + if (Current_state==State_data) + CRC_en =1; + else + CRC_en =0; + +always @(Current_state) + if (Current_state==State_SFD) + CRC_init =1; + else + CRC_init =0; + +//****************************************************************************** +//gen rmon signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Frame_length_counter <=0; + else if (Current_state==State_SFD) + Frame_length_counter <=1; + else if (Current_state==State_data) + Frame_length_counter <=Frame_length_counter+ 1'b1; + +always @ (Frame_length_counter or RX_MIN_LENGTH) + if (Frame_length_counterRX_MAX_LENGTH) + Too_long =1; + else + Too_long =0; + +assign Rx_pkt_length_rmon=Frame_length_counter-1'b1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon_tmp <=1; + else + Rx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp_pl1 <=0; + else + Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon <=1; + else if (Rx_apply_rmon_tmp_pl1) + Rx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_err_type_rmon <=0; + else if (Current_state==State_CRCErrEnd) + Rx_pkt_err_type_rmon <=3'b001 ;// + else if (Current_state==State_FFFullErrEnd) + Rx_pkt_err_type_rmon <=3'b010 ;// + else if (Current_state==State_ErrEnd) + Rx_pkt_err_type_rmon <=3'b011 ;// + else if(Current_state==State_OkEnd) + Rx_pkt_err_type_rmon <=3'b100 ; + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_type_rmon <=0; + else if (Current_state==State_OkEnd&&pause_frame_ptr) + Rx_pkt_type_rmon <=3'b100 ;// + else if(Current_state==State_SFD&&Next_state==State_data) + Rx_pkt_type_rmon <={1'b0,MRxD[7:6]}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_ptr <=0; + else if(Current_state==State_IFG) + broadcast_ptr <=0; + else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11) + broadcast_ptr <=1; + + + +//****************************************************************************** +//MAC add checker signals +//****************************************************************************** +always @ (Frame_length_counter or Fifo_data_en) + if(Frame_length_counter>=1&&Frame_length_counter<=6) + MAC_add_en <=Fifo_data_en; + else + MAC_add_en <=0; + +//****************************************************************************** +//flow control signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Pause_current <=Pause_idle; + else + Pause_current <=Pause_next; + +always @ (*) + case (Pause_current) + Pause_idle : + if(Current_state==State_SFD) + Pause_next =Pause_pre_syn; + else + Pause_next =Pause_current; + Pause_pre_syn: + case (Frame_length_counter) + 16'd1: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd2: if (RxD_dl1==8'h80) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd3: if (RxD_dl1==8'hc2) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd4: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd5: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd6: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd13: if (RxD_dl1==8'h88) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd14: if (RxD_dl1==8'h08) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd15: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd16: if (RxD_dl1==8'h01) + Pause_next =Pause_quanta_hi; + else + Pause_next =Pause_idle; + default: Pause_next =Pause_current; + endcase + Pause_quanta_hi : + Pause_next =Pause_quanta_lo; + Pause_quanta_lo : + Pause_next =Pause_syn; + Pause_syn : + if (Current_state==State_IFG) + Pause_next =Pause_idle; + else + Pause_next =Pause_current; + default + Pause_next =Pause_idle; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_h <=0; + else if(Pause_current==Pause_quanta_hi) + pause_quanta_h <=RxD_dl1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta <=0; + else if(Pause_current==Pause_quanta_lo) + pause_quanta <={pause_quanta_h,RxD_dl1}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val_tmp <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn) + pause_quanta_val_tmp <=1; + else + pause_quanta_val_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp) + pause_quanta_val <=1; + else + pause_quanta_val <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_frame_ptr <=0; + else if(Pause_current==Pause_syn) + pause_frame_ptr <=1; + else + pause_frame_ptr <=0; + +endmodule + + \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/RMON_addr_gen.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/RMON_addr_gen.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/RMON_addr_gen.v (revision 26) @@ -0,0 +1,292 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_addr_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_addr_gen( +Clk , +Reset , +//RMON +Pkt_type_rmon , +Pkt_length_rmon , +Apply_rmon ,//pluse signal looks like eop +Pkt_err_type_rmon , +// +Reg_apply , +Reg_addr , +Reg_data , +Reg_next , +//CPU +Reg_drop_apply +); +input Clk ; +input Reset ; + //RMON +input [2:0] Pkt_type_rmon ; +input [15:0] Pkt_length_rmon ; +input Apply_rmon ;//pluse signal looks like eop +input [2:0] Pkt_err_type_rmon ; + //RMON_ctrl +output Reg_apply ; +output [4:0] Reg_addr ; +output [15:0] Reg_data ; +input Reg_next ; + //CPU +output Reg_drop_apply ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd0; +parameter StatePktLength =4'd1; +parameter StatePktNumber =4'd2; +parameter StatePktType =4'd3; +parameter StatePktRange =4'd4; + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; + +reg [2:0] PktTypeReg ; +reg [15:0] PktLengthReg ; +reg [2:0] PktErrTypeReg ; + +reg Reg_apply ; +reg [4:0] Reg_addr ; +reg [15:0] Reg_data ; +reg Reg_drop_apply ; +//****************************************************************************** +//register boundery signals + +//****************************************************************************** +reg Apply_rmon_dl1; +reg Apply_rmon_dl2; +reg Apply_rmon_pulse; +reg [2:0] Pkt_type_rmon_dl1 ; +reg [15:0] Pkt_length_rmon_dl1 ; +reg [2:0] Pkt_err_type_rmon_dl1 ; + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Pkt_type_rmon_dl1 <=0; + Pkt_length_rmon_dl1 <=0; + Pkt_err_type_rmon_dl1 <=0; + end + else + begin + Pkt_type_rmon_dl1 <=Pkt_type_rmon ; + Pkt_length_rmon_dl1 <=Pkt_length_rmon ; + Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ; + end + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Apply_rmon_dl1 <=0; + Apply_rmon_dl2 <=0; + end + else + begin + Apply_rmon_dl1 <=Apply_rmon; + Apply_rmon_dl2 <=Apply_rmon_dl1; + end + +always @(Apply_rmon_dl1 or Apply_rmon_dl2) + if (Apply_rmon_dl1&!Apply_rmon_dl2) + Apply_rmon_pulse =1; + else + Apply_rmon_pulse =0; + + + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + PktTypeReg <=0; + PktLengthReg <=0; + PktErrTypeReg <=0; + end + else if (Apply_rmon_pulse&&CurrentState==StateIdle) + begin + PktTypeReg <=Pkt_type_rmon_dl1 ; + PktLengthReg <=Pkt_length_rmon_dl1 ; + PktErrTypeReg <=Pkt_err_type_rmon_dl1 ; + end + + +//****************************************************************************** +//State Machine +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateIdle; + else + CurrentState <=NextState; + +always @(CurrentState or Apply_rmon_pulse or Reg_next) + case (CurrentState) + StateIdle: + if (Apply_rmon_pulse) + NextState =StatePktLength; + else + NextState =StateIdle; + StatePktLength: + if (Reg_next) + NextState =StatePktNumber; + else + NextState =CurrentState; + StatePktNumber: + if (Reg_next) + NextState =StatePktType; + else + NextState =CurrentState; + StatePktType: + if (Reg_next) + NextState =StatePktRange; + else + NextState =CurrentState; + StatePktRange: + if (Reg_next) + NextState =StateIdle; + else + NextState =CurrentState; + default: + NextState =StateIdle; + endcase + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Reg_apply +always @ (CurrentState) + if (CurrentState==StatePktLength||CurrentState==StatePktNumber|| + CurrentState==StatePktType||CurrentState==StatePktRange) + Reg_apply =1; + else + Reg_apply =0; + +//Reg_addr +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_addr <=0; + else case (CurrentState) + StatePktLength: + Reg_addr <=5'd00; + StatePktNumber: + Reg_addr <=5'd01; + StatePktType: + case(PktTypeReg) + 3'b011: + Reg_addr <=5'd02; //broadcast + 3'b001: + Reg_addr <=5'd03; //multicast + 3'b100: + Reg_addr <=5'd16; //pause frame + default: + Reg_addr <=5'd04; //unicast + endcase + StatePktRange: + case(PktErrTypeReg) + 3'b001: + Reg_addr <=5'd05; + 3'b010: + Reg_addr <=5'd06; + 3'b011: + Reg_addr <=5'd07; + 3'b100: + if (PktLengthReg<64) + Reg_addr <=5'd08; + else if (PktLengthReg==64) + Reg_addr <=5'd09; + else if (PktLengthReg<128) + Reg_addr <=5'd10; + else if (PktLengthReg<256) + Reg_addr <=5'd11; + else if (PktLengthReg<512) + Reg_addr <=5'd12; + else if (PktLengthReg<1024) + Reg_addr <=5'd13; + else if (PktLengthReg<1519) + Reg_addr <=5'd14; + else + Reg_addr <=5'd15; + default: + Reg_addr <=5'd05; + endcase + default: + Reg_addr <=5'd05; + endcase + +//Reg_data +always @ (CurrentState or PktLengthReg) + case (CurrentState) + StatePktLength: + Reg_data =PktLengthReg; + StatePktNumber: + Reg_data =1; + StatePktType: + Reg_data =1; + StatePktRange: + Reg_data =1; + default: + Reg_data =0; + endcase + +//Reg_drop_apply +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_drop_apply <=0; + else if (CurrentState!=StateIdle&&Apply_rmon_pulse) + Reg_drop_apply <=1; + else + Reg_drop_apply <=0; + + +endmodule + Index: sgmii/trunk/build/OpenCore_MAC/RMON_dpram.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/RMON_dpram.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/RMON_dpram.v (revision 26) @@ -0,0 +1,46 @@ +module RMON_dpram( +Reset , +Clk , +//port-a for Rmon +Addra, +Dina, +Douta, +Wea, +//port-b for CPU +Addrb, +Doutb +); + +input Reset ; +input Clk ; + //port-a for Rmon +input [5:0] Addra; +input [31:0] Dina; +output [31:0] Douta; +input Wea; + //port-b for CPU +input [5:0] Addrb; +output [31:0] Doutb; +//****************************************************************************** +//internal signals +//****************************************************************************** + +wire Clka; +wire Clkb; +assign Clka=Clk; +assign #2 Clkb=Clk; +//****************************************************************************** + +duram #(32,6,"M4K") U_duram( +.data_a (Dina ), +.data_b (32'b0 ), +.wren_a (Wea ), +.wren_b (1'b0 ), +.address_a (Addra ), +.address_b (Addrb ), +.clock_a (Clka ), +.clock_b (Clkb ), +.q_a (Douta ), +.q_b (Doutb )); + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/loopbackFifo.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/loopbackFifo.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/loopbackFifo.v (revision 26) @@ -0,0 +1,162 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file LoopbackFIFO.v when simulating +// the core, LoopbackFIFO. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module LoopbackFIFO( + clk, + din, + rd_en, + wr_en, + almost_empty, + almost_full, + dout, + empty, + full); + + +input clk; +input [35 : 0] din; +input rd_en; +input wr_en; +output almost_empty; +output almost_full; +output [35 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V3_3 #( + .C_COMMON_CLOCK(1), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("virtex4"), + .C_HAS_ALMOST_EMPTY(1), + .C_HAS_ALMOST_FULL(1), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(0), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(1), + .C_PRELOAD_REGS(0), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(510), + .C_PROG_FULL_THRESH_NEGATE_VAL(509), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(100), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_ECC(0), + .C_USE_FIFO16_FLAGS(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(100), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .CLK(clk), + .DIN(din), + .RD_EN(rd_en), + .WR_EN(wr_en), + .ALMOST_EMPTY(almost_empty), + .ALMOST_FULL(almost_full), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_CLK(), + .RD_RST(), + .RST(), + .SRST(), + .WR_CLK(), + .WR_RST(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of LoopbackFIFO is "black_box" + +endmodule + Index: sgmii/trunk/build/OpenCore_MAC/RMON_ctrl.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/RMON_ctrl.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/RMON_ctrl.v (revision 26) @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_CTRL.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_CTRL ( +Clk , +Reset , +//RMON_CTRL +Reg_apply_0 , +Reg_addr_0 , +Reg_data_0 , +Reg_next_0 , +Reg_apply_1 , +Reg_addr_1 , +Reg_data_1 , +Reg_next_1 , +//dual-port ram +Addra , +Dina , +Douta , +Wea , +//CPU +CPU_rd_addr , +CPU_rd_apply , +CPU_rd_grant , +CPU_rd_dout + +); +input Clk ; +input Reset ; + //RMON_CTRL +input Reg_apply_0 ; +input [4:0] Reg_addr_0 ; +input [15:0] Reg_data_0 ; +output Reg_next_0 ; +input Reg_apply_1 ; +input [4:0] Reg_addr_1 ; +input [15:0] Reg_data_1 ; +output Reg_next_1 ; + //dual-port ram + //port-a for Rmon +output [5:0] Addra ; +output [31:0] Dina ; +input [31:0] Douta ; +output Wea ; + //CPU +input [5:0] CPU_rd_addr ; +input CPU_rd_apply ; +output CPU_rd_grant ; +output [31:0] CPU_rd_dout ; + + + + +//****************************************************************************** +//internal signals +//****************************************************************************** + +parameter StateCPU =4'd00; +parameter StateMAC0 =4'd01; +parameter StateMAC1 =4'd02; + + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; +reg [3:0] CurrentState_reg; + +reg [4:0] StepCounter; +reg [31:0] DoutaReg; +reg [5:0] Addra ; +reg [31:0] Dina; +reg Reg_next_0 ; +reg Reg_next_1 ; +reg Write; +reg Read; +reg Pipeline; +reg [31:0] CPU_rd_dout ; +reg CPU_rd_apply_reg ; +//****************************************************************************** +//State Machine +//****************************************************************************** + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateMAC0; + else + CurrentState <=NextState; + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState_reg <=StateMAC0; + else if(CurrentState!=StateCPU) + CurrentState_reg <=CurrentState; + +always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg + or Reg_apply_1 + or StepCounter + ) + case(CurrentState) + StateMAC0: + if(!Reg_apply_0&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_0) + NextState =StateMAC1; + else + NextState =CurrentState; + StateMAC1: + if(!Reg_apply_1&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_1) + NextState =StateMAC0; + else + NextState =CurrentState; + StateCPU: + if (StepCounter==3) + case (CurrentState_reg) + StateMAC0 :NextState =StateMAC0 ; + StateMAC1 :NextState =StateMAC1 ; + default :NextState =StateMAC0; + endcase + else + NextState =CurrentState; + + default: + NextState =StateMAC0; + endcase + + + +always @(posedge Clk or posedge Reset) + if (Reset) + StepCounter <=0; + else if(NextState!=CurrentState) + StepCounter <=0; + else if (StepCounter!=4'hf) + StepCounter <=StepCounter + 1; + +//****************************************************************************** +//temp signals +//****************************************************************************** +always @(StepCounter) + if( StepCounter==1||StepCounter==4|| + StepCounter==7||StepCounter==10) + Read =1; + else + Read =0; + +always @(StepCounter or CurrentState) + if( StepCounter==2||StepCounter==5|| + StepCounter==8||StepCounter==11) + Pipeline =1; + else + Pipeline =0; + +always @(StepCounter or CurrentState) + if( StepCounter==3||StepCounter==6|| + StepCounter==9||StepCounter==12) + Write =1; + else + Write =0; + +always @(posedge Clk or posedge Reset) + if (Reset) + DoutaReg <=0; + else if (Read) + DoutaReg <=Douta; + + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Addra +always @(*) + case(CurrentState) + StateMAC0 : Addra={1'd0 ,Reg_addr_0 }; + StateMAC1 : Addra={1'd1 ,Reg_addr_1 }; + StateCPU: Addra=CPU_rd_addr; + default: Addra=0; + endcase + +//Dina +always @(posedge Clk or posedge Reset) + if (Reset) + Dina <=0; + else + case(CurrentState) + StateMAC0 : Dina<=Douta+Reg_data_0 ; + StateMAC1 : Dina<=Douta+Reg_data_1 ; + StateCPU: Dina<=0; + default: Dina<=0; + endcase + +assign Wea =Write; +//Reg_next +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC0) + Reg_next_0 =Pipeline; + else + Reg_next_0 =0; + +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC1) + Reg_next_1 =Pipeline; + else + Reg_next_1 =0; + + +//CPU_rd_grant +reg CPU_rd_apply_dl1; +reg CPU_rd_apply_dl2; +//rising edge +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + CPU_rd_apply_dl1 <=0; + CPU_rd_apply_dl2 <=0; + end + else + begin + CPU_rd_apply_dl1 <=CPU_rd_apply; + CPU_rd_apply_dl2 <=CPU_rd_apply_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_apply_reg <=0; + else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2) + CPU_rd_apply_reg <=1; + else if (CurrentState==StateCPU&&Write) + CPU_rd_apply_reg <=0; + +assign CPU_rd_grant =!CPU_rd_apply_reg; + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_dout <=0; + else if (Pipeline&&CurrentState==StateCPU) + CPU_rd_dout <=Douta; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/eth_outputcontrol.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/eth_outputcontrol.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/eth_outputcontrol.v (revision 26) @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +parameter Tp = 1; + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= #Tp 1'b0; + MdoEn_d <= #Tp 1'b0; + MdoEn <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; + MdoEn_d <= #Tp MdoEn_2d; + MdoEn <= #Tp MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= #Tp 1'b0; + Mdo_d <= #Tp 1'b0; + Mdo <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= #Tp ~SerialEn & BitCounter<32; + Mdo_d <= #Tp ShiftedBit | Mdo_2d; + Mdo <= #Tp Mdo_d; + end + end +end + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_bb.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_bb.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_bb.v (revision 26) @@ -0,0 +1,131 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: lpbff.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module lpbff ( + clock, + data, + rdreq, + wrreq, + almost_empty, + almost_full, + empty, + full, + q); + + input clock; + input [35:0] data; + input rdreq; + input wrreq; + output almost_empty; + output almost_full; + output empty; + output full; + output [35:0] q; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "511" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "36" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "36" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2" +// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "511" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL data[35..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL q[35..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0 +// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.qip =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.qip (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.qip (revision 26) @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "9.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpbff.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpbff_bb.v"] Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_waveforms.html =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_waveforms.html (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_waveforms.html (revision 26) @@ -0,0 +1,16 @@ + + +Sample Waveforms for "lpbff.v" + + +

Sample behavioral waveforms for design file "lpbff.v"

The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpbff.v". The design "lpbff.v" has a depth of 512 words of 36 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

Fig. 1 : Wave showing read and write operation.

The above waveform shows the behavior of the design under normal read and write conditions .

Fig. 2 : Wave showing FIFO full operation.

The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.

+ + Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave0.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave0.jpg =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave0.jpg (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave0.jpg (revision 26)

sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave0.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave1.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave1.jpg =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave1.jpg (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave1.jpg (revision 26)

sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff_wave1.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF/lpbff.v (revision 26) @@ -0,0 +1,179 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: lpbff.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module lpbff ( + clock, + data, + rdreq, + wrreq, + almost_empty, + almost_full, + empty, + full, + q); + + input clock; + input [35:0] data; + input rdreq; + input wrreq; + output almost_empty; + output almost_full; + output empty; + output full; + output [35:0] q; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire [35:0] sub_wire3; + wire sub_wire4; + wire almost_full = sub_wire0; + wire empty = sub_wire1; + wire almost_empty = sub_wire2; + wire [35:0] q = sub_wire3[35:0]; + wire full = sub_wire4; + + scfifo scfifo_component ( + .rdreq (rdreq), + .clock (clock), + .wrreq (wrreq), + .data (data), + .almost_full (sub_wire0), + .empty (sub_wire1), + .almost_empty (sub_wire2), + .q (sub_wire3), + .full (sub_wire4) + // synopsys translate_off + , + .aclr (), + .sclr (), + .usedw () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.almost_empty_value = 2, + scfifo_component.almost_full_value = 511, + scfifo_component.intended_device_family = "Arria II GX", + scfifo_component.lpm_numwords = 512, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 36, + scfifo_component.lpm_widthu = 9, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "511" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "36" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "36" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2" +// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "511" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL data[35..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL q[35..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0 +// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpbff_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf Index: sgmii/trunk/build/OpenCore_MAC/LoopbackFF =================================================================== --- sgmii/trunk/build/OpenCore_MAC/LoopbackFF (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/LoopbackFF (revision 26)

sgmii/trunk/build/OpenCore_MAC/LoopbackFF Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx.v.bak (revision 26) @@ -0,0 +1,233 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +`include "header.v" + +module MAC_rx ( +output [23:0] Monitoring, +input Reset , +input Clk_user, +input Clk , + //RMII interface +input MCrs_dv , +input [7:0] MRxD , +input MRxErr , + //flow_control signals +output [15:0] pause_quanta , +output pause_quanta_val , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //CPU +input MAC_rx_add_chk_en , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input broadcast_filter_en , +input [15:0] broadcast_bucket_depth , +input [15:0] broadcast_bucket_interval , +input RX_APPEND_CRC, +input [4:0] Rx_Hwmark , +input [4:0] Rx_Lwmark , +input CRC_chk_en , +input [5:0] RX_IFG_SET , +input [15:0] RX_MAX_LENGTH ,// 1518 +input [6:0] RX_MIN_LENGTH ,// 64 + //RMON interface +output [15:0] Rx_pkt_length_rmon , +output Rx_apply_rmon , +output [2:0] Rx_pkt_err_type_rmon , +output [2:0] Rx_pkt_type_rmon +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_chk interface +wire CRC_en ; +wire CRC_init; +wire CRC_err ; + //MAC_rx_add_chk interface +wire MAC_add_en ; +wire MAC_rx_add_chk_err ; + //broadcast_filter +wire broadcast_ptr ; +wire broadcast_drop ; + //flow_control signals +//wire [15:0] pause_quanta ; +//wire pause_quanta_val ; + //MAC_rx_ctrl interface +wire [7:0] Fifo_data ; +wire Fifo_data_en ; +wire Fifo_full ; +wire Fifo_data_err ; +wire Fifo_data_end ; +//****************************************************************************** +//instantiation +//****************************************************************************** + +assign Monitoring = {0,Clk,MCrs_dv,MRxErr,Fifo_data_err,Fifo_data_end,Fifo_data_en,Fifo_full, + Fifo_data, + MRxD}; + +MAC_rx_ctrl U_MAC_rx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //RMII interface ( //RMII interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //CRC_chk interface (//CRC_chk interface ), +.CRC_en (CRC_en ), +.CRC_init (CRC_init ), +.CRC_err (CRC_err ), + //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //broadcast_filter (//broadcast_filter ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_rx_FF interface (//MAC_rx_FF interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), +.Fifo_full (Fifo_full ), + //RMON interface (//RMON interface ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ) +); + +MAC_rx_FF U_MAC_rx_FF ( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_full (Fifo_full ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), + //CPU (//CPU ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.RX_APPEND_CRC (RX_APPEND_CRC ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_eop (Rx_mac_eop ) +); + +`ifdef MAC_BROADCAST_FILTER_EN +Broadcast_filter U_Broadcast_filter( +.Reset (Reset ), +.Clk (Clk ), + //MAC_rx_ctrl (//MAC_rx_ctrl ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //FromCPU (//FromCPU ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ) +); +`else +assign broadcast_drop=0; +`endif + +CRC_chk U_CRC_chk( +.Reset (Reset ), +.Clk (Clk ), +.CRC_data (Fifo_data ), +.CRC_init (CRC_init ), +.CRC_en (CRC_en ), + //From CPU (//From CPU ), +.CRC_chk_en (CRC_chk_en ), +.CRC_err (CRC_err ) +); + +`ifdef MAC_TARGET_CHECK_EN +MAC_rx_add_chk U_MAC_rx_add_chk( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.data (Fifo_data ), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //From CPU (//From CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_add_prom_data ), +.MAC_add_prom_add (MAC_add_prom_add ), +.MAC_add_prom_wr (MAC_add_prom_wr ) +); +`else +assign MAC_rx_add_chk_err=0; +`endif + + + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/GbMAC.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/GbMAC.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/GbMAC.v.bak (revision 26) @@ -0,0 +1,492 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:49:28 06/15/2010 +// Design Name: +// Module Name: GbMAC_verify +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GbMAC( + input clk_125M, + input clk_25M, //10Mbps not supported + input clk_125M_90, + input clk_25M_90, + input MAC_Sysclk, //FIFO interface of MAC block + input MAC_Regclk, //Register interface of MAC block + + input cal_blk_clk, //calibration clock + input rstn, //hardware reset + input MACrst, //Software reset of mac + + + //MDIO interface + inout mdio, + output mdc, + + + //GMII interface + + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_TXClk, + input [7:0] GMII_RXD, + input GMII_RX_EN, + input GMII_RX_ER, + input GMII_RXClk, + + //SGMII interface + + output SGMII_Tx, + input SGMII_Rx, + + //RGMII interface + //RX + input RGMII_Rx_DV, + input [3:0] RGMII_Rx_D, + input RGMII_Rx_CLK, + //TX + output RGMII_Tx_CLK, + output RGMII_Tx_EN, + output [3:0] RGMII_Tx_D, + + //Host interface + input [7:0] address , + input read , + input write , + input [15:0] writedata , + output [15:0] readdata , + output waitreq , + + //status + output led_an , + output led_link , + output [2:0] Speed , + output reg [3:0] link_stat , + + output pktlen_fifo_ra , + output [15:0] pktlen_fifo_data , + input pktlen_fifo_rd , + + //PACKET Inteface + output Rx_mac_ra , + input Rx_mac_rd , + output [31:0] Rx_mac_data , + output [1:0] Rx_mac_BE , + output Rx_mac_pa , + output Rx_mac_sop , + output Rx_mac_eop , + //user interface + output Tx_mac_wa , + input Tx_mac_wr , + input [31:0] Tx_mac_data , + input [1:0] Tx_mac_BE ,//big endian + input Tx_mac_sop , + input Tx_mac_eop +); + + //clocks + wire CLK_125M_90; + wire CLK_125M; + wire CLK_25M; + wire CLK_25M_90; + + //MAC Module signals + wire [2:0] gEMAC_Speed; + + //user interface RX + wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop; + reg Tx_wr; + wire Rx_rd; + wire [31:0] Rx_data, Tx_data; + wire [1:0] Rx_BE, Tx_BE; + wire pkt_length_fifo_rd, pkt_length_fifo_ra; + wire [15:0] pkt_length_fifo_data; + + + //host interface + wire RxClk_MAC;//For MAC Receiver block + wire TxClk_MAC;//For MAC Transmitter block + wire MAC_RegSelect; + wire MAC_RdnWr; + wire [15:0] MAC_RegDin; + wire [15:0] MAC_RegDout; + wire [7:0] MAC_RegAddr; + wire MAC_RegWait; + wire MAC_rsti; + + wire sysrst; + reg pwr_on_rst; + + + wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout; + wire LoopbackFIFO_empty; + wire LoopbackFIFO_full; + wire LoopbackFIFO_wren; + reg LoopbackFIFO_rden; + wire sysclk,regclk; + + reg [3:0] pwr_on_cnt; + reg Sync_Rst, CE; + + assign CLK_125M = clk_125M; + assign CLK_125M_90 = clk_125M_90; + assign CLK_25M = clk_25M; + assign CLK_25M_90 = clk_25M_90; + assign sysclk = MAC_Sysclk; + assign regclk = MAC_Regclk; + + + + //Phy interface + wire MAC_Tx_Clk_d; + wire MAC_Tx_Clk; + wire MAC_Rx_Clk; + + wire [31:0] MAC_Monitoring; + wire MAC_GMII_TxER; + wire MAC_GMII_TxEN; + wire [7:0] MAC_GMII_TxD; + wire MAC_GMII_RxDV; + wire MAC_GMII_RxER; + wire GMII_RxDV; + wire [7:0] MAC_GMII_RxD; + wire MAC_Carrier_Sense; + wire MAC_Colision_Detect; + + + /* Altera GBX signals */ + wire [7:0] gmii_rx_d; + wire gmii_rx_dv; + wire gmii_rx_err; + wire [7:0] gmii_tx_d; + wire gmii_tx_en; + wire gmii_tx_err; + wire GXB_tx_clk; + wire GXB_rx_clk; + wire [3:0] mii_rx_d; + wire [3:0] mii_tx_d; + wire mii_rx_dv; + wire mii_tx_en; + wire mii_rx_err; + wire mii_tx_err; + wire set_100; + wire hd_ena; + wire GXB_reset; + wire [4:0] GXB_reg_addr; + wire [15:0] GXB_readdata; + wire [15:0] GXB_writedata; + wire GXB_read; + wire GXB_write; + wire GXB_wait; + wire GXB_regclk; + wire GXB_refclk; + wire GXB_reconfig_clk; + wire [3:0] GXB_reconfig_togxb; + wire GXB_led_an; + wire GXB_tx_clkena; + wire GXB_rx_clkena; + wire GXB_led_link; + wire GXB_cs; + + wire mdi; + wire mdo; + wire mdoe; + + /* + wire Rx_mac_ra,Rx_mac_rd,Rx_mac_pa, Rx_mac_sop,Rx_mac_eop; + wire [31:0] Rx_mac_data ; + wire [1:0] Rx_mac_BE ; + wire Tx_mac_wa, Tx_mac_wr,Tx_mac_sop,Tx_mac_eop; + wire [31:0] Tx_mac_data; + wire [1:0] Tx_mac_BE ;*/ + + initial + begin + pwr_on_rst <= 1; + pwr_on_cnt <= 0; + end + + //power on reset circuit + always@(posedge CLK_125M) + begin + if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1; + if (pwr_on_cnt<15 && pwr_on_cnt>9) + pwr_on_rst <= 1; + else + pwr_on_rst <= 0; + end + + always@(posedge(CLK_125M)) + begin + if(!rstn) + begin + Sync_Rst <= 1; + CE <= 0; + end + else + begin + Sync_Rst <= 0; + CE <= 1; + end + end + assign sysrst = (~rstn)|pwr_on_rst; + assign MAC_rsti = MACrst | pwr_on_rst | (~rstn); + assign MAC_Carrier_Sense = 0; + assign MAC_Colision_Detect = 0; + + //MAC Module + MAC_top gMAC( //system signals + .Reset (MAC_rsti), + .Clk_125M (CLK_125M), + .Clk_125M_90 (CLK_125M_90), + .Clk_25M_90 (CLK_25M_90), + .Clk_25M (CLK_25M), + .Clk_user (sysclk), + .Clk_reg (regclk), + .Tx_clk (clk_25M), //used only in MII mode + + + .Speed (Speed), + + //user interface RX + .Rx_mac_ra (Rx_ra), + .Rx_mac_rd (Rx_rd), + .Rx_mac_data (Rx_data), + .Rx_mac_BE (Rx_BE), + .Rx_mac_pa (Rx_pa), + .Rx_mac_sop (Rx_sop), + .Rx_mac_eop (Rx_eop), + //user interface + .Tx_mac_wa (Tx_wa), + .Tx_mac_wr (Tx_wr), + .Tx_mac_data (Tx_data), + .Tx_mac_BE (Tx_BE),//big endian + .Tx_mac_sop (Tx_sop), + .Tx_mac_eop (Tx_eop), + //pkg_lgth fifo + .Pkg_lgth_fifo_rd (pktlen_fifo_rd), + .Pkg_lgth_fifo_ra (pktlen_fifo_ra), + .Pkg_lgth_fifo_data (pktlen_fifo_data), + //Phy interface + //Phy interface + .Rx_clk (MAC_Rx_Clk), + .Gtx_clk (MAC_Tx_Clk), //used only in GMII mode + .Gtx_clk_d (MAC_Tx_Clk_d), + .Tx_er (MAC_GMII_TxER), + .Tx_en (MAC_GMII_TxEN), + .Txd (MAC_GMII_TxD), + .Rx_er (MAC_GMII_RxER), + .Rx_dv (MAC_GMII_RxDV), + .Rxd (MAC_GMII_RxD), + .Crs (MAC_Carrier_Sense), + .Col (MAC_Colision_Detect), + //host interface + .CSB (MAC_RegSelect), + .WRB (MAC_RdnWr), + .CD_in (MAC_RegDin), + .CD_out (MAC_RegDout), + .CA (MAC_RegAddr), + .Monitoring (MAC_Monitoring), + //mdx + .Mdo(mdo), // MII Management Data Output + .MdoEn(mdoe), // MII Management Data Output Enable + .Mdi(mdi), + .Mdc(mdc) // MII Management Data Clock + ); + + assign mdio = mdoe?(mdo):1'bz; + assign mdi = mdio; + + //RGMII adapter + RGMII2GMII R2G( + .RGMII_RxD(RGMII_Rx_D), + .RGMII_RxCtl(RGMII_Rx_DV), + .RGMII_RxClk(RGMII_Rx_CLK), + .RxD(MAC_GMII_RxD), + .RxDV(MAC_GMII_RxDV), + .RxER(MAC_GMII_RxER), + .RxClk(MAC_Rx_Clk), + .ClkEN(1'b1), + .rst(sysrst) + ); + + GMII2RGMII G2R( + .TxD(MAC_GMII_TxD), + .TxClk(MAC_Tx_Clk), + .TxClk90(MAC_Tx_Clk_d), + .TxEn(MAC_GMII_TxEN), + .TxErr(MAC_GMII_TxER), + .RGMII_TxD(RGMII_Tx_D), + .RGMII_TxCtl(RGMII_Tx_EN), + .RGMII_TxClk(RGMII_Tx_CLK), + + .ClkEN(1'b1), + .rst(sysrst) + ); + + always@(posedge MAC_Rx_Clk) + begin + if((~MAC_GMII_RxDV) & (~MAC_GMII_RxER)) link_stat <= MAC_GMII_RxD[3:0]; + end + + //GMII to SGMII + /* + sgmii_if sgmii ( + .gmii_rx_d(gmii_rx_d), + .gmii_rx_dv(gmii_rx_dv), + .gmii_rx_err(gmii_rx_err), + .gmii_tx_d(gmii_tx_d), + .gmii_tx_en(gmii_tx_en), + .gmii_tx_err(gmii_tx_err), + + .tx_clk(GXB_tx_clk), + .rx_clk(GXB_rx_clk), + + .mii_rx_d(mii_rx_d), + .mii_rx_dv(mii_rx_dv), + .mii_rx_err(mii_rx_err), + .mii_tx_d(mii_tx_d), + .mii_tx_en(mii_tx_en), + .mii_tx_err(mii_tx_err), + .mii_col(), + .mii_crs(), + + .set_10(), + .set_100(set_100), + .set_1000(), + .hd_ena(hd_ena), + + .reset_tx_clk(GXB_reset), + .reset_rx_clk(GXB_reset), + + .address(GXB_reg_addr), + .readdata(GXB_readdata), + .read(GXB_read), + .writedata(GXB_writedata), + .write(GXB_write), + .waitrequest(GXB_wait), + .clk(GXB_regclk), + .reset(GXB_reset), + + .txp(SGMII_Tx), + .rxp(SGMII_Rx), + .ref_clk(GXB_refclk), + .reconfig_clk(GXB_reconfig_clk), + .reconfig_togxb(GXB_reconfig_togxb), + .reconfig_fromgxb(), + .led_col(), + .led_crs(), + .led_an(GXB_led_an), + .tx_clkena(GXB_tx_clkena), + .rx_clkena(GXB_rx_clkena), + .led_link(GXB_led_link), + .led_disp_err(), + .gxb_cal_blk_clk(GXB_refclk), + .led_char_err() + ); + + //MII is open + assign GXB_reset = MAC_rsti; + assign GXB_regclk = regclk; + assign GXB_reg_addr = address[4:0]; + assign GXB_writedata = writedata; + assign GXB_read = read & GXB_cs; + assign GXB_write = write & GXB_cs; + assign GXB_cs = (address[7]==1'b1)?1'b1:1'b0; + + assign led_an = GXB_led_an; + assign led_link = GXB_led_link; + + //Others signal + assign GXB_reconfig_clk = 1'b0; + assign reconfig_togxb = 4'b0010; + assign GXB_refclk = clk_125M; + + //Connect MAC and GXB + //GMII Interafce + assign MAC_GMII_RxD = gmii_rx_d; + assign MAC_GMII_RxDV = gmii_rx_dv; + assign MAC_GMII_RxER = gmii_rx_err; + assign gmii_tx_d = MAC_GMII_TxD; + assign gmii_tx_en= MAC_GMII_TxEN; + assign gmii_tx_err = MAC_GMII_TxER; + + assign MAC_Tx_Clk = GXB_tx_clk; + assign MAC_Rx_Clk = GXB_rx_clk; + + */ + + assign MAC_RegSelect = (address[7]==1'b1)?1'b1:1'b0; + assign MAC_RdnWr = ~(write & (~read)& (~MAC_RegSelect)); + assign MAC_RegAddr[7:1] = address[6:0]; + assign MAC_RegDin = writedata; + //Multiplex data out + assign readdata = ((~MAC_RegSelect) & (~GXB_cs))?MAC_RegDout:GXB_readdata; + //wait signal + assign waitreq = (GXB_wait & GXB_cs) | (MAC_RegWait & (~MAC_RegSelect)); + + reg MAC_RegSelect_rd ; + assign MAC_RegWait = (~MAC_RegSelect_rd) & (~MAC_RegSelect & read); + always@(posedge regclk) + begin + MAC_RegSelect_rd <= (~MAC_RegSelect & read) ; + end + + assign Tx_mac_wa = Tx_wa; + assign Tx_wr = Tx_mac_wr; + assign Tx_sop = Tx_mac_sop; + assign Tx_eop = Tx_mac_eop; + assign Tx_BE = Tx_mac_BE; + assign Tx_data = Tx_mac_data; + //MAC BLOCK +// assign Tx_data = LoopbackFIFO_dout[31:0]; +// assign Tx_BE = LoopbackFIFO_dout[35:34]; +// assign Tx_sop = LoopbackFIFO_dout[32]; +// assign Tx_eop = LoopbackFIFO_dout[33]; +// assign LoopbackFIFO_din = {Rx_BE,Rx_eop,Rx_sop, Rx_data}; + +// always@(posedge sysclk) +// begin +// +// Rx_rd <= Rx_ra & (~LoopbackFIFO_full); +// LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty); +// Tx_wr <= LoopbackFIFO_rden; +// +// end +// assign LoopbackFIFO_wren = Rx_pa; + +// //Loopback FIFO block +// lpbff lpbff_inst ( +// .data ( LoopbackFIFO_din ), +// .rdreq ( LoopbackFIFO_rden ), +// .clock (sysclk), +// .wrreq ( LoopbackFIFO_wren ), +// .q ( LoopbackFIFO_dout ), +// .almost_empty (LoopbackFIFO_empty ), +// .almost_full (LoopbackFIFO_full ) +// ); + + assign Rx_mac_ra = Rx_ra; + assign Rx_mac_pa = Rx_pa; + assign Rx_mac_BE = Rx_BE; + assign Rx_mac_sop = Rx_sop; + assign Rx_mac_eop = Rx_eop; + assign Rx_rd = Rx_mac_rd; + assign Rx_mac_data = Rx_data; + +endmodule + + \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/timescale.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/timescale.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/timescale.v (revision 26) @@ -0,0 +1,59 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 11:36:31 mohor +// Log file added. +// +// +// + +`timescale 1ns / 1ns Index: sgmii/trunk/build/OpenCore_MAC/Broadcast_filter.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/Broadcast_filter.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/Broadcast_filter.v (revision 26) @@ -0,0 +1,104 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Broadcast_filter.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module Broadcast_filter ( +Reset , +Clk , +//MAC_rx_ctrl , +broadcast_ptr , +broadcast_drop , +//FromCPU , +broadcast_filter_en , +broadcast_bucket_depth , +broadcast_bucket_interval +); +input Reset ; +input Clk ; + //MAC_rx_ctrl +input broadcast_ptr ; +output broadcast_drop ; + //FromCPU ; +input broadcast_filter_en ; +input [15:0] broadcast_bucket_depth ; +input [15:0] broadcast_bucket_interval ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [15:0] time_counter ; +reg [15:0] broadcast_counter ; +reg broadcast_drop ; +//****************************************************************************** +// +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + time_counter <=0; + else if (time_counter==broadcast_bucket_interval) + time_counter <=0; + else + time_counter <=time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_counter <=0; + else if (time_counter==broadcast_bucket_interval) + broadcast_counter <=0; + else if (broadcast_ptr&&broadcast_counter!=broadcast_bucket_depth) + broadcast_counter <=broadcast_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_drop <=0; + else if(broadcast_filter_en&&broadcast_counter==broadcast_bucket_depth) + broadcast_drop <=1; + else + broadcast_drop <=0; + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/GbMAC_test.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/GbMAC_test.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/GbMAC_test.v (revision 26) @@ -0,0 +1,582 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:20:11 06/01/2010 +// Design Name: +// Module Name: GbMAC_test +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GbMAC_test( + + input PhyA_RxClk, + input PhyA_RxCtl, + input [3:0] PhyA_RxD, + output PhyA_TxClk, + output PhyA_TxCtl, + output [3:0] PhyA_TxD, + + //--------------------------------------------------------------------- + //-- pcix bus signals + //---------------------------------------------------------------------- +// inout [31:0] pcixad, +// inout [3:0] pcixc, +// inout pcixpar, +// inout pcixframe_n, +// inout pcixtrdy_n, +// inout pcixirdy_n, +// inout pcixstop_n, +// inout pcixdevsel_n, +// input pcixidsel, +// inout pcixperr_n, +// inout pcixserr_n, +// output pcixint_n, +// output pcixreq_n, +// input pcixgnt_n, +// input pcixreset_n, + input V4_PCIXClk, + + output V4_Uart_Tx, + input V4_Uart_Rx, + + input V4_CLK_125M, + input V4_CLK_Sys, + input V4_rst_n + ); + +//This test module consists of +//1) MAC block +//2) GMII-RGMII adapter +//3) State machine for intialization +//4) State machine for Checking incoming packets +//5) State machine for Generating tramitting packets + +// OPB BUS +wire [0:0] OPB_CS_n; +wire [11:0] OPB_Addr; +wire OPB_ADS; +wire [1:0] OPB_BE; +wire OPB_RnW; +wire OPB_Rd_n; +wire OPB_Wr_n; +wire OPB_Burst; +reg OPB_Rdy; +wire [15:0] OPB_Din; +wire [15:0] OPB_Dout; +wire [0:31] OPB_outD; +wire [0:31] OPB_inD; + +//PCI-X signals +/////////////////////////////////////////// +wire [63:0] s_data_out_i; +wire [7:0] s_cbea_out_i; +wire [63:0] s_data_in_i; +wire s_addl_vld_i; +wire s_addh_vld_i; +wire s_attr_vld_i; +wire s_datl_vld_i; +wire s_dath_vld_i; +wire s_data_nxt_i; +wire s_tabort_i; +wire s_retry_i; +wire s_discon_i; +wire s_nxtadb_i; +wire s_wait_i; +wire s_split_i; +wire s_write_i; +wire [15:0] s_hit_i; +wire s_done_i; +wire [63:0]m_data_out_i; +wire [7:0] m_cbea_in_i; +wire [63:0]m_data_in_i; +wire m_addl_vld_i; +wire m_addh_vld_i; +wire m_attr_vld_i; +wire m_datl_vld_i; +wire m_dath_vld_i; +wire m_data_nxt_i; +wire m_mabort_i; +wire m_retry_i; +wire m_nxtadb_i; +wire m_discon_i; +wire m_tabort_i; +wire m_split_i; +wire m_finish_i; +wire m_done_i; +wire m_req_i; +wire ad_io_i; +wire cbe_io_i; +wire uperr_n_i; +wire userr_n_i; +wire int_n_i; +wire [95:0] ms_stat_i; +wire pme_n_i; +wire [47:0] pm_stat_i; +wire [31:0] csr_i; +wire [47:0] csrx_i; +wire pciw_en_i; +wire pcix_en_i; +wire rtr_i; +wire [511:0] cfg_bus_i; +wire pci_core_rst_i; +wire pci_core_clk_i; + +wire csr_systemerr_n_i; +wire csrx_unexpected_i; +wire csrx_discarded_i; +wire pcixpar64_i; +wire pcixreq64_n_i; +wire pcixack64_n_i; + +/********************************************************/ + + //MAC Module signals + wire [2:0] gEMAC_Speed; + //user interface RX + wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop; + reg Tx_wr; + reg Rx_rd; + wire [31:0] Rx_data, Tx_data; + wire [1:0] Rx_BE, Tx_BE; + wire pkt_length_fifo_rd, pkt_length_fifo_ra; + wire [15:0] pkt_length_fifo_data; + wire Carrier_Sense, Colision_Detect; + + //host interface + wire MAC_RegSelect; + wire MAC_RdnWr; + wire [15:0] MAC_RegDin; + wire [15:0] MAC_RegDout; + wire [7:0] MAC_RegAddr; + + //initializing statemachine + reg [7:0] init_state; + + +//RGMII-GMII adaptation module + wire [7:0] GMII_TxD; + wire GMII_TxEN, GMII_TxER, GTx_Clk; + wire [7:0] GMII_RxD; + wire GMII_RxDV, GMII_RxER, GRx_Clk; + reg CE, Sync_Rst; + + wire [3:0] RGMII_RxD; + wire [3:0] RGMII_TxD; + wire RGMII_RxCtl, RGMII_RxClk; + wire RGMII_TxCtl, RGMII_TxClk; + + wire [3:0] RxPhyA_Stat; + wire [3:0] RxPhyB_Stat; + + wire GRxB_Clk, GTxB_Clk; + +//Packet generate + reg [10:0] cntr; + reg RxDV_d; + reg RxD_d; + reg [7:0] Txdata; + + assign PhyA_TxD = RGMII_TxD; + assign PhyA_TxClk = RGMII_TxClk; + assign PhyA_TxCtl = RGMII_TxCtl; + + assign RGMII_RxD = PhyA_RxD; + assign RGMII_RxCtl= PhyA_RxCtl; + assign RGMII_RxClk= PhyA_RxClk; + + assign CLK_66M = V4_PCIXClk; + + wire CLK_125M; + wire CLK_25M; + wire V4_rst; + wire uB_rst; + reg pwr_on_rst; + + wire MAC_Sysclk; + wire MAC_Regclk; + + wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout; + wire LoopbackFIFO_empty; + wire LoopbackFIFO_full; + wire LoopbackFIFO_wren; + reg LoopbackFIFO_rden; + + reg one_sec_pulse; + reg [27:0] one_sec; + reg [31:0] rx_rate; + reg [31:0] rx_rate_reg; + + wire [0:0] ila_trig0, ila_trig1, ila_trig2; + wire [63:0] ila_data_bus; + wire [35:0] ila_control; + wire [23:0] MAC_Monitoring; + + LoopbackFIFO lpbff( + .clk(CLK_125M), + .din(LoopbackFIFO_din), + .rd_en(LoopbackFIFO_rden), + .wr_en(LoopbackFIFO_wren), + .dout(LoopbackFIFO_dout), + .empty(), + .full(), + .almost_empty(LoopbackFIFO_empty), + .almost_full(LoopbackFIFO_full)); + + assign LoopbackFIFO_din = {Rx_BE,Rx_sop,Rx_eop,Rx_data}; + assign LoopbackFIFO_wren= Rx_pa; + + + always@(posedge(CLK_125M)) + begin + if(!V4_rst_n) + begin + Sync_Rst <= 1; + CE <= 0; + end + else + begin + Sync_Rst <= 0; + CE <= 1; + end + end + + assign V4_rst = (~V4_rst_n)|pwr_on_rst; + assign uB_rst = ~ V4_rst; + +Clocks Clockings(.V4_Clk_125M(V4_CLK_125M),.V4_Clk_27M(),.V4_Clk_13M5(), + .Clk_125M(CLK_125M),.Clk_27M(),.Clk_13M5(),.Clk_25M(CLK_25M), + .rst(0)); + +reg [3:0] pwr_on_cnt; + + initial + begin + pwr_on_rst <= 1; + pwr_on_cnt <= 0; + end + + always@(posedge CLK_125M) + begin + if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1; + if (pwr_on_cnt<15 && pwr_on_cnt>9) + pwr_on_rst <= 1; + else + pwr_on_rst <= 0; + end + + +RGMII_GMII_Adaptation RGMIIAdp(.TxD(GMII_TxD), .TxEN(GMII_TxEN), .TxER(GMII_TxER), .TxClk(GTx_Clk), + .RxD(GMII_RxD), .RxDV(GMII_RxDV), .RxER(GMII_RxER), .RxClk(GRx_Clk), + .RGMII_TxD(RGMII_TxD), + .RGMII_TxCtl(RGMII_TxCtl), + .RGMII_TxClk(RGMII_TxClk), + .RGMII_RxD(RGMII_RxD), + .RGMII_RxCtl(RGMII_RxCtl), + .RGMII_RxClk(RGMII_RxClk), + .Status(RxPhyA_Stat), + .CE(CE), + .rst(V4_rst) + ); + always@(posedge GRx_Clk) + begin + RxDV_d <= GMII_RxDV; + if (GMII_RxDV & (~ RxDV_d)) cntr <= 0; + else if(GMII_RxDV & RxDV_d) cntr <= cntr+1; + end + + always@(cntr,GMII_RxD) + begin + if(cntr==13) Txdata <= 13; else + if(cntr==19) Txdata <= 22; else + Txdata <= GMII_RxD; + end + +assign MAC_Sysclk = CLK_125M; +assign MAC_Regclk = CLK_66M; +//MAC Module +MAC_top gMAC( //system signals +.Reset(V4_rst), +.Clk_125M(CLK_125M), +.Clk_user(MAC_Sysclk), +.Clk_reg(MAC_Regclk), +.Speed(gEMAC_Speed), +//user interface RX +.Rx_mac_ra(Rx_ra), +.Rx_mac_rd(Rx_rd), +.Rx_mac_data(Rx_data), +.Rx_mac_BE(Rx_BE), +.Rx_mac_pa(Rx_pa), +.Rx_mac_sop(Rx_sop), +.Rx_mac_eop(Rx_eop), +//user interface +.Tx_mac_wa(Tx_wa), +.Tx_mac_wr(Tx_wr), +.Tx_mac_data(Tx_data), +.Tx_mac_BE(Tx_BE),//big endian +.Tx_mac_sop(Tx_sop), +.Tx_mac_eop(Tx_eop), +//pkg_lgth fifo +.Pkg_lgth_fifo_rd(pkt_length_fifo_rd), +.Pkg_lgth_fifo_ra(pkt_length_fifo_ra), +.Pkg_lgth_fifo_data(pkt_length_fifo_data), +//Phy interface +//Phy interface +.Gtx_clk(GTx_Clk),//used only in GMII mode +.Rx_clk(GRx_Clk), +.Tx_clk(CLK_25M),//used only in MII mode +.Tx_er(GMII_TxER), +.Tx_en(GMII_TxEN), +.Txd(GMII_TxD), +.Rx_er(GMII_RxER), +.Rx_dv(GMII_RxDV), +.Rxd(GMII_RxD), +.Crs(Carrier_Sense), +.Col(Colision_Detect), +//host interface +.CSB(MAC_RegSelect), +.WRB(MAC_RdnWr), +.CD_in(MAC_RegDin), +.CD_out(MAC_RegDout), +.CA(MAC_RegAddr), +.Monitoring(MAC_Monitoring), +//mdx +.Mdo(), // MII Management Data Output +.MdoEn(), // MII Management Data Output Enable +.Mdi(0), +.Mdc() // MII Management Data Clock +); + + //Route packet back to transmitter + assign Tx_data = LoopbackFIFO_dout[31:0]; + assign Tx_sop = LoopbackFIFO_dout[33]; + assign Tx_eop = LoopbackFIFO_dout[32]; + assign Tx_BE = LoopbackFIFO_dout[35:34]; + + assign MAC_RegSelect = OPB_CS_n; + assign MAC_RegDin = OPB_outD[0:15]; + assign OPB_inD = {MAC_RegDout,16'h0000}; + assign MAC_RegAddr = OPB_Addr[7:0]; + assign MAC_RdnWr = OPB_RnW; + +//Initializing machine + always@(posedge MAC_Regclk or posedge V4_rst) + begin + if(V4_rst) + begin + OPB_Rdy <= 0; + end + else + begin + OPB_Rdy <= ~OPB_CS_n; + end + end + + + + assign Carrier_Sense = 1; + assign Colision_Detect = 0; + + wire one_sec_pulse_long; + + assign one_sec_pulse_long = (one_sec>0 && one_sec<5)?1:0; + + always@(posedge MAC_Sysclk or posedge V4_rst) + if(V4_rst) + begin + one_sec <=0; + one_sec_pulse <= 0; + Rx_rd <= 0; + Tx_wr <= 0; + LoopbackFIFO_rden <= 0; + end + else + begin + if(one_sec == 125000000) one_sec <= 1; else one_sec <= one_sec+1; + if(one_sec == 125000000) one_sec_pulse <= 1; else one_sec_pulse <= 0; + if(one_sec_pulse) + begin + rx_rate <= 0; + rx_rate_reg <= rx_rate; + end + else + begin + if(Rx_sop) rx_rate <= rx_rate+1; + end + //start to read whenever data is available; + Rx_rd <= Rx_ra;// & (~LoopbackFIFO_full);//Start transfer only when Tx is ready also + //LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty); + //Tx_wr <= LoopbackFIFO_rden; + end + + + + + +//pci CORE +/* +pcix_lc i_pcix_lc( + .ad_io(pcixad), + //.ad_io(63 :32) => ad_io_i(63 downto 32), + .cbe_io(pcixc), + .par_io(pcixpar), + //cbe_io(7 downto 4) => cbe_io_i(7 downto 4), + //par64_io => pcixpar64_i, + .frame_io(pcixframe_n), + //req64_io => pcixreq64_n_i, + .trdy_io(pcixtrdy_n), + .irdy_io(pcixirdy_n), + .stop_io(pcixstop_n), + .devsel_io(pcixdevsel_n), + //.ack64_io(pcixack64_n_i), + .idsel_i(pcixidsel), + .perr_io(pcixperr_n), + .serr_io(pcixserr_n), + .int_o(pcixint_n), + //pme_o => open, + .req_o(pcixreq_n), + .gnt_i(pcixgnt_n), + .rst_i(pcixreset_n), + .clk_i(v4_pcixclk), + + .s_data_out(s_data_out_i), + .s_cbea_out(s_cbea_out_i), + .s_data_in(s_data_in_i), + .s_addl_vld(s_addl_vld_i), + .s_addh_vld(s_addh_vld_i), + .s_attr_vld(s_attr_vld_i), + .s_datl_vld(s_datl_vld_i), + .s_dath_vld (s_dath_vld_i), + .s_data_nxt (s_data_nxt_i), + .s_tabort (s_tabort_i), + .s_retry (s_retry_i), + .s_discon (s_discon_i), + .s_nxtadb (s_nxtadb_i), + .s_wait (s_wait_i), + .s_split (s_split_i), + .s_write (s_write_i), + .s_done (s_done_i), + .s_hit (s_hit_i), + + .m_data_out (m_data_out_i), + .m_cbea_in (m_cbea_in_i), + .m_data_in (m_data_in_i), + .m_addl_vld (m_addl_vld_i), + .m_addh_vld (m_addh_vld_i), + .m_attr_vld (m_attr_vld_i), + .m_datl_vld (m_datl_vld_i), + .m_dath_vld (m_dath_vld_i), + .m_data_nxt (m_data_nxt_i), + .m_mabort (m_mabort_i), + .m_retry (m_retry_i), + .m_nxtadb (m_nxtadb_i), + .m_discon (m_discon_i), + .m_tabort (m_tabort_i), + .m_split (m_split_i), + .m_finish (m_finish_i), + .m_done (m_done_i), + .m_req (m_req_i), + + .perr_n (uperr_n_i), + .serr_n (userr_n_i), + .int_n (int_n_i), + .ms_stat (ms_stat_i), + .pme_n (pme_n_i), + .pm_stat (pm_stat_i), + .csr (csr_i), + .csr_systemerr_n (csr_systemerr_n_i), + .csrx_unexpected (csrx_unexpected_i), + .csrx_discarded (csrx_discarded_i), + .csrx (csrx_i), + .pciw_en (pciw_en_i), + .pcix_en (pcix_en_i), + .rtr (rtr_i), + .cfg (cfg_bus_i), + + .rst (pci_core_rst_i), + .clk (pci_core_clk_i) + ); +*/ + //Microblaze + uBlaze microBlaze + ( .uBlaze_Int(one_sec_pulse_long), + .fpga_0_RS232_req_to_send_pin(), + .fpga_0_RS232_RX_pin(V4_Uart_Rx), + .fpga_0_RS232_TX_pin(V4_Uart_Tx), + .sys_clk_pin(CLK_66M), + .sys_rst_pin(uB_rst), + .PRH_Clk_pin(CLK_66M), + .PRH_Rst_pin(V4_rst), + .PRH_CS_n_pin(OPB_CS_n), + .PRH_Addr_pin(OPB_Addr), + .PRH_ADS_pin(OPB_ADS), + .PRH_BE_pin(OPB_BE), + .PRH_RNW_pin(OPB_RnW), + .PRH_Rd_n_pin(OPB_Rd_n), + .PRH_Wr_n_pin(OPB_Wr_n), + .PRH_Burst_pin(OPB_Burst), + .PRH_Rdy_pin(OPB_Rdy), + .PRH_Data_I_pin(OPB_inD), + .PRH_Data_O_pin(OPB_outD), + .PRH_Data_T_pin()); + + //Monitoring + ila i_ila + ( + .control(ila_control), + .clk(GRx_Clk), + .data(ila_data_bus), + .trig0(ila_trig0), + .trig1(ila_trig1), + .trig2(ila_trig2) + ); + + + + assign ila_data_bus[31:0] = {0,GMII_RxER,GMII_RxDV,GMII_RxD}; + assign ila_data_bus[47:32] = {0}; + assign ila_data_bus[63:48] = {0}; + assign ila_trig0 = GMII_RxDV; + assign ila_trig1 = GMII_RxER; + assign ila_trig2 = 0; + + icon i_icon + ( + .control0(ila_control) + ); + +endmodule + +module icon + ( + control0 + ); + output [35:0] control0; +endmodule + +module ila + ( + control, + clk, + data, + trig0, + trig1, + trig2 + ); + input [35:0] control; + input clk; + input [63:0] data; + input [0:0] trig0; + input [0:0] trig1; + input [0:0] trig2; +endmodule Index: sgmii/trunk/build/OpenCore_MAC/GMII_SGMII.v.bak =================================================================== --- sgmii/trunk/build/OpenCore_MAC/GMII_SGMII.v.bak (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/GMII_SGMII.v.bak (revision 26) @@ -0,0 +1,38 @@ + + + +module GMII_SGMII ( +//GMII interface +input [7:0] TxD, +input TxDV, +input TxER, +input TxClk, + +output [7:0] RxD, +output RxDV, +output RxER, +output RxClk, + +//SGMII Interface + +output SGMII_Tx, +input SGMII_Rx, + +//Supplementary + +input clk_125M, +input [2:0] Speed, +input rstn, +output core_clk, //This clock will change according to speed, will be either 125,25,2.5 +output core_clkh //This clock will change according to speed, will be either 125,12.5,1.25 +); + + + + + + + + + +endmodule Index: sgmii/trunk/build/OpenCore_MAC/GbMAC.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/GbMAC.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/GbMAC.v (revision 26) @@ -0,0 +1,492 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:49:28 06/15/2010 +// Design Name: +// Module Name: GbMAC_verify +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module GbMAC( + input clk_125M, + input clk_25M, //10Mbps not supported + input clk_125M_90, + input clk_25M_90, + input MAC_Sysclk, //FIFO interface of MAC block + input MAC_Regclk, //Register interface of MAC block + + input cal_blk_clk, //calibration clock + input rstn, //hardware reset + input MACrst, //Software reset of mac + + + //MDIO interface + inout mdio, + output mdc, + + + //GMII interface + + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_TXClk, + input [7:0] GMII_RXD, + input GMII_RX_EN, + input GMII_RX_ER, + input GMII_RXClk, + + //SGMII interface + + output SGMII_Tx, + input SGMII_Rx, + + //RGMII interface + //RX + input RGMII_Rx_DV, + input [3:0] RGMII_Rx_D, + input RGMII_Rx_CLK, + //TX + output RGMII_Tx_CLK, + output RGMII_Tx_EN, + output [3:0] RGMII_Tx_D, + + //Host interface + input [7:0] address , + input read , + input write , + input [15:0] writedata , + output [15:0] readdata , + output waitreq , + + //status + output led_an , + output led_link , + output [2:0] Speed , + output reg [3:0] link_stat , + + output pktlen_fifo_ra , + output [15:0] pktlen_fifo_data , + input pktlen_fifo_rd , + + //PACKET Inteface + output Rx_mac_ra , + input Rx_mac_rd , + output [31:0] Rx_mac_data , + output [1:0] Rx_mac_BE , + output Rx_mac_pa , + output Rx_mac_sop , + output Rx_mac_eop , + //user interface + output Tx_mac_wa , + input Tx_mac_wr , + input [31:0] Tx_mac_data , + input [1:0] Tx_mac_BE ,//big endian + input Tx_mac_sop , + input Tx_mac_eop +); + + //clocks + wire CLK_125M_90; + wire CLK_125M; + wire CLK_25M; + wire CLK_25M_90; + + //MAC Module signals + wire [2:0] gEMAC_Speed; + + //user interface RX + wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop; + wire Tx_wr; + wire Rx_rd; + wire [31:0] Rx_data, Tx_data; + wire [1:0] Rx_BE, Tx_BE; + wire pkt_length_fifo_rd, pkt_length_fifo_ra; + wire [15:0] pkt_length_fifo_data; + + + //host interface + wire RxClk_MAC;//For MAC Receiver block + wire TxClk_MAC;//For MAC Transmitter block + wire MAC_RegSelect; + wire MAC_RdnWr; + wire [15:0] MAC_RegDin; + wire [15:0] MAC_RegDout; + wire [7:0] MAC_RegAddr; + wire MAC_RegWait; + wire MAC_rsti; + + wire sysrst; + reg pwr_on_rst; + + + wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout; + wire LoopbackFIFO_empty; + wire LoopbackFIFO_full; + wire LoopbackFIFO_wren; + reg LoopbackFIFO_rden; + wire sysclk,regclk; + + reg [3:0] pwr_on_cnt; + reg Sync_Rst, CE; + + assign CLK_125M = clk_125M; + assign CLK_125M_90 = clk_125M_90; + assign CLK_25M = clk_25M; + assign CLK_25M_90 = clk_25M_90; + assign sysclk = MAC_Sysclk; + assign regclk = MAC_Regclk; + + + + //Phy interface + wire MAC_Tx_Clk_d; + wire MAC_Tx_Clk; + wire MAC_Rx_Clk; + + wire [31:0] MAC_Monitoring; + wire MAC_GMII_TxER; + wire MAC_GMII_TxEN; + wire [7:0] MAC_GMII_TxD; + wire MAC_GMII_RxDV; + wire MAC_GMII_RxER; + wire GMII_RxDV; + wire [7:0] MAC_GMII_RxD; + wire MAC_Carrier_Sense; + wire MAC_Colision_Detect; + + + /* Altera GBX signals */ + wire [7:0] gmii_rx_d; + wire gmii_rx_dv; + wire gmii_rx_err; + wire [7:0] gmii_tx_d; + wire gmii_tx_en; + wire gmii_tx_err; + wire GXB_tx_clk; + wire GXB_rx_clk; + wire [3:0] mii_rx_d; + wire [3:0] mii_tx_d; + wire mii_rx_dv; + wire mii_tx_en; + wire mii_rx_err; + wire mii_tx_err; + wire set_100; + wire hd_ena; + wire GXB_reset; + wire [4:0] GXB_reg_addr; + wire [15:0] GXB_readdata; + wire [15:0] GXB_writedata; + wire GXB_read; + wire GXB_write; + wire GXB_wait; + wire GXB_regclk; + wire GXB_refclk; + wire GXB_reconfig_clk; + wire [3:0] GXB_reconfig_togxb; + wire GXB_led_an; + wire GXB_tx_clkena; + wire GXB_rx_clkena; + wire GXB_led_link; + wire GXB_cs; + + wire mdi; + wire mdo; + wire mdoe; + + /* + wire Rx_mac_ra,Rx_mac_rd,Rx_mac_pa, Rx_mac_sop,Rx_mac_eop; + wire [31:0] Rx_mac_data ; + wire [1:0] Rx_mac_BE ; + wire Tx_mac_wa, Tx_mac_wr,Tx_mac_sop,Tx_mac_eop; + wire [31:0] Tx_mac_data; + wire [1:0] Tx_mac_BE ;*/ + + initial + begin + pwr_on_rst <= 1; + pwr_on_cnt <= 0; + end + + //power on reset circuit + always@(posedge CLK_125M) + begin + if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1; + if (pwr_on_cnt<15 && pwr_on_cnt>9) + pwr_on_rst <= 1; + else + pwr_on_rst <= 0; + end + + always@(posedge(CLK_125M)) + begin + if(!rstn) + begin + Sync_Rst <= 1; + CE <= 0; + end + else + begin + Sync_Rst <= 0; + CE <= 1; + end + end + assign sysrst = (~rstn)|pwr_on_rst; + assign MAC_rsti = MACrst | pwr_on_rst | (~rstn); + assign MAC_Carrier_Sense = 0; + assign MAC_Colision_Detect = 0; + + //MAC Module + MAC_top gMAC( //system signals + .Reset (MAC_rsti), + .Clk_125M (CLK_125M), + .Clk_125M_90 (CLK_125M_90), + .Clk_25M_90 (CLK_25M_90), + .Clk_25M (CLK_25M), + .Clk_user (sysclk), + .Clk_reg (regclk), + .Tx_clk (clk_25M), //used only in MII mode + + + .Speed (Speed), + + //user interface RX + .Rx_mac_ra (Rx_ra), + .Rx_mac_rd (Rx_rd), + .Rx_mac_data (Rx_data), + .Rx_mac_BE (Rx_BE), + .Rx_mac_pa (Rx_pa), + .Rx_mac_sop (Rx_sop), + .Rx_mac_eop (Rx_eop), + //user interface + .Tx_mac_wa (Tx_wa), + .Tx_mac_wr (Tx_wr), + .Tx_mac_data (Tx_data), + .Tx_mac_BE (Tx_BE),//big endian + .Tx_mac_sop (Tx_sop), + .Tx_mac_eop (Tx_eop), + //pkg_lgth fifo + .Pkg_lgth_fifo_rd (pktlen_fifo_rd), + .Pkg_lgth_fifo_ra (pktlen_fifo_ra), + .Pkg_lgth_fifo_data (pktlen_fifo_data), + //Phy interface + //Phy interface + .Rx_clk (MAC_Rx_Clk), + .Gtx_clk (MAC_Tx_Clk), //used only in GMII mode + .Gtx_clk_d (MAC_Tx_Clk_d), + .Tx_er (MAC_GMII_TxER), + .Tx_en (MAC_GMII_TxEN), + .Txd (MAC_GMII_TxD), + .Rx_er (MAC_GMII_RxER), + .Rx_dv (MAC_GMII_RxDV), + .Rxd (MAC_GMII_RxD), + .Crs (MAC_Carrier_Sense), + .Col (MAC_Colision_Detect), + //host interface + .CSB (MAC_RegSelect), + .WRB (MAC_RdnWr), + .CD_in (MAC_RegDin), + .CD_out (MAC_RegDout), + .CA (MAC_RegAddr), + .Monitoring (MAC_Monitoring), + //mdx + .Mdo(mdo), // MII Management Data Output + .MdoEn(mdoe), // MII Management Data Output Enable + .Mdi(mdi), + .Mdc(mdc) // MII Management Data Clock + ); + + assign mdio = mdoe?(mdo):1'bz; + assign mdi = mdio; + + //RGMII adapter + RGMII2GMII R2G( + .RGMII_RxD(RGMII_Rx_D), + .RGMII_RxCtl(RGMII_Rx_DV), + .RGMII_RxClk(RGMII_Rx_CLK), + .RxD(MAC_GMII_RxD), + .RxDV(MAC_GMII_RxDV), + .RxER(MAC_GMII_RxER), + .RxClk(MAC_Rx_Clk), + .ClkEN(1'b1), + .rst(sysrst) + ); + + GMII2RGMII G2R( + .TxD(MAC_GMII_TxD), + .TxClk(MAC_Tx_Clk), + .TxClk90(MAC_Tx_Clk_d), + .TxEn(MAC_GMII_TxEN), + .TxErr(MAC_GMII_TxER), + .RGMII_TxD(RGMII_Tx_D), + .RGMII_TxCtl(RGMII_Tx_EN), + .RGMII_TxClk(RGMII_Tx_CLK), + + .ClkEN(1'b1), + .rst(sysrst) + ); + + always@(posedge MAC_Rx_Clk) + begin + if((~MAC_GMII_RxDV) & (~MAC_GMII_RxER)) link_stat <= MAC_GMII_RxD[3:0]; + end + + //GMII to SGMII + /* + sgmii_if sgmii ( + .gmii_rx_d(gmii_rx_d), + .gmii_rx_dv(gmii_rx_dv), + .gmii_rx_err(gmii_rx_err), + .gmii_tx_d(gmii_tx_d), + .gmii_tx_en(gmii_tx_en), + .gmii_tx_err(gmii_tx_err), + + .tx_clk(GXB_tx_clk), + .rx_clk(GXB_rx_clk), + + .mii_rx_d(mii_rx_d), + .mii_rx_dv(mii_rx_dv), + .mii_rx_err(mii_rx_err), + .mii_tx_d(mii_tx_d), + .mii_tx_en(mii_tx_en), + .mii_tx_err(mii_tx_err), + .mii_col(), + .mii_crs(), + + .set_10(), + .set_100(set_100), + .set_1000(), + .hd_ena(hd_ena), + + .reset_tx_clk(GXB_reset), + .reset_rx_clk(GXB_reset), + + .address(GXB_reg_addr), + .readdata(GXB_readdata), + .read(GXB_read), + .writedata(GXB_writedata), + .write(GXB_write), + .waitrequest(GXB_wait), + .clk(GXB_regclk), + .reset(GXB_reset), + + .txp(SGMII_Tx), + .rxp(SGMII_Rx), + .ref_clk(GXB_refclk), + .reconfig_clk(GXB_reconfig_clk), + .reconfig_togxb(GXB_reconfig_togxb), + .reconfig_fromgxb(), + .led_col(), + .led_crs(), + .led_an(GXB_led_an), + .tx_clkena(GXB_tx_clkena), + .rx_clkena(GXB_rx_clkena), + .led_link(GXB_led_link), + .led_disp_err(), + .gxb_cal_blk_clk(GXB_refclk), + .led_char_err() + ); + + //MII is open + assign GXB_reset = MAC_rsti; + assign GXB_regclk = regclk; + assign GXB_reg_addr = address[4:0]; + assign GXB_writedata = writedata; + assign GXB_read = read & GXB_cs; + assign GXB_write = write & GXB_cs; + assign GXB_cs = (address[7]==1'b1)?1'b1:1'b0; + + assign led_an = GXB_led_an; + assign led_link = GXB_led_link; + + //Others signal + assign GXB_reconfig_clk = 1'b0; + assign reconfig_togxb = 4'b0010; + assign GXB_refclk = clk_125M; + + //Connect MAC and GXB + //GMII Interafce + assign MAC_GMII_RxD = gmii_rx_d; + assign MAC_GMII_RxDV = gmii_rx_dv; + assign MAC_GMII_RxER = gmii_rx_err; + assign gmii_tx_d = MAC_GMII_TxD; + assign gmii_tx_en= MAC_GMII_TxEN; + assign gmii_tx_err = MAC_GMII_TxER; + + assign MAC_Tx_Clk = GXB_tx_clk; + assign MAC_Rx_Clk = GXB_rx_clk; + + */ + + assign MAC_RegSelect = (address[7]==1'b1)?1'b1:1'b0; + assign MAC_RdnWr = ~(write & (~read)& (~MAC_RegSelect)); + assign MAC_RegAddr[7:1] = address[6:0]; + assign MAC_RegDin = writedata; + //Multiplex data out + assign readdata = ((~MAC_RegSelect) & (~GXB_cs))?MAC_RegDout:GXB_readdata; + //wait signal + assign waitreq = (GXB_wait & GXB_cs) | (MAC_RegWait & (~MAC_RegSelect)); + + reg MAC_RegSelect_rd ; + assign MAC_RegWait = (~MAC_RegSelect_rd) & (~MAC_RegSelect & read); + always@(posedge regclk) + begin + MAC_RegSelect_rd <= (~MAC_RegSelect & read) ; + end + + assign Tx_mac_wa = Tx_wa; + assign Tx_wr = Tx_mac_wr; + assign Tx_sop = Tx_mac_sop; + assign Tx_eop = Tx_mac_eop; + assign Tx_BE = Tx_mac_BE; + assign Tx_data = Tx_mac_data; + //MAC BLOCK +// assign Tx_data = LoopbackFIFO_dout[31:0]; +// assign Tx_BE = LoopbackFIFO_dout[35:34]; +// assign Tx_sop = LoopbackFIFO_dout[32]; +// assign Tx_eop = LoopbackFIFO_dout[33]; +// assign LoopbackFIFO_din = {Rx_BE,Rx_eop,Rx_sop, Rx_data}; + +// always@(posedge sysclk) +// begin +// +// Rx_rd <= Rx_ra & (~LoopbackFIFO_full); +// LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty); +// Tx_wr <= LoopbackFIFO_rden; +// +// end +// assign LoopbackFIFO_wren = Rx_pa; + +// //Loopback FIFO block +// lpbff lpbff_inst ( +// .data ( LoopbackFIFO_din ), +// .rdreq ( LoopbackFIFO_rden ), +// .clock (sysclk), +// .wrreq ( LoopbackFIFO_wren ), +// .q ( LoopbackFIFO_dout ), +// .almost_empty (LoopbackFIFO_empty ), +// .almost_full (LoopbackFIFO_full ) +// ); + + assign Rx_mac_ra = Rx_ra; + assign Rx_mac_pa = Rx_pa; + assign Rx_mac_BE = Rx_BE; + assign Rx_mac_sop = Rx_sop; + assign Rx_mac_eop = Rx_eop; + assign Rx_rd = Rx_mac_rd; + assign Rx_mac_data = Rx_data; + +endmodule + + \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC/MAC_rx.v =================================================================== --- sgmii/trunk/build/OpenCore_MAC/MAC_rx.v (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC/MAC_rx.v (revision 26) @@ -0,0 +1,233 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +`include "header.v" + +module MAC_rx ( +output [23:0] Monitoring, +input Reset , +input Clk_user, +input Clk , + //RMII interface +input MCrs_dv , +input [7:0] MRxD , +input MRxErr , + //flow_control signals +output [15:0] pause_quanta , +output pause_quanta_val , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //CPU +input MAC_rx_add_chk_en , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input broadcast_filter_en , +input [15:0] broadcast_bucket_depth , +input [15:0] broadcast_bucket_interval , +input RX_APPEND_CRC, +input [4:0] Rx_Hwmark , +input [4:0] Rx_Lwmark , +input CRC_chk_en , +input [5:0] RX_IFG_SET , +input [15:0] RX_MAX_LENGTH ,// 1518 +input [6:0] RX_MIN_LENGTH ,// 64 + //RMON interface +output [15:0] Rx_pkt_length_rmon , +output Rx_apply_rmon , +output [2:0] Rx_pkt_err_type_rmon , +output [2:0] Rx_pkt_type_rmon +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_chk interface +wire CRC_en ; +wire CRC_init; +wire CRC_err ; + //MAC_rx_add_chk interface +wire MAC_add_en ; +wire MAC_rx_add_chk_err ; + //broadcast_filter +wire broadcast_ptr ; +wire broadcast_drop ; + //flow_control signals +//wire [15:0] pause_quanta ; +//wire pause_quanta_val ; + //MAC_rx_ctrl interface +wire [7:0] Fifo_data ; +wire Fifo_data_en ; +wire Fifo_full ; +wire Fifo_data_err ; +wire Fifo_data_end ; +//****************************************************************************** +//instantiation +//****************************************************************************** + +assign Monitoring = {1'b0,Clk,MCrs_dv,MRxErr,Fifo_data_err,Fifo_data_end,Fifo_data_en,Fifo_full, + Fifo_data, + MRxD}; + +MAC_rx_ctrl U_MAC_rx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //RMII interface ( //RMII interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //CRC_chk interface (//CRC_chk interface ), +.CRC_en (CRC_en ), +.CRC_init (CRC_init ), +.CRC_err (CRC_err ), + //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //broadcast_filter (//broadcast_filter ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_rx_FF interface (//MAC_rx_FF interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), +.Fifo_full (Fifo_full ), + //RMON interface (//RMON interface ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ) +); + +MAC_rx_FF U_MAC_rx_FF ( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_full (Fifo_full ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), + //CPU (//CPU ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.RX_APPEND_CRC (RX_APPEND_CRC ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_eop (Rx_mac_eop ) +); + +`ifdef MAC_BROADCAST_FILTER_EN +Broadcast_filter U_Broadcast_filter( +.Reset (Reset ), +.Clk (Clk ), + //MAC_rx_ctrl (//MAC_rx_ctrl ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //FromCPU (//FromCPU ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ) +); +`else +assign broadcast_drop=0; +`endif + +CRC_chk U_CRC_chk( +.Reset (Reset ), +.Clk (Clk ), +.CRC_data (Fifo_data ), +.CRC_init (CRC_init ), +.CRC_en (CRC_en ), + //From CPU (//From CPU ), +.CRC_chk_en (CRC_chk_en ), +.CRC_err (CRC_err ) +); + +`ifdef MAC_TARGET_CHECK_EN +MAC_rx_add_chk U_MAC_rx_add_chk( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.data (Fifo_data ), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //From CPU (//From CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_add_prom_data ), +.MAC_add_prom_add (MAC_add_prom_add ), +.MAC_add_prom_wr (MAC_add_prom_wr ) +); +`else +assign MAC_rx_add_chk_err=0; +`endif + + + +endmodule \ No newline at end of file Index: sgmii/trunk/build/OpenCore_MAC =================================================================== --- sgmii/trunk/build/OpenCore_MAC (nonexistent) +++ sgmii/trunk/build/OpenCore_MAC (revision 26)

sgmii/trunk/build/OpenCore_MAC Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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Sample behavioral waveforms for design file "lpbff.v"