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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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Rev 253 → Rev 254

/open8_urisc/trunk/VHDL/o8_cpu.vhd
286,15 → 286,6
signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
signal uSec_Tick : std_logic;
 
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
 
signal CPU_Next_State : CPU_STATES := IPF_C0;
signal CPU_State : CPU_STATES := IPF_C0;
 
329,12 → 320,23
signal Int_Req, Int_Ack : std_logic := '0';
signal Set_Mask : std_logic := '0';
signal Int_Mask : DATA_TYPE := x"00";
signal ISR_Addr : ADDRESS_TYPE := x"0000";
signal i_Ints : INTERRUPT_BUNDLE := x"00";
signal Pending : INTERRUPT_BUNDLE := x"00";
signal Wait_for_FSM : std_logic := '0';
signal Wait_for_ISR : std_logic := '0';
 
alias ISR_Addr_Base is ISR_Start_Addr(15 downto 4);
signal ISR_Addr_Offset : std_logic_vector(3 downto 0) := x"0";
 
constant INT_VECTOR_0 : std_logic_vector(3 downto 0) := x"0";
constant INT_VECTOR_1 : std_logic_vector(3 downto 0) := x"2";
constant INT_VECTOR_2 : std_logic_vector(3 downto 0) := x"4";
constant INT_VECTOR_3 : std_logic_vector(3 downto 0) := x"6";
constant INT_VECTOR_4 : std_logic_vector(3 downto 0) := x"8";
constant INT_VECTOR_5 : std_logic_vector(3 downto 0) := x"A";
constant INT_VECTOR_6 : std_logic_vector(3 downto 0) := x"C";
constant INT_VECTOR_7 : std_logic_vector(3 downto 0) := x"E";
 
signal IDX_Offset : ADDRESS_TYPE := x"0000";
 
signal IDX_Reg_l : integer := 0;
382,6 → 384,35
-- Address bus selection/generation logic
-------------------------------------------------------------------------------
 
-- Address selection logic based on current CPU state. This is combinatorial,
-- as adding pipeline registration would add a clock cycle to every instr,
-- without really adding the Fmax to compensate.
Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr, Program_Ctr )
begin
case( CPU_State )is
 
when LDA_C2 | STA_C2 =>
Open8_Bus.Address <= Operand2 & Operand1;
 
when LDX_C1 | STX_C1 =>
Open8_Bus.Address <= IDX_NoOffset_Calc;
 
when LDO_C2 | STO_C2 =>
Open8_Bus.Address <= IDX_Offset_Calc;
 
when ISR_C1 | ISR_C2 =>
Open8_Bus.Address <= ISR_Addr_Base & ISR_Addr_Offset;
 
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
Open8_Bus.Address <= Stack_Ptr;
 
when others =>
Open8_Bus.Address <= Program_Ctr;
 
end case;
end process;
 
-- The original model treated the offset to LDO/STO as a signed value
-- allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
-- always helpful, so the generic allows the CPU to use unsigned math
425,35 → 456,6
end if;
end process;
 
-- Address selection logic based on current CPU state. This is combinatorial,
-- as adding pipeline registration would add a clock cycle to every instr,
-- without really adding the Fmax to compensate.
Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
IDX_Offset_Calc, ISR_Addr, Stack_Ptr, Program_Ctr )
begin
case( CPU_State )is
 
when LDA_C2 | STA_C2 =>
Open8_Bus.Address <= Operand2 & Operand1;
 
when LDX_C1 | STX_C1 =>
Open8_Bus.Address <= IDX_NoOffset_Calc;
 
when LDO_C2 | STO_C2 =>
Open8_Bus.Address <= IDX_Offset_Calc;
 
when ISR_C1 | ISR_C2 =>
Open8_Bus.Address <= ISR_Addr;
 
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
Open8_Bus.Address <= Stack_Ptr;
 
when others =>
Open8_Bus.Address <= Program_Ctr;
 
end case;
end process;
 
-------------------------------------------------------------------------------
-- Combinatorial portion of CPU finite state machine
-- State Logic / Instruction Decoding & Execution
1051,7 → 1053,7
else
Int_Mask <= Default_Interrupt_Mask;
end if;
ISR_Addr <= INT_VECTOR_0;
ISR_Addr_Offset <= INT_VECTOR_0;
 
for i in 0 to 7 loop
Regfile(i) <= x"00";
1214,28 → 1216,28
 
if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
if( Pending(0) = '1' )then
ISR_Addr <= INT_VECTOR_0;
ISR_Addr_Offset <= INT_VECTOR_0;
Pending(0) <= '0';
elsif( Pending(1) = '1' )then
ISR_Addr <= INT_VECTOR_1;
ISR_Addr_Offset <= INT_VECTOR_1;
Pending(1) <= '0';
elsif( Pending(2) = '1' )then
ISR_Addr <= INT_VECTOR_2;
ISR_Addr_Offset <= INT_VECTOR_2;
Pending(2) <= '0';
elsif( Pending(3) = '1' )then
ISR_Addr <= INT_VECTOR_3;
ISR_Addr_Offset <= INT_VECTOR_3;
Pending(3) <= '0';
elsif( Pending(4) = '1' )then
ISR_Addr <= INT_VECTOR_4;
ISR_Addr_Offset <= INT_VECTOR_4;
Pending(4) <= '0';
elsif( Pending(5) = '1' )then
ISR_Addr <= INT_VECTOR_5;
ISR_Addr_Offset <= INT_VECTOR_5;
Pending(5) <= '0';
elsif( Pending(6) = '1' )then
ISR_Addr <= INT_VECTOR_6;
ISR_Addr_Offset <= INT_VECTOR_6;
Pending(6) <= '0';
elsif( Pending(7) = '1' )then
ISR_Addr <= INT_VECTOR_7;
ISR_Addr_Offset <= INT_VECTOR_7;
Pending(7) <= '0';
end if;
Wait_for_FSM <= or_reduce(Pending);
1254,7 → 1256,7
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
-- lower half of the address.
if( INT_Ctrl.Incr_ISR = '1' )then
ISR_Addr <= ISR_Addr + 1;
ISR_Addr_Offset <= ISR_Addr_Offset + 1;
end if;
 
-------------------------------------------------------------------------------

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