URL
https://opencores.org/ocsvn/raytrac/raytrac/trunk
Subversion Repositories raytrac
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- This comparison shows the changes necessary to convert path
/
- from Rev 255 to Rev 256
- ↔ Reverse comparison
Rev 255 → Rev 256
/raytrac/branches/fp_sgdma/ap_n_dpc.vhd
51,6 → 51,7
sc : out std_logic_vector(31 downto 0); |
ack : in std_logic; |
empty : out std_logic; |
sign_switcheroo : in std_logic; |
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--paraminput : in vectorblock06; --! Vectores A,B |
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178,6 → 179,7
rst : in std_logic; |
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sign : in std_logic; |
sign_switch : in std_logic; |
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factor0 : in std_logic_vector(31 downto 0); |
factor1 : in std_logic_vector(31 downto 0); |
/raytrac/branches/fp_sgdma/raytrac.vhd
128,9 → 128,20
constant reg_ctrl_ageb : integer:=17; --! A>=B. |
constant reg_ctrl_aeb : integer:=18; --! A==B. |
constant reg_ctrl_aneb : integer:=19; --! A!=B. |
constant reg_ctrl_reference : integer:=20; --! If one of the |
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constant reg_ctrl_accum_op : integer:=20; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub. |
constant reg_ctrl_accum_op : integer:=21; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub. |
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constant reg_ctrl_sign_switcheroo : integer:=22; --! Sphere distance, magnitude like expression sign switch. |
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constant reg_ctrl_dma_ncntg_mode : integer:=23; --! Dma Transfer Non Contigous Mode |
constant reg_ctrl_chunk_size_l : integer:=24; --! Dma Transfer Non Contigous Mode chunk size lower bit; |
constant reg_ctrl_chunk_size_h : integer:=25; --! Dma Transfer Non Contigous Mode chunk size higher bit; |
constant reg_ctrl_hop_len_low : integer:=26; --! Dma Transfer Non Contigous Mode hop length lower bit; |
constant reg_ctrl_hop_len_high : integer:=28; --! Dma Transfer Non Contigous Mode hop length |
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constant reg_ctrl_use_sw : integer:=29; --! Its ok to use a SW raytrac. This bit is ignored here, in the HW implementation. |
constant reg_ctrl_use_hw : integer:=30; --! Its ok to use a HW raytrac. This bit is is ignored here, in the HW implementation. |
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal. |
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--! Nfetch Reg Mask |
219,6 → 230,7
sc : out std_logic_vector(31 downto 0); |
ack : in std_logic; |
empty : out std_logic; |
sign_switcheroo : in std_logic; |
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). |
sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion. |
pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético. |
265,6 → 277,7
sc => ssc, |
ack => sr_ack, |
empty => sr_e, |
sign_switcheroo => sreg_block(reg_ctrl)(reg_ctrl_sign_switcheroo), |
dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s), |
sync_chain_1 => ssync_chain_1, |
pipeline_pending => spipeline_pending |
/raytrac/branches/fp_sgdma/arith/single/arithblock.vhd
32,6 → 32,7
rst : in std_logic; |
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sign : in std_logic; |
sign_switch : in std_logic; |
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factor0 : in std_logic_vector(31 downto 0); |
factor1 : in std_logic_vector(31 downto 0); |
80,6 → 81,7
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signal sadd32blko_01 : std_logic_vector(31 downto 0); |
signal ssq32o : std_logic_vector(31 downto 0); |
signal ssigna1 : std_logic; |
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--! Componentes Aritméticos |
component fadd32long |
123,6 → 125,7
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sq32o <= ssq32o; |
a1 <= sadd32blko_01; |
ssigna1 <= sign_switch or sign; |
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--!TBXINSTANCESTART |
adder_i_0 : fadd32long |
137,7 → 140,7
adder_i_1 : fadd32long |
port map ( |
clk => clk, |
dpc => sign, |
dpc => ssigna1, |
a32 => sumando2, |
b32 => sumando3, |
c32 => sadd32blko_01 |