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<?xml version="1.0"?> |
<Project Version="4" Minor="6"> |
<FileSet Dir="sources_1" File="fileset.xml"/> |
<FileSet Dir="constrs_1" File="fileset.xml"/> |
<DefaultLaunch Dir="$PRUNDIR"/> |
<DefaultPromote Dir="$PROMOTEDIR"/> |
</Project> |
|
#----------------------------------------------------------- |
# PlanAhead v12.3 |
# Build 101344 by hdbuild on Fri Sep 3 23:23:03 PDT 2010 |
# Start of session at: Wed Apr 30 20:14:26 2014 |
# Process ID: 25658 |
# Log file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.log |
# Journal file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.jou |
#----------------------------------------------------------- |
start_gui -source /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl |
# create_project -name demo1 -dir "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1" -part xc3s200avq100-5 |
# set_param project.pinAheadLayout yes |
# set srcset [get_property srcset [current_run -impl]] |
# set_property top top $srcset |
# set_param project.paUcfFile "top.ucf" |
# set hdlfile [add_files [list {top.vhd}]] |
# set_property file_type VHDL $hdlfile |
# set_property library work $hdlfile |
# add_files "top.ucf" -fileset [get_property constrset [current_run]] |
# add_files -norecurse { {/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1} } |
# open_rtl_design -part xc3s200avq100-5 |
exit |
<?xml version="1.0"?> |
<DARoots Version="1" Minor="7"> |
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> |
<Filter Type="Srcs"/> |
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd"> |
</File> |
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc"> |
<FileInfo RelPath="top.ngc"/> |
</File> |
<Config> |
<Option Name="DesignMode" Val="RTL"/> |
<Option Name="TopModule" Val="top"/> |
</Config> |
</FileSet> |
</DARoots> |
|
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pa" timeStamp="Wed Apr 30 20:16:28 2014"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="e92a26838f3f4b93bb9ba2bb56b2943f" type="ProjectID"/> |
<property name="ProjectIteration" value="1" type="ProjectIteration"/> |
</section> |
<section name="PlanAhead Usage" visible="true"> |
<item name="Project Data"> |
<property name="SrcSetCount" value="1" type="SrcSetCount"/> |
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> |
<property name="DesignMode" value="RTL" type="DesignMode"/> |
<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/> |
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/> |
</item> |
<item name="Other"> |
<property name="GuiMode" value="0" type="GuiMode"/> |
<property name="BatchMode" value="0" type="BatchMode"/> |
<property name="TclMode" value="0" type="TclMode"/> |
<property name="ISEMode" value="2" type="ISEMode"/> |
</item> |
</section> |
</application> |
</document> |
<?xml version="1.0"?> |
<DARoots Version="1" Minor="7"> |
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> |
<Filter Type="Constrs"/> |
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ucf"> |
</File> |
<Config> |
<Option Name="TargetPart" Val="xc3s200avq100-5"/> |
</Config> |
</FileSet> |
</DARoots> |
|
#----------------------------------------------------------- |
# PlanAhead v12.3 |
# Build 101344 by hdbuild on Fri Sep 3 23:23:03 PDT 2010 |
# Start of session at: Wed Apr 30 20:14:26 2014 |
# Process ID: 25658 |
# Log file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.log |
# Journal file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.jou |
#----------------------------------------------------------- |
INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead |
INFO: [HD-Licensing 1] Got a license: PlanAhead |
INFO: [HD-ArchReader 0] Loading parts and site information from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/arch.xml |
INFO: [HD-RTPRIM 0] Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml' |
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml' |
start_gui -source /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl |
# create_project -name demo1 -dir "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1" -part xc3s200avq100-5 |
# set_param project.pinAheadLayout yes |
# set srcset [get_property srcset [current_run -impl]] |
# set_property top top $srcset |
# set_param project.paUcfFile "top.ucf" |
# set hdlfile [add_files [list {top.vhd}]] |
# set_property file_type VHDL $hdlfile |
# set_property library work $hdlfile |
# add_files "top.ucf" -fileset [get_property constrset [current_run]] |
# add_files -norecurse { {/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1} } |
# open_rtl_design -part xc3s200avq100-5 |
INFO: [HD-RTLIN 2] Parsing VHDL file "/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify |
INFO: [HD-RTLIN 2] Parsing package <attributes>. |
INFO: [HD-RTLIN 2] Parsing VHDL file "/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify |
INFO: [HD-RTLIN 2] Parsing package <attributes>. |
INFO: [HD-RTLIN 2] Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd" into library work |
INFO: [HD-RTLIN 2] Parsing entity <top>. |
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <top>. |
INFO: [HD-RTLIN 2] Elaborating entity <top> (architecture <Behavioral>) from library <work>. |
INFO: [HD-ArchReader 18] Reading macro library /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn |
INFO: [HD-EDIFIN 0] Parsing Edif File '/opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn' |
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '/opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn' |
INFO: [HD-ArchReader 7] Loading clock regions from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/ClockRegion.xml |
INFO: [HD-ArchReader 8] Loading clock buffers from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/ClockBuffers.xml |
INFO: [HD-ArchReader 3] Loading package from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/vq100/Package.xml |
INFO: [HD-ArchReader 4] Loading io standards from /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/IOStandards.xml |
INFO: [HD-ArchReader 5] Loading pkg sso from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/vq100/SSORules.xml |
INFO: [HD-GDRC 0] Loading list of drcs for the architecture : /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/drc.xml |
INFO: [HD-UCFReader 0] Parsing UCF File : ./top.ucf |
INFO: [HD-UCFReader 1] Finished Parsing UCF File : ./top.ucf |
|
DESIGN RULE CHECK VIOLATION REPORT |
Build: PlanAhead v12.3 by hdbuild |
on Fri Sep 3 23:23:03 PDT 2010 |
Report: by lguanuco on host cudar75, pid 25658 |
on Wed Apr 30 20:14:39 2014 |
|
REPORT SUMMARY |
Netlist: top |
Floorplan: <none> |
Design limits: <entire design considered> |
Checks: Unknown block name |
Unknown Unisim pin name |
Mismatching Attribute |
Max vios: <unlimited> |
Vios found: 1 |
|
REPORT DETAILS |
ULMN#1 |
Unknown block name - <no location> |
Block name RTL_INV is not a valid Unisim for the specified architecture. No block of type RTL_INV exists in the Unisim library for the spartan3a architecture. |
Related Vios: <none> |
|
INFO: [HD-LIB 0] Reading timing library /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/spartan3a-5.lib . |
INFO: [HD-LIB 1] Done reading timing library /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/spartan3a-5.lib . |
exit |
INFO: [HD-Application 0] Exiting PlanAhead... |
INFO: [HD-Licensing 2] Releasing license: PlanAhead |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>top Project Status (04/30/2014 - 20:02:59)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>demo1.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>top</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Placed and Routed</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc3s200a-5vq100</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/*.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.unroutes'>All Signals Completely Routed</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD>0 <A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TD ALIGN=RIGHT>16</TD> |
<TD ALIGN=RIGHT>68</TD> |
<TD ALIGN=RIGHT>23%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
<TD ALIGN=RIGHT>1.00</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
<TD>0 (Setup: 0, Hold: 0)</TD> |
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.unroutes'>All Signals Completely Routed</A></TD> |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
<TD> </TD> |
<TD BGCOLOR='#FFFF99'><B> </B></TD> |
<TD COLSPAN='2'> </TD> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:20 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/xst.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.bld'>Translation Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:27 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:37 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:53 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:58 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/trce.xmsgs?&DataKey=Info'>5 Infos (5 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 04/30/2014 - 20:06:03</center> |
</BODY></ |
Release 12.3 par M.70d (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
cudar75:: Wed Apr 30 20:02:41 2014 |
|
par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf |
|
|
Constraints file: top.pcf. |
Loading device for application Rf_Device from file '3s200a.nph' in environment /opt/Xilinx/12.3/ISE_DS/ISE/. |
"top" is an NCD, version 3.2, device xc3s200a, package vq100, speed -5 |
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) |
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) |
|
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par |
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all |
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be |
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. |
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
|
Device speed data version: "PRODUCTION 1.41 2010-09-15". |
|
|
Design Summary Report: |
|
Number of External IOBs 16 out of 68 23% |
|
Number of External Input IOBs 8 |
|
Number of External Input IBUFs 8 |
|
Number of External Output IOBs 8 |
|
Number of External Output IOBs 8 |
|
Number of External Bidir IOBs 0 |
|
|
|
|
Overall effort level (-ol): High |
Placer effort level (-pl): High |
Placer cost table entry (-t): 1 |
Router effort level (-rl): High |
|
Starting initial Timing Analysis. REAL time: 3 secs |
Finished initial Timing Analysis. REAL time: 3 secs |
|
|
Starting Placer |
Total REAL time at the beginning of Placer: 3 secs |
Total CPU time at the beginning of Placer: 1 secs |
|
Phase 1.1 Initial Placement Analysis |
Phase 1.1 Initial Placement Analysis (Checksum:7d) REAL time: 6 secs |
|
Phase 2.7 Design Feasibility Check |
Phase 2.7 Design Feasibility Check (Checksum:7d) REAL time: 6 secs |
|
Phase 3.31 Local Placement Optimization |
Phase 3.31 Local Placement Optimization (Checksum:7d) REAL time: 6 secs |
|
Phase 4.2 Initial Clock and IO Placement |
... |
Phase 4.2 Initial Clock and IO Placement (Checksum:7d) REAL time: 6 secs |
|
Phase 5.30 Global Clock Region Assignment |
Phase 5.30 Global Clock Region Assignment (Checksum:7d) REAL time: 6 secs |
|
Phase 6.36 Local Placement Optimization |
Phase 6.36 Local Placement Optimization (Checksum:7d) REAL time: 6 secs |
|
Phase 7.3 Local Placement Optimization |
.. |
Phase 7.3 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs |
|
Phase 8.5 Local Placement Optimization |
Phase 8.5 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs |
|
Phase 9.8 Global Placement |
Phase 9.8 Global Placement (Checksum:91a3910) REAL time: 6 secs |
|
Phase 10.5 Local Placement Optimization |
Phase 10.5 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs |
|
Phase 11.18 Placement Optimization |
Phase 11.18 Placement Optimization (Checksum:7f12344) REAL time: 6 secs |
|
Phase 12.5 Local Placement Optimization |
Phase 12.5 Local Placement Optimization (Checksum:7f12344) REAL time: 6 secs |
|
Total REAL time to Placer completion: 6 secs |
Total CPU time to Placer completion: 2 secs |
Writing design to file top.ncd |
|
|
|
Starting Router |
|
|
Phase 1 : 8 unrouted; REAL time: 10 secs |
|
Phase 2 : 8 unrouted; REAL time: 10 secs |
|
Phase 3 : 0 unrouted; REAL time: 10 secs |
|
Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Updating file: top.ncd with current fully routed design. |
|
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs |
|
Total REAL time to Router completion: 11 secs |
Total CPU time to Router completion: 5 secs |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
Generating "PAR" statistics. |
|
Timing Score: 0 (Setup: 0, Hold: 0) |
|
|
|
Generating Pad Report. |
|
All signals are completely routed. |
|
Total REAL time to PAR completion: 11 secs |
Total CPU time to PAR completion: 5 secs |
|
Peak Memory Usage: 143 MB |
|
Placement: Completed - No errors found. |
Routing: Completed - No errors found. |
|
Number of error messages: 0 |
Number of warning messages: 0 |
Number of info messages: 1 |
|
Writing design to file top.ncd |
|
|
|
PAR done! |
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6e |
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<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="16"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sw<7>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
</table> |
</section> |
<section stringID="MAP_RPM_MACROS"> |
<section stringID="MAP_SHAPE_SECTION"> |
<item dataType="int" stringID="MAP_NUM_SHAPE" value="0"/> |
</section> |
</section> |
<section stringID="MAP_GUIDE_REPORT"/> |
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/> |
<section stringID="MAP_TIMING_REPORT"/> |
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/> |
<section stringID="MAP_GENERAL_CONFIG_DATA"/> |
<section stringID="MAP_CONTROL_SET_INFORMATION"/> |
</task> |
</application> |
|
</document> |
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> |
<document OS="lin" product="ISE" version="12.3"> |
|
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
|
<application stringID="Xst" timeStamp="Wed Apr 30 20:02:15 2014"> |
<section stringID="User_Env"> |
<table stringID="User_EnvVar"> |
<column stringID="variable"/> |
<column stringID="value"/> |
<row stringID="row" value="0"> |
<item stringID="variable" value="PATH"/> |
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:/usr/local/bin:/usr/bin:/bin:/usr/local/games:/usr/games"/> |
</row> |
<row stringID="row" value="1"> |
<item stringID="variable" value="XILINX"/> |
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE/"/> |
</row> |
<row stringID="row" value="2"> |
<item stringID="variable" value="LD_LIBRARY_PATH"/> |
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin"/> |
</row> |
</table> |
<item stringID="User_EnvOs" value="OS Information"> |
<item stringID="User_EnvOsname" value="Debian"/> |
<item stringID="User_EnvOsrelease" value="Debian GNU/Linux 7.4 (wheezy)"/> |
</item> |
<item stringID="User_EnvHost" value="cudar75"/> |
<table stringID="User_EnvCpu"> |
<column stringID="arch"/> |
<column stringID="speed"/> |
<row stringID="row" value="0"> |
<item stringID="arch" value="AMD Athlon(tm) II X2 255 Processor"/> |
<item stringID="speed" value="3100.000 MHz"/> |
</row> |
</table> |
</section> |
<section stringID="XST_OPTION_SUMMARY"> |
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="top.prj"/> |
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/> |
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="top"/> |
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/> |
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s200a-5-vq100"/> |
<item DEFAULT="" label="-top" stringID="XST_TOP" value="top"/> |
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/> |
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/> |
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/> |
<item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/> |
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/> |
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/> |
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/> |
<item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/> |
<item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/> |
<item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/> |
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/> |
<item DEFAULT="<>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="<>"/> |
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/> |
<item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/> |
<item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/> |
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/> |
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/> |
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/> |
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/> |
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/> |
<item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/> |
<item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/> |
<item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/> |
<item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/> |
<item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/> |
<item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/> |
<item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/> |
<item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/> |
<item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/> |
<item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/> |
<item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/> |
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/> |
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/> |
<item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/> |
<item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/> |
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/> |
<item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="500"/> |
<item DEFAULT="24" label="-bufg" stringID="XST_BUFG" value="24"/> |
<item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/> |
<item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/> |
<item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/> |
<item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/> |
<item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/> |
<item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/> |
<item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/> |
<item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/> |
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/> |
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/> |
</section> |
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/> |
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/> |
<section stringID="XST_PARTITION_REPORT"> |
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS"> |
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> |
</section> |
</section> |
<section stringID="XST_FINAL_REPORT"> |
<section stringID="XST_FINAL_RESULTS"> |
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="top.ngr"/> |
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="top"/> |
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/> |
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/> |
<item stringID="XST_KEEP_HIERARCHY" value="No"/> |
</section> |
<section stringID="XST_DESIGN_STATISTICS"> |
<item stringID="XST_IOS" value="24"/> |
</section> |
<section stringID="XST_CELL_USAGE"> |
<item dataType="int" stringID="XST_BELS" value="8"> |
<item dataType="int" stringID="XST_INV" value="8"/> |
</item> |
<item dataType="int" stringID="XST_IO_BUFFERS" value="16"> |
<item dataType="int" stringID="XST_IBUF" value="8"/> |
<item dataType="int" stringID="XST_OBUF" value="8"/> |
</item> |
</section> |
</section> |
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> |
<item stringID="XST_SELECTED_DEVICE" value="3s200avq100-5"/> |
<item AVAILABLE="1792" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="4"/> |
<item AVAILABLE="3584" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="8"/> |
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="24"/> |
<item AVAILABLE="68" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="16"/> |
</section> |
<section stringID="XST_PARTITION_RESOURCE_SUMMARY"> |
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> |
</section> |
<section stringID="XST_ERRORS_STATISTICS"> |
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> |
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="5"/> |
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/> |
</section> |
</application> |
|
</document> |
Release 12.3 Map M.70d (lin) |
Xilinx Mapping Report File for Design 'top' |
|
Design Information |
------------------ |
Command Line : map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off |
-c 100 -o top_map.ncd top.ngd top.pcf |
Target Device : xc3s200a |
Target Package : vq100 |
Target Speed : -5 |
Mapper Version : spartan3a -- $Revision: 1.52 $ |
Mapped Date : Wed Apr 30 20:02:32 2014 |
|
Design Summary |
-------------- |
Number of errors: 0 |
Number of warnings: 0 |
Logic Utilization: |
Logic Distribution: |
Number of Slices containing only related logic: 0 out of 0 0% |
Number of Slices containing unrelated logic: 0 out of 0 0% |
*See NOTES below for an explanation of the effects of unrelated logic. |
Number of bonded IOBs: 16 out of 68 23% |
|
Average Fanout of Non-Clock Nets: 1.00 |
|
Peak Memory Usage: 159 MB |
Total REAL time to MAP completion: 4 secs |
Total CPU time to MAP completion: 2 secs |
|
NOTES: |
|
Related logic is defined as being logic that shares connectivity - e.g. two |
LUTs are "related" if they share common inputs. When assembling slices, |
Map gives priority to combine logic that is related. Doing so results in |
the best timing performance. |
|
Unrelated logic shares no connectivity. Map will only begin packing |
unrelated logic into a slice once 99% of the slices are occupied through |
related logic packing. |
|
Note that once logic distribution reaches the 99% level through related |
logic packing, this does not mean the device is completely utilized. |
Unrelated logic packing will then begin, continuing until all usable LUTs |
and FFs are occupied. Depending on your timing budget, increased levels of |
unrelated logic packing may adversely affect the overall timing performance |
of your design. |
|
Table of Contents |
----------------- |
Section 1 - Errors |
Section 2 - Warnings |
Section 3 - Informational |
Section 4 - Removed Logic Summary |
Section 5 - Removed Logic |
Section 6 - IOB Properties |
Section 7 - RPMs |
Section 8 - Guide Report |
Section 9 - Area Group and Partition Summary |
Section 10 - Timing Report |
Section 11 - Configuration String Information |
Section 12 - Control Set Information |
Section 13 - Utilization by Hierarchy |
|
Section 1 - Errors |
------------------ |
|
Section 2 - Warnings |
-------------------- |
|
Section 3 - Informational |
------------------------- |
INFO:LIT:243 - Logical network clk_div_1 has no load. |
INFO:LIT:395 - The above info message is repeated 7 more times for the following |
(max. 5 shown): |
clk_div_2, |
clk_div_3, |
clk_50M, |
push<3>, |
push<2> |
To see the details of these info messages, please use the -detail switch. |
INFO:MapLib:562 - No environment variables are currently set. |
INFO:LIT:244 - All of the single ended outputs in this design are using slew |
rate limited output drivers. The delay on speed critical single ended outputs |
can be dramatically reduced by designating them as fast outputs. |
|
Section 4 - Removed Logic Summary |
--------------------------------- |
|
Section 5 - Removed Logic |
------------------------- |
|
To enable printing of redundant blocks removed and signals merged, set the |
detailed map report option and rerun map. |
|
Section 6 - IOB Properties |
-------------------------- |
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND | |
| | | | | Term | Strength | Rate | | | Delay | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
| leds<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| leds<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| sw<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| sw<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
Section 7 - RPMs |
---------------- |
|
Section 8 - Guide Report |
------------------------ |
Guide not run on this design. |
|
Section 9 - Area Group and Partition Summary |
-------------------------------------------- |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
Area Group Information |
---------------------- |
|
No area groups were found in this design. |
|
---------------------- |
|
Section 10 - Timing Report |
-------------------------- |
This design was not run using timing mode. |
|
Section 11 - Configuration String Details |
----------------------------------------- |
Use the "-detail" map option to print out Configuration Strings |
|
Section 12 - Control Set Information |
------------------------------------ |
No control set information for this architecture. |
|
Section 13 - Utilization by Hierarchy |
------------------------------------- |
Use the "-detail" map option to print out the Utilization by Hierarchy section. |
work |
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<center><big><big><b>System Settings</b></big></big></center><br> |
<A NAME="Environment Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Environment Variable</b></td> |
<td><b>xst</b></td> |
<td><b>ngdbuild</b></td> |
<td><b>map</b></td> |
<td><b>par</b></td> |
</tr> |
<tr> |
<td>LD_LIBRARY_PATH</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td> |
</tr> |
<tr> |
<td>PATH</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td> |
</tr> |
<tr> |
<td>XILINX</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td> |
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-ifn</td> |
<td> </td> |
<td>top.prj</td> |
<td> </td> |
</tr> |
<tr> |
<td>-ifmt</td> |
<td> </td> |
<td>mixed</td> |
<td>MIXED</td> |
</tr> |
<tr> |
<td>-ofn</td> |
<td> </td> |
<td>top</td> |
<td> </td> |
</tr> |
<tr> |
<td>-ofmt</td> |
<td> </td> |
<td>NGC</td> |
<td>NGC</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc3s200a-5-vq100</td> |
<td> </td> |
</tr> |
<tr> |
<td>-top</td> |
<td> </td> |
<td>top</td> |
<td> </td> |
</tr> |
<tr> |
<td>-opt_mode</td> |
<td>Optimization Goal</td> |
<td>Speed</td> |
<td>Speed</td> |
</tr> |
<tr> |
<td>-opt_level</td> |
<td>Optimization Effort</td> |
<td>1</td> |
<td>1</td> |
</tr> |
<tr> |
<td>-iuc</td> |
<td>Use synthesis Constraints File</td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-keep_hierarchy</td> |
<td>Keep Hierarchy</td> |
<td>No</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-netlist_hierarchy</td> |
<td>Netlist Hierarchy</td> |
<td>As_Optimized</td> |
<td>As_Optimized</td> |
</tr> |
<tr> |
<td>-rtlview</td> |
<td>Generate RTL Schematic</td> |
<td>Yes</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-glob_opt</td> |
<td>Global Optimization Goal</td> |
<td>AllClockNets</td> |
<td>AllClockNets</td> |
</tr> |
<tr> |
<td>-read_cores</td> |
<td>Read Cores</td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-write_timing_constraints</td> |
<td>Write Timing Constraints</td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-cross_clock_analysis</td> |
<td>Cross Clock Analysis</td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-bus_delimiter</td> |
<td>Bus Delimiter</td> |
<td><></td> |
<td><></td> |
</tr> |
<tr> |
<td>-slice_utilization_ratio</td> |
<td>Slice Utilization Ratio</td> |
<td>100</td> |
<td>100%</td> |
</tr> |
<tr> |
<td>-bram_utilization_ratio</td> |
<td>BRAM Utilization Ratio</td> |
<td>100</td> |
<td>100%</td> |
</tr> |
<tr> |
<td>-verilog2001</td> |
<td>Verilog 2001</td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-fsm_extract</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-fsm_encoding</td> |
<td> </td> |
<td>Auto</td> |
<td>AUTO</td> |
</tr> |
<tr> |
<td>-safe_implementation</td> |
<td> </td> |
<td>No</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-fsm_style</td> |
<td> </td> |
<td>LUT</td> |
<td>LUT</td> |
</tr> |
<tr> |
<td>-ram_extract</td> |
<td> </td> |
<td>Yes</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-ram_style</td> |
<td> </td> |
<td>Auto</td> |
<td>AUTO</td> |
</tr> |
<tr> |
<td>-rom_extract</td> |
<td> </td> |
<td>Yes</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-shreg_extract</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-rom_style</td> |
<td> </td> |
<td>Auto</td> |
<td>AUTO</td> |
</tr> |
<tr> |
<td>-auto_bram_packing</td> |
<td> </td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-resource_sharing</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-async_to_sync</td> |
<td> </td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-mult_style</td> |
<td> </td> |
<td>Auto</td> |
<td>AUTO</td> |
</tr> |
<tr> |
<td>-iobuf</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-max_fanout</td> |
<td> </td> |
<td>500</td> |
<td>500</td> |
</tr> |
<tr> |
<td>-bufg</td> |
<td> </td> |
<td>24</td> |
<td>24</td> |
</tr> |
<tr> |
<td>-register_duplication</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-register_balancing</td> |
<td> </td> |
<td>No</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-optimize_primitives</td> |
<td> </td> |
<td>NO</td> |
<td>NO</td> |
</tr> |
<tr> |
<td>-use_clock_enable</td> |
<td> </td> |
<td>Yes</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-use_sync_set</td> |
<td> </td> |
<td>Yes</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-use_sync_reset</td> |
<td> </td> |
<td>Yes</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-iob</td> |
<td> </td> |
<td>Auto</td> |
<td>AUTO</td> |
</tr> |
<tr> |
<td>-equivalent_register_removal</td> |
<td> </td> |
<td>YES</td> |
<td>YES</td> |
</tr> |
<tr> |
<td>-slice_utilization_ratio_maxmargin</td> |
<td> </td> |
<td>5</td> |
<td>0%</td> |
</tr> |
</TABLE> |
<A NAME="Translation Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-dd</td> |
<td> </td> |
<td>_ngo</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc3s200a-vq100-5</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Map Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-ir</td> |
<td>Use RLOC Constraints</td> |
<td>OFF</td> |
<td>OFF</td> |
</tr> |
<tr> |
<td>-cm</td> |
<td>Optimization Strategy (Cover Mode)</td> |
<td>area</td> |
<td>area</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-o</td> |
<td> </td> |
<td>top_map.ncd</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-pr</td> |
<td>Pack I/O Registers/Latches into IOBs</td> |
<td>off</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc3s200a-vq100-5</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-t</td> |
<td> </td> |
<td>1</td> |
<td>1</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td> </td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>std</td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Operating System Information</b></td> |
<td><b>xst</b></td> |
<td><b>ngdbuild</b></td> |
<td><b>map</b></td> |
<td><b>par</b></td> |
</tr> |
<tr> |
<td>CPU Architecture/Speed</td> |
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td> |
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td> |
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td> |
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td> |
</tr> |
<tr> |
<td>Host</td> |
<td>cudar75</td> |
<td>cudar75</td> |
<td>cudar75</td> |
<td>cudar75</td> |
</tr> |
<tr> |
<td>OS Name</td> |
<td>Debian</td> |
<td>Debian</td> |
<td>Debian</td> |
<td>Debian</td> |
</tr> |
<tr> |
<td>OS Release</td> |
<td>Debian GNU/Linux 7.4 (wheezy)</td> |
<td>Debian GNU/Linux 7.4 (wheezy)</td> |
<td>Debian GNU/Linux 7.4 (wheezy)</td> |
<td>Debian GNU/Linux 7.4 (wheezy)</td> |
</tr> |
</TABLE> |
</BODY> </HTML> |
Release 12.3 ngdbuild M.70d (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
Command Line: /opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle |
ise -dd _ngo -nt timestamp -i -p xc3s200a-vq100-5 top.ngc top.ngd |
|
Reading NGO file |
"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc" ... |
Gathering constraint information from source properties... |
Done. |
|
Resolving constraint associations... |
Checking Constraint Associations... |
Done... |
|
Checking expanded design ... |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
NGDBUILD Design Results Summary: |
Number of errors: 0 |
Number of warnings: 0 |
|
Total memory usage is 86904 kilobytes |
|
Writing NGD file "top.ngd" ... |
Total REAL time to NGDBUILD completion: 3 sec |
Total CPU time to NGDBUILD completion: 2 sec |
|
Writing NGDBUILD log file "top.bld"... |
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6 |
###3208:XlxV32DM 1f39 c70eNqll9ly2zgWhl9FF7qbspsACIIkOilLIu1woi2S7Dh9ERbXHs3Y8qIk3V2S3n0OFm4SaV04KYsH38Hy4ycJgH0H7TC/oPCXEPh7dPjFevNj++Ofh8xCVdxbb7PexXPv74RssWFEF79ekGFc0B406UWvWdS7WL/2nvIcKulr0oMavYun3o+n5/Axer7cJKmILzd/qutzkvdgzPUr/DzDD1QnnFwi8YMR4qYbTOe3K/f55/Y/vxPX+JhzW6PtX78zAAgDmd2uBHrI0q2CBh/eBmMvXA0WNz78jD7ZQJZhML2eJXyYPWx7xiXpod4E2bLoBsPb69Dzx4Nv4cD7dzgczu7zWiaYwm9aA/OBV+RnwxAEAEwqAGkQMRp44V3gfw3v/MUymE0dPppNJsFq5XuMjxb+AIKUj54en5Ue3JtEqigHcYp4NkQ8AFME/K0pMlJQ6rNVDGOrSMjCPJiKltP98nY596eeS5YrGHe/h5az4W9KOZMxNKR8csmMFFpMBvNwNPHGwdQPZ/MVqF9GEk5m3u3YT2W8CiY+dDeZx7KopwmNo2fGp/7q62zxGfMZdAfjWHw+GH32PcKFO5TPvWU4HM9Gn8ObqRcOg6kXTG+Q087DhX8N3VS5+Xgw8if+dJXX4O1ycOM3ur4bjVq7rnHZ9XEbMfTkZpFIDDMJV9/mfqRKN14YeGrYuTcpZq27mAfT0L9fgdO+Jxsh1Yd8DuoTuvNHcmRUpUXPy2/TUb1JXWjRhNbSavBQPOPanwZfXINokARPf+Ddx0U8HUx8ZPL5Z3jml8HNFIaehMvZ7WLk54JCsby3Fl/6Y3gDMr4qLRITy2VZt5czNY8J3BB/Aa+ownfByA/FMwA3KW+yxSptgAm8PbUyPLm+p5GYQTCZj4NRsFK9rGo3QY0lLZACxsFwiVJ+H8CDfH9x7w3hRUO95epWBYPlKAgsfp/GYZDCAPfpYziJ/vv0epe9btdPmwKtNyUyuVjsGE8e/hdSY+LIIF3/ClEV4iokUPMxfVhvMsJhBWVcrlLGRx2gIsBFQIrALAJaBNZHh5eLnGbsYyyD0Ahn8CbrAqoXcL1A6gWzXqD1glUvMFkgHBZ1xuVaLIaXASoCDNrKZVozAmz7HL3+iDYkohyWbLGCy8tluYxJjhRHxxwrjo85UZwcc1Nx85hTxekxtxS3apxxvbXICkxVYLUKMKe/wG21QkOIqhBXIalCswppFVpVyGRIOGyJMS/3yj8fKZd7rM2LPdekfF+t/4PVagFbgHsd3PtefQe7G4xvfdcbfzPc4No7gfs9zqGfRXDnF10gDLtMURjfjSazJabucux/hZ/Z1/0e1pz9aY39/nB19YxQzq+u/rYj99rFLtotEXOx42LTRYRQZGcusQmNdxtquIhvKHIt3jdz18z4YYmslroJT6E3qN3dG/RAXRM6Sl1m8A1mLiUWshG41ceWYH1sQyuoh1w75r9WOFU9uth4o9PEtfkXksDAhy8kEpc+sV2H9xGFTN90ZNem7dopXJhrJ3ABrXxj4kJCxP8h0GNmwzWV1zG4ae36lLkgCLkMxLlw4uoTl0KnkIt43xK/h08k5n+YqYt3yHZz9xArI2wXid/dCzH5CzH4J0L5HzDGLnEjN3YPa2pCNb6mVF0sdSHi8mQhuPRNw7VAJslB7Ccz5j8JGGBw/kTzZhodpbNmGh+l02aaHKWTZto8SsfNND1KR820dZR2mmnWSK+tcmKZnjewtMmQYEmTYcHiJiPAbEMzlrf4uGZpM42O0nEzjY/STjNNjtKsmTaP0rSZpkdp0kxbR2nUTDd9jKXNWPzf9U14ZSK+xmIy/F9YPBs8trCsAPbs+gReMAy9MHhi4QGHRojLVrD/YUM+j1j4zQ+qX1Q1I6oZks3sXDUzi1EOW1mf7D7AcDjhH6CIM/4d/g5bWypQKQNYzA/Qf3RON2nTnZ+THbXKxp2yIy2bKNlRTTbRsklddnxOttkmOzsnO26VTTplx1q2qWTHNdmmlm3WZSfnZNM22ek52UmrbLNTdqJlUyU7qcmmWjaty07PybbaZCfnZKetsmmn7FTLtpTstCbb0rKtuuzsnGzWJjs+JztrlW11ys60bKZkZzXZTMtmddn5Odl2m+zonOy8VTbrlJ1r2baSnddk21q2XZMtd9A3ZTttsp0zsmW3p7LtLtmyvpDtSNlQrGQ7WrZTk82UbAJtZFcOf0IN2ay5cMOHp1wA1T+1oNiZkmFA21yeKkyi1NtHjVPZ2FbV0clkWXOyKFOTVR45hmqGq8kyPVlbLukfGDpd7UG+SbiskYgWFYYj6XekPCDnPDDf4wFp84B1ekBaPYg6PSDaA6I8IKdbB8iXHhDtgVnimgf0nAfWezww2zywOj2grR7EnR5Q7YGpPKCn+xDIlx6Y2gOrxDUP2DkP7Pd4QNs8oJ0esFYPkk4PmPaAKg/Y6aYG8qUHVHtgl7jmgXPOg+g9HlhtHpidHjitHqSdHujTn20pD5zTHRLkSw8s7UFU4poH8TkPkvd4wNo8IJ0exK0eZJ0e6DOZzZQH8el2C/KlB0x7kJS45kF6zoPsPR7YbR7gTg/SVg/yTg/0Scm2lQfp6d4N8qUHtvYgK3HlgfyYe8sDG73HA6fNA9TlgRRz4gE2ujyQ9YUHcrf/AMWTgwDIlx44ygM1G4lLD9R5Au++W6g4TOijETCaF+cifcoTLCuOePrAKlhanFb12Vuw8uCtPyMEi4tvCP1FJFhUfA7pjzvBnOLLTk8TmF3OUd9+YCwt7r1+LQSLi3dCLxeCOcVaoZdRwVixhurtRTBa7C162xWMFHuuPo4IhoqzSHUOEXpjiYWv5dYsphbLHhTWu5VwIZaDKawXcGFYLHUprNc04W0sp6Cwfs3FbVCzVVg/+eKOxdIYhYtTIZIYPJQ3fpOpMfVX+k8CCyYHalUUVZRVFFfUriipqFNRs6JRRWlF44paFU0qyiqalrQmNythTVdewkpAbpSwGilHJbQriEsYVZCUMKmgWcKsguqs0lgoypz1Ro69kbPfyDlv5KI3cvEbuaQ7J1cRpHIVzEuYltBJSxiXMIpL6JQwdkpY3fCElbB6YlJawtojR0pYPrPw7+pqtEModbMIxwlBGMBwh3dEH8D5C6H8sMN5vQh15rsvMLLBv4DpiL/EIn5JZCx6i8QlgwtU/T9g13Zu |
Release 12.3 - par M.70d (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
Wed Apr 30 20:02:53 2014 |
|
|
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: |
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. |
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. |
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. |
|
INPUT FILE: top_map.ncd |
OUTPUT FILE: top_pad.txt |
PART TYPE: xc3s200a |
SPEED GRADE: -5 |
PACKAGE: vq100 |
|
Pinout by Pin Number: |
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|Pin Number|Signal Name|Pin Usage |Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|P1 | | |TMS | | | | | | | | | | | | |
|P2 | | |TDI | | | | | | | | | | | | |
|P3 | |DIFFMLR |IO_L01P_3 |UNUSED | |3 | | | | | | | | | |
|P4 | |DIFFSLR |IO_L01N_3 |UNUSED | |3 | | | | | | | | | |
|P5 | |DIFFMLR |IO_L02P_3 |UNUSED | |3 | | | | | | | | | |
|P6 | |DIFFSLR |IO_L02N_3 |UNUSED | |3 | | | | | | | | | |
|P7 | |DIFFSI_NDT|IP_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | | |
|P9 | |DIFFMLR |IO_L03P_3/LHCLK0 |UNUSED | |3 | | | | | | | | | |
|P10 | |DIFFSLR |IO_L03N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | |
|P11 | | |VCCO_3 | | |3 | | | | |any******| | | | |
|P12 | |DIFFMLR |IO_L04P_3/LHCLK2 |UNUSED | |3 | | | | | | | | | |
|P13 | |DIFFSLR |IO_L04N_3/IRDY2/LHCLK3|UNUSED | |3 | | | | | | | | | |
|P14 | | |GND | | | | | | | | | | | | |
|P15 | |DIFFMLR |IO_L05P_3/TRDY2/LHCLK6|UNUSED | |3 | | | | | | | | | |
|P16 | |DIFFSLR |IO_L05N_3/LHCLK7 |UNUSED | |3 | | | | | | | | | |
|P17 | | |VCCINT | | | | | | | |1.2 | | | | |
|P18 | | |GND | | | | | | | | | | | | |
|P19 | |DIFFMLR |IO_L06P_3 |UNUSED | |3 | | | | | | | | | |
|P20 | |DIFFSLR |IO_L06N_3 |UNUSED | |3 | | | | | | | | | |
|P21 | |DIFFMI_NDT|IP_3 |UNUSED | |3 | | | | | | | | | |
|P22 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P23 |sw<7> |IBUF |IO_L01P_2/M1 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P24 | |DIFFMTB |IO_L02P_2/M2 |UNUSED | |2 | | | | | | | | | |
|P25 |leds<7> |IOB |IO_L01N_2/M0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P26 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|P27 |leds<5> |IOB |IO_L02N_2/CSO_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P28 |sw<5> |IBUF |IO_L03P_2/RDWR_B |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P29 |sw<1> |IBUF |IO_L03N_2/VS2 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P30 | |DIFFMTB |IO_L04P_2/VS1 |UNUSED | |2 | | | | | | | | | |
|P31 |leds<1> |IOB |IO_L04N_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P32 |sw<3> |IBUF |IO_L05P_2 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P33 |leds<3> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P34 |sw<2> |IBUF |IO_L06P_2/D7 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P35 |leds<2> |IOB |IO_L06N_2/D6 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P36 |leds<6> |IOB |IO_L07P_2/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P37 |sw<6> |IBUF |IO_L07N_2/D4 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P38 | | |VCCINT | | | | | | | |1.2 | | | | |
|P39 | |IBUF |IP_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|P40 |leds<4> |IOB |IO_L08P_2/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P41 |sw<4> |IBUF |IO_L08N_2/GCLK15 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P42 | | |GND | | | | | | | | | | | | |
|P43 |sw<0> |IBUF |IO_L09P_2/GCLK0 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE | |
|P44 |leds<0> |IOB |IO_L09N_2/GCLK1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|P46 | |DIFFSTB |IO_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | | |
|P47 | | |GND | | | | | | | | | | | | |
|P48 | |DIFFMTB |IO_L10P_2/INIT_B |UNUSED | |2 | | | | | | | | | |
|P49 | |DIFFSTB |IO_L10N_2/D3 |UNUSED | |2 | | | | | | | | | |
|P50 | |DIFFMTB |IO_L11P_2/D2 |UNUSED | |2 | | | | | | | | | |
|P51 | |DIFFMTB |IO_L12P_2/D0/DIN/MISO |UNUSED | |2 | | | | | | | | | |
|P52 | |DIFFSTB |IO_L11N_2/D1 |UNUSED | |2 | | | | | | | | | |
|P53 | |DIFFSTB |IO_L12N_2/CCLK |UNUSED | |2 | | | | | | | | | |
|P54 | | |DONE | | | | | | | | | | | | |
|P55 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P56 | |DIFFMLR |IO_L01P_1 |UNUSED | |1 | | | | | | | | | |
|P57 | |DIFFSLR |IO_L01N_1 |UNUSED | |1 | | | | | | | | | |
|P58 | | |GND | | | | | | | | | | | | |
|P59 | |DIFFMLR |IO_L02P_1/RHCLK0 |UNUSED | |1 | | | | | | | | | |
|P60 | |DIFFSLR |IO_L02N_1/RHCLK1 |UNUSED | |1 | | | | | | | | | |
|P61 | |DIFFMLR |IO_L03P_1/RHCLK2 |UNUSED | |1 | | | | | | | | | |
|P62 | |DIFFSLR |IO_L03N_1/TRDY1/RHCLK3|UNUSED | |1 | | | | | | | | | |
|P63 | | |GND | | | | | | | | | | | | |
|P64 | |DIFFMLR |IO_L04P_1/IRDY1/RHCLK6|UNUSED | |1 | | | | | | | | | |
|P65 | |DIFFSLR |IO_L04N_1/RHCLK7 |UNUSED | |1 | | | | | | | | | |
|P66 | | |VCCINT | | | | | | | |1.2 | | | | |
|P67 | | |VCCO_1 | | |1 | | | | |any******| | | | |
|P68 | |DIFFMI_NDT|IP_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|P69 | | |GND | | | | | | | | | | | | |
|P70 | |DIFFMLR |IO_L05P_1 |UNUSED | |1 | | | | | | | | | |
|P71 | |DIFFSLR |IO_L05N_1 |UNUSED | |1 | | | | | | | | | |
|P72 | |DIFFMLR |IO_L06P_1 |UNUSED | |1 | | | | | | | | | |
|P73 | |DIFFSLR |IO_L06N_1 |UNUSED | |1 | | | | | | | | | |
|P74 | | |GND | | | | | | | | | | | | |
|P75 | | |TDO | | | | | | | | | | | | |
|P76 | | |TCK | | | | | | | | | | | | |
|P77 | |DIFFMTB |IO_L01P_0/VREF_0 |UNUSED | |0 | | | | | | | | | |
|P78 | |DIFFSTB |IO_L01N_0 |UNUSED | |0 | | | | | | | | | |
|P79 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|P80 | | |GND | | | | | | | | | | | | |
|P81 | | |VCCINT | | | | | | | |1.2 | | | | |
|P82 | |IBUF |IP_0/VREF_0 |UNUSED | |0 | | | | | | | | | |
|P83 | |DIFFMTB |IO_L02P_0/GCLK4 |UNUSED | |0 | | | | | | | | | |
|P84 | |DIFFSTB |IO_L02N_0/GCLK5 |UNUSED | |0 | | | | | | | | | |
|P85 | |DIFFMTB |IO_L03P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |
|P86 | |DIFFSTB |IO_L03N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |
|P87 | | |GND | | | | | | | | | | | | |
|P88 | |DIFFMTB |IO_L04P_0/GCLK8 |UNUSED | |0 | | | | | | | | | |
|P89 | |DIFFSTB |IO_L04N_0/GCLK9 |UNUSED | |0 | | | | | | | | | |
|P90 | |DIFFSTB |IO_0/GCLK11 |UNUSED | |0 | | | | | | | | | |
|P91 | | |GND | | | | | | | | | | | | |
|P92 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P93 | |DIFFMTB |IO_L05P_0 |UNUSED | |0 | | | | | | | | | |
|P94 | |DIFFSTB |IO_L05N_0 |UNUSED | |0 | | | | | | | | | |
|P95 | | |GND | | | | | | | | | | | | |
|P96 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|P97 | |IBUF |IP_0 |UNUSED | |0 | | | | | | | | | |
|P98 | |DIFFMTB |IO_L06P_0/VREF_0 |UNUSED | |0 | | | | | | | | | |
|P99 | |DIFFSTB |IO_L06N_0/PUDC_B |UNUSED | |0 | | | | | | | | | |
|P100 | | |PROG_B | | | | | | | | | | | | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
* Default value. |
** This default Pullup/Pulldown value can be overridden in Bitgen. |
****** Special VCCO requirements may apply. Please consult the device |
family datasheet for specific guideline on VCCO requirements. |
|
|
xst -intstyle ise -ifn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.xst" -ofn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.syr" |
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s200a-vq100-5 top.ngc top.ngd |
map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf |
par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf |
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf |
<?xml version="1.0" encoding="utf-8"?> |
<!--This is an ISE project configuration file.--> |
<!--It holds project specific layout data for the projectmgr plugin.--> |
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> |
<Project version="2" owner="projectmgr" name="demo1" > |
<!--This is an ISE project configuration file.--> |
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > |
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<ClosedNodesVersion>2</ClosedNodesVersion> |
</ClosedNodes> |
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<SelectedItem>top - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd)</SelectedItem> |
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<CurrentItem>top - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd)</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>Design Utilities</ClosedNode> |
</ClosedNodes> |
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<SelectedItem></SelectedItem> |
</SelectedItems> |
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<CurrentItem></CurrentItem> |
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<ItemView guiview="File" > |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem></CurrentItem> |
</ItemView> |
<ItemView guiview="Library" > |
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<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>work</ClosedNode> |
</ClosedNodes> |
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000124000000010001000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>work</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
<ClosedNode>Configure Target Device</ClosedNode> |
<ClosedNode>Design Utilities</ClosedNode> |
<ClosedNode>Implement Design</ClosedNode> |
<ClosedNode>Synthesize - XST</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>I/O Pin Planning (PlanAhead) - Pre-Synthesis</SelectedItem> |
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001e8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e80000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>I/O Pin Planning (PlanAhead) - Pre-Synthesis</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > |
<ClosedNodes> |
<ClosedNodesVersion>1</ClosedNodesVersion> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>Edit Constraints (Text)</SelectedItem> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>Edit Constraints (Text)</CurrentItem> |
</ItemView> |
<SourceProcessView>000000ff0000000000000002000001440000011d01000000060100000002</SourceProcessView> |
<CurrentView>Implementation</CurrentView> |
</Project> |
<?xml version='1.0' encoding='UTF-8'?> |
<report-views version="2.0" > |
<header> |
<DateModified>2014-04-30T19:55:22</DateModified> |
<ModuleName>top</ModuleName> |
<SummaryTimeStamp>Unknown</SummaryTimeStamp> |
<SavedFilePath>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/iseconfig/top.xreport</SavedFilePath> |
<ImplementationReportsDirectory>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1</ImplementationReportsDirectory> |
<DateInitialized>2014-04-30T19:55:22</DateInitialized> |
<EnableMessageFiltering>false</EnableMessageFiltering> |
</header> |
<body> |
<viewgroup label="Design Overview" > |
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" > |
<toc-item title="Design Overview" target="Design Overview" /> |
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> |
<toc-item title="Performance Summary" target="Performance Summary" /> |
<toc-item title="Failing Constraints" target="Failing Constraints" /> |
<toc-item title="Detailed Reports" target="Detailed Reports" /> |
</view> |
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<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" /> |
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<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" /> |
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</viewgroup> |
<viewgroup label="XPS Errors and Warnings" > |
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> |
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<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> |
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> |
</viewgroup> |
<viewgroup label="XPS Reports" > |
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<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> |
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> |
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" /> |
</viewgroup> |
<viewgroup label="Errors and Warnings" > |
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> |
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<toc-item title="HDL Compilation" target=" HDL Compilation " /> |
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> |
<toc-item title="HDL Analysis" target=" HDL Analysis " /> |
<toc-item title="HDL Parsing" target=" HDL Parsing " /> |
<toc-item title="HDL Elaboration" target=" HDL Elaboration " /> |
<toc-item title="HDL Synthesis" target=" HDL Synthesis " /> |
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<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> |
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> |
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> |
<toc-item title="Partition Report" target=" Partition Report " /> |
<toc-item title="Final Report" target=" Final Report " /> |
<toc-item title="Design Summary" target=" Design Summary " /> |
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<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> |
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> |
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> |
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> |
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> |
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> |
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> |
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> |
</view> |
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<toc-item title="Command Line" target="Command Line:" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> |
</view> |
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> |
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> |
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> |
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> |
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> |
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> |
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> |
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> |
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> |
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> |
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> |
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> |
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Device Utilization" target="Device Utilization Summary:" /> |
<toc-item title="Router Information" target="Starting Router" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Clock Report" target="Generating Clock Report" /> |
<toc-item title="Timing Results" target="Timing Score:" /> |
<toc-item title="Final Summary" target="Peak Memory Usage:" /> |
</view> |
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
<toc-item title="Timing Summary" target="Timing summary:" /> |
<toc-item title="Trace Settings" target="Trace Settings:" /> |
</view> |
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" > |
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> |
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> |
<toc-item title="Pin Resources" target="** Pin Resources **" /> |
<toc-item title="Global Resources" target="** Global Control Resources **" /> |
</view> |
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" > |
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> |
<toc-item title="Performance Summary" target="Performance Summary:" /> |
</view> |
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Power summary" target="Power summary" /> |
<toc-item title="Thermal summary" target="Thermal summary" /> |
</view> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> |
<toc-item title="Final Summary" target="DRC detected" /> |
</view> |
</viewgroup> |
<viewgroup label="Secondary Reports" > |
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> |
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
<toc-item title="Design Information" target="Design Information" /> |
<toc-item title="Design Summary" target="Design Summary" /> |
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<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
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work |
Release 12.3 Map M.70d (lin) |
Xilinx Map Application Log File for Design 'top' |
|
Design Information |
------------------ |
Command Line : map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off |
-c 100 -o top_map.ncd top.ngd top.pcf |
Target Device : xc3s200a |
Target Package : vq100 |
Target Speed : -5 |
Mapper Version : spartan3a -- $Revision: 1.52 $ |
Mapped Date : Wed Apr 30 20:02:32 2014 |
|
Mapping design into LUTs... |
Running directed packing... |
Running delay-based LUT packing... |
Running related packing... |
Updating timing models... |
|
Design Summary |
-------------- |
|
Design Summary: |
Number of errors: 0 |
Number of warnings: 0 |
Logic Utilization: |
Logic Distribution: |
Number of Slices containing only related logic: 0 out of 0 0% |
Number of Slices containing unrelated logic: 0 out of 0 0% |
*See NOTES below for an explanation of the effects of unrelated logic. |
Number of bonded IOBs: 16 out of 68 23% |
|
Average Fanout of Non-Clock Nets: 1.00 |
|
Peak Memory Usage: 159 MB |
Total REAL time to MAP completion: 4 secs |
Total CPU time to MAP completion: 2 secs |
|
NOTES: |
|
Related logic is defined as being logic that shares connectivity - e.g. two |
LUTs are "related" if they share common inputs. When assembling slices, |
Map gives priority to combine logic that is related. Doing so results in |
the best timing performance. |
|
Unrelated logic shares no connectivity. Map will only begin packing |
unrelated logic into a slice once 99% of the slices are occupied through |
related logic packing. |
|
Note that once logic distribution reaches the 99% level through related |
logic packing, this does not mean the device is completely utilized. |
Unrelated logic packing will then begin, continuing until all usable LUTs |
and FFs are occupied. Depending on your timing budget, increased levels of |
unrelated logic packing may adversely affect the overall timing performance |
of your design. |
|
Mapping completed. |
See MAP report file "top_map.mrp" for details. |
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|
<header> |
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|
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/> |
|
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="top_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="demo1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-30T19:53:45" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E14E4DF5D9E1A20DBB6BE9CAABEC8DB2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
-------------------------------------------------------------------------------- |
Release 12.3 Trace (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
/opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3 |
-fastpaths -xml top.twx top.ncd -o top.twr top.pcf |
|
Design file: top.ncd |
Physical constraint file: top.pcf |
Device,package,speed: xc3s200a,vq100,-5 (PRODUCTION 1.41 2010-09-15) |
Report level: verbose report |
|
Environment Variable Effect |
-------------------- ------ |
NONE No environment variables were set |
-------------------------------------------------------------------------------- |
|
INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
option. All paths that are not constrained will be reported in the |
unconstrained paths section(s) of the report. |
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
a 50 Ohm transmission line loading model. For the details of this model, |
and for more information on accounting for different loading conditions, |
please see the device datasheet. |
INFO:Timing:3390 - This architecture does not support a default System Jitter |
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock |
Uncertainty calculation. |
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and |
'Phase Error' calculations, these terms will be zero in the Clock |
Uncertainty calculation. Please make appropriate modification to |
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase |
Error. |
|
|
|
Data Sheet report: |
----------------- |
All values displayed in nanoseconds (ns) |
|
Pad to Pad |
---------------+---------------+---------+ |
Source Pad |Destination Pad| Delay | |
---------------+---------------+---------+ |
sw<0> |leds<0> | 4.987| |
sw<1> |leds<1> | 5.256| |
sw<2> |leds<2> | 4.987| |
sw<3> |leds<3> | 4.991| |
sw<4> |leds<4> | 4.980| |
sw<5> |leds<5> | 4.993| |
sw<6> |leds<6> | 4.980| |
sw<7> |leds<7> | 4.987| |
---------------+---------------+---------+ |
|
|
Analysis completed Wed Apr 30 20:02:58 2014 |
-------------------------------------------------------------------------------- |
|
Trace Settings: |
------------------------- |
Trace Settings |
|
Peak Memory Usage: 97 MB |
|
|
|
Release 12.3 - xst M.70d (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
--> |
Parameter TMPDIR set to xst/projnav.tmp |
|
|
Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.04 secs |
|
--> |
Parameter xsthdpdir set to xst |
|
|
Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.04 secs |
|
--> |
Reading design: top.prj |
|
TABLE OF CONTENTS |
1) Synthesis Options Summary |
2) HDL Compilation |
3) Design Hierarchy Analysis |
4) HDL Analysis |
5) HDL Synthesis |
5.1) HDL Synthesis Report |
6) Advanced HDL Synthesis |
6.1) Advanced HDL Synthesis Report |
7) Low Level Synthesis |
8) Partition Report |
9) Final Report |
9.1) Device utilization summary |
9.2) Partition Resource Summary |
9.3) TIMING REPORT |
|
|
========================================================================= |
* Synthesis Options Summary * |
========================================================================= |
---- Source Parameters |
Input File Name : "top.prj" |
Input Format : mixed |
Ignore Synthesis Constraint File : NO |
|
---- Target Parameters |
Output File Name : "top" |
Output Format : NGC |
Target Device : xc3s200a-5-vq100 |
|
---- Source Options |
Top Module Name : top |
Automatic FSM Extraction : YES |
FSM Encoding Algorithm : Auto |
Safe Implementation : No |
FSM Style : LUT |
RAM Extraction : Yes |
RAM Style : Auto |
ROM Extraction : Yes |
Mux Style : Auto |
Decoder Extraction : YES |
Priority Encoder Extraction : Yes |
Shift Register Extraction : YES |
Logical Shifter Extraction : YES |
XOR Collapsing : YES |
ROM Style : Auto |
Mux Extraction : Yes |
Resource Sharing : YES |
Asynchronous To Synchronous : NO |
Multiplier Style : Auto |
Automatic Register Balancing : No |
|
---- Target Options |
Add IO Buffers : YES |
Global Maximum Fanout : 500 |
Add Generic Clock Buffer(BUFG) : 24 |
Register Duplication : YES |
Slice Packing : YES |
Optimize Instantiated Primitives : NO |
Use Clock Enable : Yes |
Use Synchronous Set : Yes |
Use Synchronous Reset : Yes |
Pack IO Registers into IOBs : Auto |
Equivalent register Removal : YES |
|
---- General Options |
Optimization Goal : Speed |
Optimization Effort : 1 |
Keep Hierarchy : No |
Netlist Hierarchy : As_Optimized |
RTL Output : Yes |
Global Optimization : AllClockNets |
Read Cores : YES |
Write Timing Constraints : NO |
Cross Clock Analysis : NO |
Hierarchy Separator : / |
Bus Delimiter : <> |
Case Specifier : Maintain |
Slice Utilization Ratio : 100 |
BRAM Utilization Ratio : 100 |
Verilog 2001 : YES |
Auto BRAM Packing : NO |
Slice Utilization Ratio Delta : 5 |
|
========================================================================= |
|
|
========================================================================= |
* HDL Compilation * |
========================================================================= |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd" in Library work. |
Architecture behavioral of Entity top is up to date. |
|
========================================================================= |
* Design Hierarchy Analysis * |
========================================================================= |
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>). |
|
|
========================================================================= |
* HDL Analysis * |
========================================================================= |
Analyzing Entity <top> in library <work> (Architecture <behavioral>). |
Entity <top> analyzed. Unit <top> generated. |
|
|
========================================================================= |
* HDL Synthesis * |
========================================================================= |
|
Performing bidirectional port resolution... |
|
Synthesizing Unit <top>. |
Related source file is "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd". |
WARNING:Xst:647 - Input <clk_div_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
WARNING:Xst:647 - Input <clk_div_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
WARNING:Xst:647 - Input <clk_div_3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
WARNING:Xst:647 - Input <push> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
WARNING:Xst:647 - Input <clk_50M> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
Unit <top> synthesized. |
|
|
========================================================================= |
HDL Synthesis Report |
|
Found no macro |
========================================================================= |
|
========================================================================= |
* Advanced HDL Synthesis * |
========================================================================= |
|
|
========================================================================= |
Advanced HDL Synthesis Report |
|
Found no macro |
========================================================================= |
|
========================================================================= |
* Low Level Synthesis * |
========================================================================= |
|
Optimizing unit <top> ... |
|
Mapping all equations... |
Building and optimizing final netlist ... |
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0. |
|
Final Macro Processing ... |
|
========================================================================= |
Final Register Report |
|
Found no macro |
========================================================================= |
|
========================================================================= |
* Partition Report * |
========================================================================= |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
========================================================================= |
* Final Report * |
========================================================================= |
Final Results |
RTL Top Level Output File Name : top.ngr |
Top Level Output File Name : top |
Output Format : NGC |
Optimization Goal : Speed |
Keep Hierarchy : No |
|
Design Statistics |
# IOs : 24 |
|
Cell Usage : |
# BELS : 8 |
# INV : 8 |
# IO Buffers : 16 |
# IBUF : 8 |
# OBUF : 8 |
========================================================================= |
|
Device utilization summary: |
--------------------------- |
|
Selected Device : 3s200avq100-5 |
|
Number of Slices: 4 out of 1792 0% |
Number of 4 input LUTs: 8 out of 3584 0% |
Number of IOs: 24 |
Number of bonded IOBs: 16 out of 68 23% |
|
--------------------------- |
Partition Resource Summary: |
--------------------------- |
|
No Partitions were found in this design. |
|
--------------------------- |
|
|
========================================================================= |
TIMING REPORT |
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT |
GENERATED AFTER PLACE-and-ROUTE. |
|
Clock Information: |
------------------ |
No clock signals found in this design |
|
Asynchronous Control Signals Information: |
---------------------------------------- |
No asynchronous control signals found in this design |
|
Timing Summary: |
--------------- |
Speed Grade: -5 |
|
Minimum period: No path found |
Minimum input arrival time before clock: No path found |
Maximum output required time after clock: No path found |
Maximum combinational path delay: 6.496ns |
|
Timing Detail: |
-------------- |
All values displayed in nanoseconds (ns) |
|
========================================================================= |
Timing constraint: Default path analysis |
Total number of paths / destination ports: 8 / 8 |
------------------------------------------------------------------------- |
Delay: 6.496ns (Levels of Logic = 3) |
Source: sw<7> (PAD) |
Destination: leds<7> (PAD) |
|
Data Path: sw<7> to leds<7> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 1 0.824 0.357 sw_7_IBUF (sw_7_IBUF) |
INV:I->O 1 0.562 0.357 leds_7_not00001_INV_0 (leds_7_OBUF) |
OBUF:I->O 4.396 leds_7_OBUF (leds<7>) |
---------------------------------------- |
Total 6.496ns (5.782ns logic, 0.714ns route) |
(89.0% logic, 11.0% route) |
|
========================================================================= |
|
|
Total REAL time to Xst completion: 5.00 secs |
Total CPU time to Xst completion: 3.74 secs |
|
--> |
|
|
Total memory usage is 147108 kilobytes |
|
Number of errors : 0 ( 0 filtered) |
Number of warnings : 5 ( 0 filtered) |
Number of infos : 0 ( 0 filtered) |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<DesignSummary rev="1"> |
<CmdHistory> |
</CmdHistory> |
</DesignSummary> |
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn top.prj |
-ifmt mixed |
-ofn top |
-ofmt NGC |
-p xc3s200a-5-vq100 |
-top top |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 500 |
-bufg 24 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6e |
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|
#Release 12.3 - par M.70d (lin) |
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
#Wed Apr 30 20:02:53 2014 |
|
# |
## NOTE: This file is designed to be imported into a spreadsheet program |
# such as Microsoft Excel for viewing, printing and sorting. The | |
# character is used as the data field separator. This file is also designed |
# to support parsing. |
# |
#INPUT FILE: top_map.ncd |
#OUTPUT FILE: top_pad.csv |
#PART TYPE: xc3s200a |
#SPEED GRADE: -5 |
#PACKAGE: vq100 |
# |
# Pinout by Pin Number: |
# |
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, |
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, |
P1,,,TMS,,,,,,,,,,,, |
P2,,,TDI,,,,,,,,,,,, |
P3,,DIFFMLR,IO_L01P_3,UNUSED,,3,,,,,,,,, |
P4,,DIFFSLR,IO_L01N_3,UNUSED,,3,,,,,,,,, |
P5,,DIFFMLR,IO_L02P_3,UNUSED,,3,,,,,,,,, |
P6,,DIFFSLR,IO_L02N_3,UNUSED,,3,,,,,,,,, |
P7,,DIFFSI_NDT,IP_3/VREF_3,UNUSED,,3,,,,,,,,, |
P8,,,GND,,,,,,,,,,,, |
P9,,DIFFMLR,IO_L03P_3/LHCLK0,UNUSED,,3,,,,,,,,, |
P10,,DIFFSLR,IO_L03N_3/LHCLK1,UNUSED,,3,,,,,,,,, |
P11,,,VCCO_3,,,3,,,,,any******,,,, |
P12,,DIFFMLR,IO_L04P_3/LHCLK2,UNUSED,,3,,,,,,,,, |
P13,,DIFFSLR,IO_L04N_3/IRDY2/LHCLK3,UNUSED,,3,,,,,,,,, |
P14,,,GND,,,,,,,,,,,, |
P15,,DIFFMLR,IO_L05P_3/TRDY2/LHCLK6,UNUSED,,3,,,,,,,,, |
P16,,DIFFSLR,IO_L05N_3/LHCLK7,UNUSED,,3,,,,,,,,, |
P17,,,VCCINT,,,,,,,,1.2,,,, |
P18,,,GND,,,,,,,,,,,, |
P19,,DIFFMLR,IO_L06P_3,UNUSED,,3,,,,,,,,, |
P20,,DIFFSLR,IO_L06N_3,UNUSED,,3,,,,,,,,, |
P21,,DIFFMI_NDT,IP_3,UNUSED,,3,,,,,,,,, |
P22,,,VCCAUX,,,,,,,,2.5,,,, |
P23,sw<7>,IBUF,IO_L01P_2/M1,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P24,,DIFFMTB,IO_L02P_2/M2,UNUSED,,2,,,,,,,,, |
P25,leds<7>,IOB,IO_L01N_2/M0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P26,,,VCCO_2,,,2,,,,,2.50,,,, |
P27,leds<5>,IOB,IO_L02N_2/CSO_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P28,sw<5>,IBUF,IO_L03P_2/RDWR_B,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P29,sw<1>,IBUF,IO_L03N_2/VS2,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P30,,DIFFMTB,IO_L04P_2/VS1,UNUSED,,2,,,,,,,,, |
P31,leds<1>,IOB,IO_L04N_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P32,sw<3>,IBUF,IO_L05P_2,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P33,leds<3>,IOB,IO_L05N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P34,sw<2>,IBUF,IO_L06P_2/D7,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P35,leds<2>,IOB,IO_L06N_2/D6,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P36,leds<6>,IOB,IO_L07P_2/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P37,sw<6>,IBUF,IO_L07N_2/D4,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P38,,,VCCINT,,,,,,,,1.2,,,, |
P39,,IBUF,IP_2/VREF_2,UNUSED,,2,,,,,,,,, |
P40,leds<4>,IOB,IO_L08P_2/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P41,sw<4>,IBUF,IO_L08N_2/GCLK15,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P42,,,GND,,,,,,,,,,,, |
P43,sw<0>,IBUF,IO_L09P_2/GCLK0,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE, |
P44,leds<0>,IOB,IO_L09N_2/GCLK1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, |
P45,,,VCCO_2,,,2,,,,,2.50,,,, |
P46,,DIFFSTB,IO_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,, |
P47,,,GND,,,,,,,,,,,, |
P48,,DIFFMTB,IO_L10P_2/INIT_B,UNUSED,,2,,,,,,,,, |
P49,,DIFFSTB,IO_L10N_2/D3,UNUSED,,2,,,,,,,,, |
P50,,DIFFMTB,IO_L11P_2/D2,UNUSED,,2,,,,,,,,, |
P51,,DIFFMTB,IO_L12P_2/D0/DIN/MISO,UNUSED,,2,,,,,,,,, |
P52,,DIFFSTB,IO_L11N_2/D1,UNUSED,,2,,,,,,,,, |
P53,,DIFFSTB,IO_L12N_2/CCLK,UNUSED,,2,,,,,,,,, |
P54,,,DONE,,,,,,,,,,,, |
P55,,,VCCAUX,,,,,,,,2.5,,,, |
P56,,DIFFMLR,IO_L01P_1,UNUSED,,1,,,,,,,,, |
P57,,DIFFSLR,IO_L01N_1,UNUSED,,1,,,,,,,,, |
P58,,,GND,,,,,,,,,,,, |
P59,,DIFFMLR,IO_L02P_1/RHCLK0,UNUSED,,1,,,,,,,,, |
P60,,DIFFSLR,IO_L02N_1/RHCLK1,UNUSED,,1,,,,,,,,, |
P61,,DIFFMLR,IO_L03P_1/RHCLK2,UNUSED,,1,,,,,,,,, |
P62,,DIFFSLR,IO_L03N_1/TRDY1/RHCLK3,UNUSED,,1,,,,,,,,, |
P63,,,GND,,,,,,,,,,,, |
P64,,DIFFMLR,IO_L04P_1/IRDY1/RHCLK6,UNUSED,,1,,,,,,,,, |
P65,,DIFFSLR,IO_L04N_1/RHCLK7,UNUSED,,1,,,,,,,,, |
P66,,,VCCINT,,,,,,,,1.2,,,, |
P67,,,VCCO_1,,,1,,,,,any******,,,, |
P68,,DIFFMI_NDT,IP_1/VREF_1,UNUSED,,1,,,,,,,,, |
P69,,,GND,,,,,,,,,,,, |
P70,,DIFFMLR,IO_L05P_1,UNUSED,,1,,,,,,,,, |
P71,,DIFFSLR,IO_L05N_1,UNUSED,,1,,,,,,,,, |
P72,,DIFFMLR,IO_L06P_1,UNUSED,,1,,,,,,,,, |
P73,,DIFFSLR,IO_L06N_1,UNUSED,,1,,,,,,,,, |
P74,,,GND,,,,,,,,,,,, |
P75,,,TDO,,,,,,,,,,,, |
P76,,,TCK,,,,,,,,,,,, |
P77,,DIFFMTB,IO_L01P_0/VREF_0,UNUSED,,0,,,,,,,,, |
P78,,DIFFSTB,IO_L01N_0,UNUSED,,0,,,,,,,,, |
P79,,,VCCO_0,,,0,,,,,any******,,,, |
P80,,,GND,,,,,,,,,,,, |
P81,,,VCCINT,,,,,,,,1.2,,,, |
P82,,IBUF,IP_0/VREF_0,UNUSED,,0,,,,,,,,, |
P83,,DIFFMTB,IO_L02P_0/GCLK4,UNUSED,,0,,,,,,,,, |
P84,,DIFFSTB,IO_L02N_0/GCLK5,UNUSED,,0,,,,,,,,, |
P85,,DIFFMTB,IO_L03P_0/GCLK6,UNUSED,,0,,,,,,,,, |
P86,,DIFFSTB,IO_L03N_0/GCLK7,UNUSED,,0,,,,,,,,, |
P87,,,GND,,,,,,,,,,,, |
P88,,DIFFMTB,IO_L04P_0/GCLK8,UNUSED,,0,,,,,,,,, |
P89,,DIFFSTB,IO_L04N_0/GCLK9,UNUSED,,0,,,,,,,,, |
P90,,DIFFSTB,IO_0/GCLK11,UNUSED,,0,,,,,,,,, |
P91,,,GND,,,,,,,,,,,, |
P92,,,VCCAUX,,,,,,,,2.5,,,, |
P93,,DIFFMTB,IO_L05P_0,UNUSED,,0,,,,,,,,, |
P94,,DIFFSTB,IO_L05N_0,UNUSED,,0,,,,,,,,, |
P95,,,GND,,,,,,,,,,,, |
P96,,,VCCO_0,,,0,,,,,any******,,,, |
P97,,IBUF,IP_0,UNUSED,,0,,,,,,,,, |
P98,,DIFFMTB,IO_L06P_0/VREF_0,UNUSED,,0,,,,,,,,, |
P99,,DIFFSTB,IO_L06N_0/PUDC_B,UNUSED,,0,,,,,,,,, |
P100,,,PROG_B,,,,,,,,,,,, |
|
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, |
# |
#* Default value. |
#** This default Pullup/Pulldown value can be overridden in Bitgen. |
#****** Special VCCO requirements may apply. Please consult the device |
# family datasheet for specific guideline on VCCO requirements. |
# |
# |
# |
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 19:55:21 04/30/2014 |
-- Design Name: |
-- Module Name: top - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--use IEEE.NUMERIC_STD.ALL; |
|
-- Uncomment the following library declaration if instantiating |
-- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity top is |
Port ( clk_50M : in STD_LOGIC; |
clk_div_1 : in STD_LOGIC; |
clk_div_2 : in STD_LOGIC; |
clk_div_3 : in STD_LOGIC; |
push : in STD_LOGIC_VECTOR (3 downto 0); |
sw : in STD_LOGIC_VECTOR (7 downto 0); |
leds : out STD_LOGIC_VECTOR (7 downto 0)); |
end top; |
|
architecture Behavioral of top is |
|
begin |
|
sw2leds: |
for ii in 0 to 7 generate |
begin |
leds(ii) <= not sw(ii); |
end generate; |
|
end Behavioral; |
|
|
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6 |
###3792:XlxV32DM 24ec eb8eNqlWNly2zgW/RU96G3KaWIjQKKTiizRCSfaIsmO0w/D4tqtmcR24nS6u2T/+1xs3ETZqYpdJu49F7g4OMRGj9PsgDw53pTf9/f725twhF7Q0RjLMwZ/OYG/z4E82998u//2z6fSR4092t+Xo7O70d85uceel559/4I874yNoMko/Vqmo7P919FtVUElW+YjqDE6ux19u71LPqd3L27yQtkvbn435V1ejaDP/Vd43H6Cx91XoPGNZPLsr1Gv59tPoz/2v/8xOvs2QscJ8yYhl7+sJzPEiDOoM5gzfGv4njOQM1wd39Xhrg53dbjLzIUzAmsIV1m4OoISCSoQSV4g9cAISRrGy/XlLrz78/6PX0novaqksND9X79yABAGZHW5U9Cnsrg3oCfPL+P5LNlNNm8ieEzfCkC2Sby8WOXyvPx0P/JeEJBngYR2w/j88iKZRfPJx2Qy+3dyfr66rlqReAnPogUAYxdfnSdAAMC8AdSAPDmdzJKrOPqQXEWbbbxaBnK6Wizi3S6acTndRBMwCjm9/Xxn+ODRIjWu7iRw9uocyRhEUeAvXZKpATU/YWzo21iKFpbxUrVcPmwvt+toOQvJdgf9PjxAy9X5L4Y51zY09OV8NZlFMyYXL7hXQMvFZJ1MF7N5vIyS1XoHo9imGlysZpfzqND2Ll5EkHaxzrRrhwuN0zsul9Huw2rzDssVpIP+fLmeTN9FMyKVSuq56feAmFzPtsn5fDV9l7xZzpLzeDmLl29QMIwnm+hCZapj6/lkGi2i5a5qgZfbyZuok/pqOh1M3cJ16n4b1fXizQZlGp+tlrvEvM7kcnm5jWbJOl5uTdcw+mQDo4ZUeQ3sPq6j1HhvZkk8M1XXs4WTzvYIaZLoegevDXKqRsjk0JOqPf6raKqJoiasMm8/LqftJu1xuSasFTadJ2rBWDk7+OYCSAMlWErx7Dpz9nKyiBCV63ewgLbxmyV0vUi2q8vNNKoUCm49QXy5jeawnEq5qxVVA6u0b9vrkdI+Au8v2sB6N/BVPI0SNZHgnVZdbLMrOsAClmLLh2UQzSykRhAv1vN4Gu9Mll3rJZi+tASawDw+36JCXscwV6/PrmfnsGrRaLu7NMZkO41jX14XWRIX0MF18TlZpP+9/XpVflVniIP2NzVEpToQuMw//S9h3iLQRrH/nqDGxI0Je2X+ufi0vympVHs8kbDjc6k3Pu+VNZAzsDOIM6gzmDP8V4Gs902L8VeZNhIvWcHmYB3UdnDbIW2Hth3Wdvy2w7VDJBx/RN6lX7nUe7zioA3kDAwE6+3fYgSwe2j0Lb0hKZNwFKiTQRcv6u1R48jgqI9jg+M+TgxO+jg1OO3jzOCsj/sG91s4l/bI0hW4qcBbFWBMf4HkZucHEzUmbkzSmLQxWWP6jcm1SSQc+JmsbwK/f2ZSX0mEdFcUyuRDc65MdrsNHC3hRXwdzdon49VkfhmFs/lHL4wvZkfgwwOuIM8mvopcCoTh9HLO/Gq6WG0xC7fz6AM8Vh8eHmD7eTiu8fDw+Pr1HcJUvn79d0rDi9AP0WGLs5CUIQlCRAhDAkxBWHa48UWI5I0fhL4c+zz0ffm4xelA3VxuiQgFDb027BOpqh/BYhjOh+FCFqnGTjOVY1aErJRjjEKRyhuSh4z4SCB4FWOSKWxMCmgGFYMQZvb3HcUmZYi901l9GsIu/55BcXh8z7AqxgzaFdBVoGJjX/c49r0Qdpsxq8JUaYWVbix1LFL5D/OhCwEl0+WcpKF/GPtVyCBVCAfemIQ+JKIhR5AgFESOhXo+vmVE/uazEB9wHmISPr6luZxTGhLdHtrwkHvyBvjIx8xIBe9NPQ9faCq/UF++pZn8DWNoggEvQ1SFj3s/h6py7xemKE2RqeKWp1CMmQh5AAOB1SXfwtv8kym9JIRFN4x6Yd4N417Y74ZJL8y6YdoL026Y9cKkG/Z7YdwN8054LwIbFsKOGzDexZDC/C6GFca6GAEscDoGQzruA94No16YdcO4FybdMOmFUTdMe0OtumHWCxfdsN8LZ91wV8dMy4zV72HMYNrC2qQ8zOSeemp+/Ysq6lAt09UAO6g48eUNrUL1fUhFSGBpqLZc7gnVs5KqEcEk52bx1s24aYZ0szQwzYTr5fFe1yeHl9AdRfIluPBN9B/4e7wP1CLAOkQoYJ58hPxkiD1sqX36+RD96jn2ZJA9PsmeWPa5YU9a7AvLPm+zp4Ps0RH7Yoh9+Rx7OsienGRPLfvCsKct9qVlX7TZs0H25Ih9OcS+eI49G2RPT7Jnln1p2LMW+8qyL9vs/SH25RH5aoh8/hx5f5A8O0net+QrQ95vyKeeJV+1yfNB6UWfvfCG2GfPseeD7P2T7LlhD71p9rzFHhn2EGqxF4PsvSP2aIh9+hx7Mcien2QvLHtk2IsWe2zZozb7dJB9cMQeD7EPnmOfDrIXJ9mnlj027NMWe2LZ4xZ7YfZxou4kKlWh2efyFlcd8r390jP7pfkxG08qDBkqb4lutGeZGUPQa4x0Y1udHQ1ZU2oNGZshG6XS1DTzmyHr+jDkQG+lL8E9OiOAPtwKVQ0QBVo0MIGqcEdXShRDSsAs70tR/owUxZAU/KQUxaAU6UkpCitFYaQojg8coK+lKKwUZQ23pKgGpcB9KQLvZ6Qoh6TwT0pRDUqRnZSislKURorq+PQC+lqK0kgReDXcSBGgQSnokRT4Z6SohqRgp6TQnI6lyE9JoesrKfSR8RLco6MQ6GspKisFruGWFGRIiuJICfoTSqTekBL0pBJkUInipBL2QpZ6RglyfK4CfaVE6lklaA23lGCDk4IfSeH/jBRoSApyUgo2KEV5Ugp7P0qRkYIdH9JAX0uBrBR+Dbek4ENSVEdKiJ9RAg8pgU8qwQeVqE4qYa8rKTZK8OMDH+hrJbBVQtRwS4l0cFKkR1JkPyMFGZICnZQiHZICeyelsLcH6EZLMXB7APpaCmKlyGq4lsJcQvDhPzx1NxB7rVKYcHcqe1FUGHe3RHv1VZjv7r32Lq8w5i7y9utEYdR9mtjvLYUR97FlvyAVht3nox0mYEHqxmhngcK4mwJ2jSiMuQVitxCFEbd/2A1WYcjtrvb8AUxU7vCxx7PCCnc229uLwjJ3dWl92gJfT8NK1+abkRi4sLD7GKMGrizsvnKYhoGXhuvvB9/AxMJ2zavX4OnRGtguAPXGPC2Mge1kUC/X0xrqF39TGmHtvwL+pCWsUkCzBkUNmjcobtCiQUmDlg1KG7RqUFajldegfoOiBuUNimu0oVuRGmx4VbQGGwIVq8FWT34NigbkNZg2oKjBvAGDGiwb0KzLzkZhYpcUrnr4QAhJc+GVHvwQD1NVBQdP+/A9xZVfEIyGfJcPCcyUD++3yp7iQYEHJWkghKdC3DPtqoBXT/lBwYUqC8/0e+QLEWg+/JQfZKps88x/QK/MyzURpwdCT/upV+hxOX36vsvX5lH8AA8k0qDdDw9S8ZSPRKbzC9vvsW/ytXmUP6RHVbTfC0JP+x6t9HiLAHtDvstXCEwcj+oHeLj548br5sspX3h+aftFQz4SnPT0QJ73Q4KUuCvA075Hi7wrSNd3+VqCIA/9kCI+6yrg06d8IawCdkb0fZevpYj+tzgyPOptR19+DVjUoD4SDJjVYObVYNCAZQ02W26e12CzZxdpDbY2fVGD9akBP69fTw8I4zDNfVFQzgE4P+ADDcxVR36hmXw8UNZ2oc768B42L0++h/6R/II85XxByHiQr1IFgQIq/x8j9yUD |
/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc 1398898940 |
OK |
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NETDELAY | |
NETSKEW | |
PATH | |
DEFPERIOD | |
UNCONSTPATH | |
DEFPATH | |
PATH2SETUP | |
UNCONSTPATH2SETUP | |
PATHCLASS | |
PATHDELAY | |
PERIOD | |
FREQUENCY | |
PATHBLOCK | |
OFFSET | |
OFFSETIN | |
OFFSETINCLOCK | |
UNCONSTOFFSETINCLOCK | |
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OFFSETINMOD | |
OFFSETOUT | |
OFFSETOUTCLOCK | |
UNCONSTOFFSETOUTCLOCK | |
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]> |
<twReport><twHead anchorID="1"><twExecVer>Release 12.3 Trace (lin)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3 |
-fastpaths -xml top.twx top.ncd -o top.twr top.pcf |
|
</twCmdLine><twDesign>top.ncd</twDesign><twDesignPath>top.ncd</twDesignPath><twPCF>top.pcf</twPCF><twPcfPath>top.pcf</twPcfPath><twDevInfo arch="spartan3a" pkg="vq100"><twDevName>xc3s200a</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.41 2010-09-15</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="5">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="6">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="7" twNameLen="15"><twPad2PadList anchorID="8" twSrcWidth="5" twDestWidth="7"><twPad2Pad><twSrc>sw<0></twSrc><twDest>leds<0></twDest><twDel>4.987</twDel></twPad2Pad><twPad2Pad><twSrc>sw<1></twSrc><twDest>leds<1></twDest><twDel>5.256</twDel></twPad2Pad><twPad2Pad><twSrc>sw<2></twSrc><twDest>leds<2></twDest><twDel>4.987</twDel></twPad2Pad><twPad2Pad><twSrc>sw<3></twSrc><twDest>leds<3></twDest><twDel>4.991</twDel></twPad2Pad><twPad2Pad><twSrc>sw<4></twSrc><twDest>leds<4></twDest><twDel>4.980</twDel></twPad2Pad><twPad2Pad><twSrc>sw<5></twSrc><twDest>leds<5></twDest><twDel>4.993</twDel></twPad2Pad><twPad2Pad><twSrc>sw<6></twSrc><twDest>leds<6></twDest><twDel>4.980</twDel></twPad2Pad><twPad2Pad><twSrc>sw<7></twSrc><twDest>leds<7></twDest><twDel>4.987</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Apr 30 20:02:58 2014 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue> |
|
Peak Memory Usage: 97 MB |
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport> |
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<?xml version="1.0" encoding="UTF-8"?> |
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<CmdHistory> |
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Release 12.3 - par M.70d (lin) |
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
|
Wed Apr 30 20:02:53 2014 |
|
All signals are completely routed. |
|
|
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<outfile xil_pn:name="xst"/> |
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<transform xil_pn:end_ts="1398898941" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1398898941"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputAdded"/> |
</transform> |
<transform xil_pn:end_ts="1398898947" xil_pn:in_ck="154288912569" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5619283267425655681" xil_pn:start_ts="1398898941"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<outfile xil_pn:name="top.bld"/> |
<outfile xil_pn:name="top.ngd"/> |
<outfile xil_pn:name="top_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1398898958" xil_pn:in_ck="154288912570" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5662573859661895013" xil_pn:start_ts="1398898947"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="top.pcf"/> |
<outfile xil_pn:name="top_map.map"/> |
<outfile xil_pn:name="top_map.mrp"/> |
<outfile xil_pn:name="top_map.ncd"/> |
<outfile xil_pn:name="top_map.ngm"/> |
<outfile xil_pn:name="top_map.xrpt"/> |
<outfile xil_pn:name="top_summary.xml"/> |
<outfile xil_pn:name="top_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1398898979" xil_pn:in_ck="182976548277359827" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="7122883464624052383" xil_pn:start_ts="1398898958"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
<outfile xil_pn:name="top.ncd"/> |
<outfile xil_pn:name="top.pad"/> |
<outfile xil_pn:name="top.par"/> |
<outfile xil_pn:name="top.ptwx"/> |
<outfile xil_pn:name="top.unroutes"/> |
<outfile xil_pn:name="top.xpi"/> |
<outfile xil_pn:name="top_pad.csv"/> |
<outfile xil_pn:name="top_pad.txt"/> |
<outfile xil_pn:name="top_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1398898979" xil_pn:in_ck="154288912438" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1398898974"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
<outfile xil_pn:name="top.twr"/> |
<outfile xil_pn:name="top.twx"/> |
</transform> |
</transforms> |
|
</generated_project> |
vhdl work "top.vhd" |
BtnDemo Project Status | |||
Project File: | +BtnDemo.xise | +Parser Errors: | +No Errors | +
Module Name: | +BtnDemo | +Implementation State: | +Mapped | +
Target Device: | +xc3s1000-4fg320 | +
|
++X +1 Error (1 new) | +
Product Version: | ISE 12.3 | +
|
+1 Warning (1 new) | +
Design Goal: | +Balanced | +
|
++ | +
Design Strategy: | +Xilinx Default (unlocked) | +
|
++ |
Environment: | ++ +System Settings + | +
|
++ |
Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | +Errors | Warnings | Infos | |
Synthesis Report | Current | mié abr 30 19:14:15 2014 | 0 | 1 Warning (1 new) | 1 Info (1 new) | |
Translation Report | Current | mié abr 30 19:14:23 2014 | 0 | 0 | 0 | |
Map Report | Current | mié abr 30 19:14:28 2014 | X 1 Error (1 new) | 0 | 0 | |
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |
+ +
Environment Settings | +||||
Environment Variable | +xst | +ngdbuild | +map | +par | +
LD_LIBRARY_PATH | +/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin | +/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin | +< data not available > | +< data not available > | +
PATH | +/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin: /usr/local/bin: /usr/bin: /bin: /usr/local/games: /usr/games |
+/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin: /usr/local/bin: /usr/bin: /bin: /usr/local/games: /usr/games |
+< data not available > | +< data not available > | +
XILINX | +/opt/Xilinx/12.3/ISE_DS/ISE/ | +/opt/Xilinx/12.3/ISE_DS/ISE/ | +< data not available > | +< data not available > | +
Synthesis Property Settings | +|||
Switch Name | +Property Name | +Value | +Default Value | +
-ifn | ++ | BtnDemo.prj | ++ |
-ifmt | ++ | mixed | +MIXED | +
-ofn | ++ | BtnDemo | ++ |
-ofmt | ++ | NGC | +NGC | +
-p | ++ | xc3s1000-4-fg320 | ++ |
-top | ++ | BtnDemo | ++ |
-opt_mode | +Optimization Goal | +Speed | +Speed | +
-opt_level | +Optimization Effort | +1 | +1 | +
-iuc | +Use synthesis Constraints File | +NO | +NO | +
-keep_hierarchy | +Keep Hierarchy | +No | +NO | +
-netlist_hierarchy | +Netlist Hierarchy | +As_Optimized | +As_Optimized | +
-rtlview | +Generate RTL Schematic | +Yes | +NO | +
-glob_opt | +Global Optimization Goal | +AllClockNets | +AllClockNets | +
-read_cores | +Read Cores | +YES | +YES | +
-write_timing_constraints | +Write Timing Constraints | +NO | +NO | +
-cross_clock_analysis | +Cross Clock Analysis | +NO | +NO | +
-bus_delimiter | +Bus Delimiter | +<> | +<> | +
-slice_utilization_ratio | +Slice Utilization Ratio | +100 | +100% | +
-bram_utilization_ratio | +BRAM Utilization Ratio | +100 | +100% | +
-verilog2001 | +Verilog 2001 | +YES | +YES | +
-fsm_extract | ++ | YES | +YES | +
-fsm_encoding | ++ | Auto | +AUTO | +
-safe_implementation | ++ | No | +NO | +
-fsm_style | ++ | LUT | +LUT | +
-ram_extract | ++ | Yes | +YES | +
-ram_style | ++ | Auto | +AUTO | +
-rom_extract | ++ | Yes | +YES | +
-shreg_extract | ++ | YES | +YES | +
-rom_style | ++ | Auto | +AUTO | +
-auto_bram_packing | ++ | NO | +NO | +
-resource_sharing | ++ | YES | +YES | +
-async_to_sync | ++ | NO | +NO | +
-mult_style | ++ | Auto | +AUTO | +
-iobuf | ++ | YES | +YES | +
-max_fanout | ++ | 500 | +500 | +
-bufg | ++ | 8 | +8 | +
-register_duplication | ++ | YES | +YES | +
-register_balancing | ++ | No | +NO | +
-optimize_primitives | ++ | NO | +NO | +
-use_clock_enable | ++ | Yes | +YES | +
-use_sync_set | ++ | Yes | +YES | +
-use_sync_reset | ++ | Yes | +YES | +
-iob | ++ | Auto | +AUTO | +
-equivalent_register_removal | ++ | YES | +YES | +
-slice_utilization_ratio_maxmargin | ++ | 5 | +0% | +
Translation Property Settings | +|||
Switch Name | +Property Name | +Value | +Default Value | +
-intstyle | ++ | ise | +None | +
-dd | ++ | _ngo | +None | +
-p | ++ | xc3s1000-fg320-4 | +None | +
Operating System Information | +||||
Operating System Information | +xst | +ngdbuild | +map | +par | +
CPU Architecture/Speed | +AMD Athlon(tm) II X2 255 Processor/3100.000 MHz | +AMD Athlon(tm) II X2 255 Processor/3100.000 MHz | +< data not available > | +< data not available > | +
Host | +cudar75 | +cudar75 | +< data not available > | +< data not available > | +
OS Name | +Debian | +Debian | +< data not available > | +< data not available > | +
OS Release | +Debian GNU/Linux 7.4 (wheezy) | +Debian GNU/Linux 7.4 (wheezy) | +< data not available > | +< data not available > | +
{R3951<5289:on><:3:713}i9;0:7c?<:39'54