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URL https://opencores.org/ocsvn/phr/phr/trunk

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Rev 259 → Rev 260

/phr/trunk/codigo/demos/projects/demo1/top.stx --- phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead_run.log (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead_run.log (revision 260) @@ -0,0 +1,13 @@ + +****** PlanAhead v12.3 + **** Build 101344 by hdbuild on Fri Sep 3 23:23:03 PDT 2010 + ** Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. + +INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead +INFO: [HD-Licensing 1] Got a license: PlanAhead +INFO: [HD-ArchReader 0] Loading parts and site information from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/arch.xml +INFO: [HD-RTPRIM 0] Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml' +INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml' +starting gui ... +INFO: [HD-Application 0] Exiting PlanAhead... +INFO: [HD-Licensing 2] Releasing license: PlanAhead
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/demo1.ppr
0,0 → 1,8
<?xml version="1.0"?>
<Project Version="4" Minor="6">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
</Project>
 
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.jou
0,0 → 1,21
#-----------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Fri Sep 3 23:23:03 PDT 2010
# Start of session at: Wed Apr 30 20:14:26 2014
# Process ID: 25658
# Log file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.log
# Journal file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui -source /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl
# create_project -name demo1 -dir "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1" -part xc3s200avq100-5
# set_param project.pinAheadLayout yes
# set srcset [get_property srcset [current_run -impl]]
# set_property top top $srcset
# set_param project.paUcfFile "top.ucf"
# set hdlfile [add_files [list {top.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# add_files "top.ucf" -fileset [get_property constrset [current_run]]
# add_files -norecurse { {/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1} }
# open_rtl_design -part xc3s200avq100-5
exit
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/demo1.data/sources_1/fileset.xml
0,0 → 1,16
<?xml version="1.0"?>
<DARoots Version="1" Minor="7">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd">
</File>
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc">
<FileInfo RelPath="top.ngc"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
</Config>
</FileSet>
</DARoots>
 
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/demo1.data/wt/webtalk_pa.xml
0,0 → 1,27
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Apr 30 20:16:28 2014">
<section name="Project Information" visible="false">
<property name="ProjectID" value="e92a26838f3f4b93bb9ba2bb56b2943f" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Other">
<property name="GuiMode" value="0" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="2" type="ISEMode"/>
</item>
</section>
</application>
</document>
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/demo1.data/constrs_1/fileset.xml
0,0 → 1,12
<?xml version="1.0"?>
<DARoots Version="1" Minor="7">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ucf">
</File>
<Config>
<Option Name="TargetPart" Val="xc3s200avq100-5"/>
</Config>
</FileSet>
</DARoots>
 
/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.log
0,0 → 1,72
#-----------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Fri Sep 3 23:23:03 PDT 2010
# Start of session at: Wed Apr 30 20:14:26 2014
# Process ID: 25658
# Log file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.log
# Journal file: /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
INFO: [HD-Licensing 1] Got a license: PlanAhead
INFO: [HD-ArchReader 0] Loading parts and site information from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/arch.xml
INFO: [HD-RTPRIM 0] Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml'
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file '/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml'
start_gui -source /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl
# create_project -name demo1 -dir "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1" -part xc3s200avq100-5
# set_param project.pinAheadLayout yes
# set srcset [get_property srcset [current_run -impl]]
# set_property top top $srcset
# set_param project.paUcfFile "top.ucf"
# set hdlfile [add_files [list {top.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# add_files "top.ucf" -fileset [get_property constrset [current_run]]
# add_files -norecurse { {/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1} }
# open_rtl_design -part xc3s200avq100-5
INFO: [HD-RTLIN 2] Parsing VHDL file "/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
INFO: [HD-RTLIN 2] Parsing package <attributes>.
INFO: [HD-RTLIN 2] Parsing VHDL file "/opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
INFO: [HD-RTLIN 2] Parsing package <attributes>.
INFO: [HD-RTLIN 2] Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <top>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <top>.
INFO: [HD-RTLIN 2] Elaborating entity <top> (architecture <Behavioral>) from library <work>.
INFO: [HD-ArchReader 18] Reading macro library /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn
INFO: [HD-EDIFIN 0] Parsing Edif File '/opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '/opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/hd_int_macros.edn'
INFO: [HD-ArchReader 7] Loading clock regions from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/ClockRegion.xml
INFO: [HD-ArchReader 8] Loading clock buffers from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/ClockBuffers.xml
INFO: [HD-ArchReader 3] Loading package from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/vq100/Package.xml
INFO: [HD-ArchReader 4] Loading io standards from /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/IOStandards.xml
INFO: [HD-ArchReader 5] Loading pkg sso from /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/xc3s200a/vq100/SSORules.xml
INFO: [HD-GDRC 0] Loading list of drcs for the architecture : /opt/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan3a/drc.xml
INFO: [HD-UCFReader 0] Parsing UCF File : ./top.ucf
INFO: [HD-UCFReader 1] Finished Parsing UCF File : ./top.ucf
 
DESIGN RULE CHECK VIOLATION REPORT
Build: PlanAhead v12.3 by hdbuild
on Fri Sep 3 23:23:03 PDT 2010
Report: by lguanuco on host cudar75, pid 25658
on Wed Apr 30 20:14:39 2014
 
REPORT SUMMARY
Netlist: top
Floorplan: <none>
Design limits: <entire design considered>
Checks: Unknown block name
Unknown Unisim pin name
Mismatching Attribute
Max vios: <unlimited>
Vios found: 1
 
REPORT DETAILS
ULMN#1
Unknown block name - <no location>
Block name RTL_INV is not a valid Unisim for the specified architecture. No block of type RTL_INV exists in the Unisim library for the spartan3a architecture.
Related Vios: <none>
 
INFO: [HD-LIB 0] Reading timing library /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/spartan3a-5.lib .
INFO: [HD-LIB 1] Done reading timing library /opt/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan3a/spartan3a/spartan3a-5.lib .
exit
INFO: [HD-Application 0] Exiting PlanAhead...
INFO: [HD-Licensing 2] Releasing license: PlanAhead
/phr/trunk/codigo/demos/projects/demo1/top_summary.html
0,0 → 1,131
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>top Project Status (04/30/2014 - 20:02:59)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>demo1.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s200a-5vq100</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/*.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>68</TD>
<TD ALIGN=RIGHT>23%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.00</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:20 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/xst.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.bld'>Translation Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:27 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:37 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:53 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>mié abr 30 20:02:58 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/_xmsgs/trce.xmsgs?&DataKey=Info'>5 Infos (5 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 04/30/2014 - 20:06:03</center>
</BODY></
/phr/trunk/codigo/demos/projects/demo1/top.par
0,0 → 1,158
Release 12.3 par M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
cudar75:: Wed Apr 30 20:02:41 2014
 
par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf
 
 
Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s200a.nph' in environment /opt/Xilinx/12.3/ISE_DS/ISE/.
"top" is an NCD, version 3.2, device xc3s200a, package vq100, speed -5
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
 
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
 
Device speed data version: "PRODUCTION 1.41 2010-09-15".
 
 
Design Summary Report:
 
Number of External IOBs 16 out of 68 23%
 
Number of External Input IOBs 8
 
Number of External Input IBUFs 8
 
Number of External Output IOBs 8
 
Number of External Output IOBs 8
 
Number of External Bidir IOBs 0
 
 
 
 
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
 
Starting initial Timing Analysis. REAL time: 3 secs
Finished initial Timing Analysis. REAL time: 3 secs
 
 
Starting Placer
Total REAL time at the beginning of Placer: 3 secs
Total CPU time at the beginning of Placer: 1 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7d) REAL time: 6 secs
 
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:7d) REAL time: 6 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:7d) REAL time: 6 secs
 
Phase 4.2 Initial Clock and IO Placement
...
Phase 4.2 Initial Clock and IO Placement (Checksum:7d) REAL time: 6 secs
 
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:7d) REAL time: 6 secs
 
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:7d) REAL time: 6 secs
 
Phase 7.3 Local Placement Optimization
..
Phase 7.3 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs
 
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:91a3910) REAL time: 6 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:91a3910) REAL time: 6 secs
 
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:7f12344) REAL time: 6 secs
 
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:7f12344) REAL time: 6 secs
 
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 2 secs
Writing design to file top.ncd
 
 
 
Starting Router
 
 
Phase 1 : 8 unrouted; REAL time: 10 secs
 
Phase 2 : 8 unrouted; REAL time: 10 secs
 
Phase 3 : 0 unrouted; REAL time: 10 secs
 
Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Updating file: top.ncd with current fully routed design.
 
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 11 secs
 
Total REAL time to Router completion: 11 secs
Total CPU time to Router completion: 5 secs
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
Timing Score: 0 (Setup: 0, Hold: 0)
 
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 11 secs
Total CPU time to PAR completion: 5 secs
 
Peak Memory Usage: 143 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
 
Writing design to file top.ncd
 
 
 
PAR done!
/phr/trunk/codigo/demos/projects/demo1/top.ngr
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$55x03=(`fgn#aizaow`k*iwmgid~h} pip,pwsic&idhdi`/egnkv)wzf`noy} ddol5*rhx'|chi5<s323esw689'>=<5;:HLSQQ<w}zb7?7>1f::9MKVR\3y|0:4?>008<?IR\Y__6akks=594;d<03fnh~28:1<:?=<t5=1<364BTQ\MK@H12IDA@G[TDF4?FTBI]OO=6G<;HLU3>JHO@IJ@:5B.62g[I7<G=1[M_Zn;QKM[GSTAMRi7]GA_CWPJDKB;2X_@o5\IF@VWZOINFk0_DIPBTQJ@]d<[@MTNX]AALG7?Q_WM01]EHYPTXRF5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^T\ECI=h5WSU]JIUJBELD_MYG@N^ALJVRUI@D__<>4XRV\VQJXX[E[I_ZV6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv:?]usODeoia94cmi\15K>3jf`Sigy_0;8gimXl`|T>45llj]gmsY4?2fnh~2?>69oaau;97=0`hj|<3<4?icc{595;6bjdr>7:2=kmmy79394ldfp838>3eoo1950?58h`bt4>49>6bjdr]3[kis89:;Sdc_mggwZ6Xff~;<=>>239oaauX9Vddx=>?0^kntZjblzU:Sca{0123574<dlnxS?Qaou2345YneyUgii}P2^llp56788897akks^1\jjr789:Te`~Pldfp[6Yig}:;<=?=2:nf`vY3Wge<=>?_hos[icc{V>Tbbz?012267=kmmyT9R``t1234ZojxVfnh~Q:_omw45679;80`hj|_7]mkq6789Uba}Qceeq\2Zhh|9:;<<<=;mggwZ1Xff~;<=>Pilr\h`btW>Uecy>?0134?ust`5:5;6~zsi>2:2=w}zb7>374ptqk86<76>1{y~f33?d8wjsuklUmeakaalg6?vq;87?0z2>>49ps949=2y|0>0:;ru?0;3<{~6>285|w=4=3>up4>0;285|w=5=7>rhx8:0tn=|212b)0+qy8:;qMN4`9CD}472O096<u\9;3e>a<6;:?:4h4<826:k7c281e=h49;%3`>4><uZ21=k4k:01014>b2:288n5k4483>4<6sZ31=k4k:01014>b2:28845yF0094?7=93:p_44>f;f9565291o1?5=;9:&23?e<,o0:7o:::182<?>=99qG=l4>{%d903=zD8h1=v*<b;28y!712=?0V:4<{581>6<zR891>v;56;j67<722c9?7>5;h07>5<<a;;1<75`2e83>!762;i0b<>50:9l6g<72-;:6?m4n0295>=h:h0;6)?>:3a8j46=:21d>44?:%32>7e<f8:1?65`2983>!762;i0b<>54:9l62<72-;:6?m4n0291>=h:?0;6)?>:3a8j46=>21d>84?:%32>7e<f8:1;65f3`83>!762:30b<>50:9j7=<72-;:6>74n0295>=n;>0;6)?>:2;8j46=:21b?;4?:%32>6?<f8:1?65f4583>!762=90b<>50:9j07<72-;:69=4n0295>=n<80;6)?>:518j46=:21b8=4?:%32>15<f8:1?65f3g83>!762=90b<>54:9j7`<72-;:69=4n0291>=n;m0;6)?>:518j46=>21b?n4?:%32>15<f8:1;65m2d83>7<729q/=;4m;I3:?lg=831di7>5;|`1b?6=:3:1<v*>6;`8L4?<ah0;66aj:188yg5729096=4?{%35>g=O901bm7>5;ng94?=zj:;1<7<50;2x 40=j2B:56gn:188k`<722wi??4?:383>5}#9?0i7E?6;hc94?=hm3:17pl<3;296?6=8r.::7l4H0;8md<722en6=44}c17>5<5290;w)?9:c9K5<=ni3:17bk50;9~f63=8381<7>t$049f>N612cj6=44od83>>{t:m0;6?uQ2e9>70<b3-;>6?m4n0694>{t:k0;6?uQ2c9>71<b3-;>6?m4n0695>{t:h0;6?uQ2`9>76<b3-;>6?m4n0696>{t:00;6?uQ289>77<b3-;>6?m4n0697>{t:10;6?uQ299>74<b3-;>6?m4n0690>{t:>0;6?uQ269>75<b3-;>6?m4n0691>{t:?0;6?uQ279>6c<b3-;>6?m4n0692>{t:<0;6?uQ249>6`<b3-;>6?m4n0693>{t<=0;6?uQ459>70<f3-;>69=4n0694>{t<;0;6?uQ439>71<f3-;>69=4n0695>{t<80;6?uQ409>76<f3-;>69=4n0696>{t<90;6?uQ419>77<f3-;>69=4n0697>{t;o0;6?uQ3g9>74<f3-;>69=4n0690>{t;l0;6?uQ3d9>75<f3-;>69=4n0691>{t;m0;6?uQ3e9>6c<f3-;>69=4n0692>{t;j0;6?uQ3b9>6`<f3-;>69=4n0693>{zutwKLNu;a;4432`?<>wKLOu?}ABSxFG
/phr/trunk/codigo/demos/projects/demo1/top_map.xrpt
0,0 → 1,280
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="12.3">
 
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
 
<application stringID="Map" timeStamp="Wed Apr 30 20:02:37 2014">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:/usr/local/bin:/usr/bin:/bin:/usr/local/games:/usr/games"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE/"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Debian"/>
<item stringID="User_EnvOsrelease" value="Debian GNU/Linux 7.4 (wheezy)"/>
</item>
<item stringID="User_EnvHost" value="cudar75"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="AMD Athlon(tm) II X2 255 Processor"/>
<item stringID="speed" value="3100.000 MHz"/>
</row>
</table>
</section>
<section stringID="MAP_OPTION_SUMMARY">
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
<item DEFAULT="area" label="-cm" stringID="MAP_COVER_MODE" value="area"/>
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="top_map.ncd"/>
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc3s200a-vq100-5"/>
</section>
<task stringID="MAP_PACK_REPORT">
<section stringID="MAP_DESIGN_INFORMATION">
<item stringID="MAP_PART" value="3s200avq100-5"/>
<item stringID="MAP_DEVICE" value="xc3s200a"/>
<item stringID="MAP_ARCHITECTURE" value="spartan3a"/>
<item stringID="MAP_PACKAGE" value="vq100"/>
<item stringID="MAP_SPEED" value="-5"/>
</section>
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="163088"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE_SLICEL" value="896"/>
<item dataType="int" stringID="MAP_AVAILABLE_SLICEM" value="896"/>
<item dataType="int" stringID="MAP_FLOPS_PER_SLICE" value="2"/>
<item dataType="int" stringID="MAP_LUTS_PER_SLICE" value="2"/>
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEL" value="0"/>
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="0"/>
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="0"/>
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
</section>
<section stringID="MAP_IOB_REPORTING">
<section stringID="MAP_IOB_DATA">
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
<item AVAILABLE="68" dataType="int" stringID="MAP_AGG_BONDED_IO" value="16"/>
<item AVAILABLE="204" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_DIFFM" value="0"/>
<item AVAILABLE="48" dataType="int" stringID="MAP_NUM_DIFFMTB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFM" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFMTB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_DIFFS" value="0"/>
<item AVAILABLE="48" dataType="int" stringID="MAP_NUM_DIFFSTB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFSTB" value="0"/>
</section>
</section>
<section stringID="MAP_HARD_IP_REPORTING">
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB16" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MULT18X18" value="0"/>
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_DCM" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_CAPTURE" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_DCIRESET" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_DNA_PORT" value="0"/>
<item AVAILABLE="16" dataType="int" stringID="MAP_NUM_MULT18X18SIO" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SPI_ACCESS" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
</section>
<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
<section stringID="MAP_IOB_PROPERTIES">
<table stringID="MAP_IOB_TABLE">
<column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
<column stringID="Type"/>
<column stringID="Direction"/>
<column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
<column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
<column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
<column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
<column label="Reg&#xA;(s)" stringID="REGS"/>
<column stringID="Resistor"/>
<column label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY"/>
<column label="Suspend" stringID="SUSPEND"/>
<row stringID="row" value="1">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="2">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="3">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="4">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="5">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="6">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="7">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="8">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="leds&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
<item label="Suspend" stringID="SUSPEND" value="3STATE"/>
</row>
<row stringID="row" value="9">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;0>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="10">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;1>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="11">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;2>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="12">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;3>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="13">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;4>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="14">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;5>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="15">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;6>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="16">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sw&lt;7>"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IBUF/IFD&#xA;Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/>
</row>
</table>
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="0"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
<section stringID="MAP_TIMING_REPORT"/>
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION"/>
</task>
</application>
 
</document>
/phr/trunk/codigo/demos/projects/demo1/top_xst.xrpt
0,0 → 1,141
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="12.3">
 
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
 
<application stringID="Xst" timeStamp="Wed Apr 30 20:02:15 2014">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:/usr/local/bin:/usr/bin:/bin:/usr/local/games:/usr/games"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE/"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Debian"/>
<item stringID="User_EnvOsrelease" value="Debian GNU/Linux 7.4 (wheezy)"/>
</item>
<item stringID="User_EnvHost" value="cudar75"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="AMD Athlon(tm) II X2 255 Processor"/>
<item stringID="speed" value="3100.000 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="top.prj"/>
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="top"/>
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s200a-5-vq100"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="top"/>
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
<item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
<item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
<item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
<item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
<item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
<item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
<item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
<item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
<item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
<item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
<item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
<item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
<item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
<item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
<item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
<item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
<item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
<item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="500"/>
<item DEFAULT="24" label="-bufg" stringID="XST_BUFG" value="24"/>
<item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
<item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
<item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
<item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
<item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
<item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
<item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
<item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_FINAL_REPORT">
<section stringID="XST_FINAL_RESULTS">
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="top.ngr"/>
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="top"/>
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="24"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="8">
<item dataType="int" stringID="XST_INV" value="8"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="16">
<item dataType="int" stringID="XST_IBUF" value="8"/>
<item dataType="int" stringID="XST_OBUF" value="8"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s200avq100-5"/>
<item AVAILABLE="1792" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="4"/>
<item AVAILABLE="3584" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="8"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="24"/>
<item AVAILABLE="68" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="16"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="5"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section>
</application>
 
</document>
/phr/trunk/codigo/demos/projects/demo1/top_map.mrp
0,0 → 1,159
Release 12.3 Map M.70d (lin)
Xilinx Mapping Report File for Design 'top'
 
Design Information
------------------
Command Line : map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off
-c 100 -o top_map.ncd top.ngd top.pcf
Target Device : xc3s200a
Target Package : vq100
Target Speed : -5
Mapper Version : spartan3a -- $Revision: 1.52 $
Mapped Date : Wed Apr 30 20:02:32 2014
 
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic: 0 out of 0 0%
Number of Slices containing unrelated logic: 0 out of 0 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Number of bonded IOBs: 16 out of 68 23%
 
Average Fanout of Non-Clock Nets: 1.00
 
Peak Memory Usage: 159 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 2 secs
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
 
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network clk_div_1 has no load.
INFO:LIT:395 - The above info message is repeated 7 more times for the following
(max. 5 shown):
clk_div_2,
clk_div_3,
clk_50M,
push<3>,
push<2>
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
 
Section 4 - Removed Logic Summary
---------------------------------
 
Section 5 - Removed Logic
-------------------------
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND |
| | | | | Term | Strength | Rate | | | Delay | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| leds<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| leds<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
| sw<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
| sw<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
No area groups were found in this design.
 
----------------------
 
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
 
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
 
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
/phr/trunk/codigo/demos/projects/demo1/top.lso
0,0 → 1,159
work
/phr/trunk/codigo/demos/projects/demo1/top_envsettings.html
0,0 → 1,475
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin</td>
</tr>
<tr>
<td>PATH</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/games:<br>/usr/games</td>
</tr>
<tr>
<td>XILINX</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td>
<td>/opt/Xilinx/12.3/ISE_DS/ISE/</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>top.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>MIXED</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>top</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s200a-5-vq100</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>top</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-verilog2001</td>
<td>Verilog 2001</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-mult_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>500</td>
<td>500</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>24</td>
<td>24</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0%</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s200a-vq100-5</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-cm</td>
<td>Optimization Strategy (Cover Mode)</td>
<td>area</td>
<td>area</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-o</td>
<td>&nbsp;</td>
<td>top_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s200a-vq100-5</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-t</td>
<td>&nbsp;</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td>
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td>
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td>
<td>AMD Athlon(tm) II X2 255 Processor/3100.000 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>cudar75</td>
<td>cudar75</td>
<td>cudar75</td>
<td>cudar75</td>
</tr>
<tr>
<td>OS Name</td>
<td>Debian</td>
<td>Debian</td>
<td>Debian</td>
<td>Debian</td>
</tr>
<tr>
<td>OS Release</td>
<td>Debian GNU/Linux 7.4 (wheezy)</td>
<td>Debian GNU/Linux 7.4 (wheezy)</td>
<td>Debian GNU/Linux 7.4 (wheezy)</td>
<td>Debian GNU/Linux 7.4 (wheezy)</td>
</tr>
</TABLE>
</BODY> </HTML>
/phr/trunk/codigo/demos/projects/demo1/top.bld
0,0 → 1,35
Release 12.3 ngdbuild M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
Command Line: /opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -i -p xc3s200a-vq100-5 top.ngc top.ngd
 
Reading NGO file
"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc" ...
Gathering constraint information from source properties...
Done.
 
Resolving constraint associations...
Checking Constraint Associations...
Done...
 
Checking expanded design ...
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
 
Total memory usage is 86904 kilobytes
 
Writing NGD file "top.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 2 sec
 
Writing NGDBUILD log file "top.bld"...
/phr/trunk/codigo/demos/projects/demo1/top_map.ncd
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###3208:XlxV32DM 1f39 c70eNqll9ly2zgWhl9FF7qbspsACIIkOilLIu1woi2S7Dh9ERbXHs3Y8qIk3V2S3n0OFm4SaV04KYsH38Hy4ycJgH0H7TC/oPCXEPh7dPjFevNj++Ofh8xCVdxbb7PexXPv74RssWFEF79ekGFc0B406UWvWdS7WL/2nvIcKulr0oMavYun3o+n5/Axer7cJKmILzd/qutzkvdgzPUr/DzDD1QnnFwi8YMR4qYbTOe3K/f55/Y/vxPX+JhzW6PtX78zAAgDmd2uBHrI0q2CBh/eBmMvXA0WNz78jD7ZQJZhML2eJXyYPWx7xiXpod4E2bLoBsPb69Dzx4Nv4cD7dzgczu7zWiaYwm9aA/OBV+RnwxAEAEwqAGkQMRp44V3gfw3v/MUymE0dPppNJsFq5XuMjxb+AIKUj54en5Ue3JtEqigHcYp4NkQ8AFME/K0pMlJQ6rNVDGOrSMjCPJiKltP98nY596eeS5YrGHe/h5az4W9KOZMxNKR8csmMFFpMBvNwNPHGwdQPZ/MVqF9GEk5m3u3YT2W8CiY+dDeZx7KopwmNo2fGp/7q62zxGfMZdAfjWHw+GH32PcKFO5TPvWU4HM9Gn8ObqRcOg6kXTG+Q087DhX8N3VS5+Xgw8if+dJXX4O1ycOM3ur4bjVq7rnHZ9XEbMfTkZpFIDDMJV9/mfqRKN14YeGrYuTcpZq27mAfT0L9fgdO+Jxsh1Yd8DuoTuvNHcmRUpUXPy2/TUb1JXWjRhNbSavBQPOPanwZfXINokARPf+Ddx0U8HUx8ZPL5Z3jml8HNFIaehMvZ7WLk54JCsby3Fl/6Y3gDMr4qLRITy2VZt5czNY8J3BB/Aa+ownfByA/FMwA3KW+yxSptgAm8PbUyPLm+p5GYQTCZj4NRsFK9rGo3QY0lLZACxsFwiVJ+H8CDfH9x7w3hRUO95epWBYPlKAgsfp/GYZDCAPfpYziJ/vv0epe9btdPmwKtNyUyuVjsGE8e/hdSY+LIIF3/ClEV4iokUPMxfVhvMsJhBWVcrlLGRx2gIsBFQIrALAJaBNZHh5eLnGbsYyyD0Ahn8CbrAqoXcL1A6gWzXqD1glUvMFkgHBZ1xuVaLIaXASoCDNrKZVozAmz7HL3+iDYkohyWbLGCy8tluYxJjhRHxxwrjo85UZwcc1Nx85hTxekxtxS3apxxvbXICkxVYLUKMKe/wG21QkOIqhBXIalCswppFVpVyGRIOGyJMS/3yj8fKZd7rM2LPdekfF+t/4PVagFbgHsd3PtefQe7G4xvfdcbfzPc4No7gfs9zqGfRXDnF10gDLtMURjfjSazJabucux/hZ/Z1/0e1pz9aY39/nB19YxQzq+u/rYj99rFLtotEXOx42LTRYRQZGcusQmNdxtquIhvKHIt3jdz18z4YYmslroJT6E3qN3dG/RAXRM6Sl1m8A1mLiUWshG41ceWYH1sQyuoh1w75r9WOFU9uth4o9PEtfkXksDAhy8kEpc+sV2H9xGFTN90ZNem7dopXJhrJ3ABrXxj4kJCxP8h0GNmwzWV1zG4ae36lLkgCLkMxLlw4uoTl0KnkIt43xK/h08k5n+YqYt3yHZz9xArI2wXid/dCzH5CzH4J0L5HzDGLnEjN3YPa2pCNb6mVF0sdSHi8mQhuPRNw7VAJslB7Ccz5j8JGGBw/kTzZhodpbNmGh+l02aaHKWTZto8SsfNND1KR820dZR2mmnWSK+tcmKZnjewtMmQYEmTYcHiJiPAbEMzlrf4uGZpM42O0nEzjY/STjNNjtKsmTaP0rSZpkdp0kxbR2nUTDd9jKXNWPzf9U14ZSK+xmIy/F9YPBs8trCsAPbs+gReMAy9MHhi4QGHRojLVrD/YUM+j1j4zQ+qX1Q1I6oZks3sXDUzi1EOW1mf7D7AcDjhH6CIM/4d/g5bWypQKQNYzA/Qf3RON2nTnZ+THbXKxp2yIy2bKNlRTTbRsklddnxOttkmOzsnO26VTTplx1q2qWTHNdmmlm3WZSfnZNM22ek52UmrbLNTdqJlUyU7qcmmWjaty07PybbaZCfnZKetsmmn7FTLtpTstCbb0rKtuuzsnGzWJjs+JztrlW11ys60bKZkZzXZTMtmddn5Odl2m+zonOy8VTbrlJ1r2baSnddk21q2XZMtd9A3ZTttsp0zsmW3p7LtLtmyvpDtSNlQrGQ7WrZTk82UbAJtZFcOf0IN2ay5cMOHp1wA1T+1oNiZkmFA21yeKkyi1NtHjVPZ2FbV0clkWXOyKFOTVR45hmqGq8kyPVlbLukfGDpd7UG+SbiskYgWFYYj6XekPCDnPDDf4wFp84B1ekBaPYg6PSDaA6I8IKdbB8iXHhDtgVnimgf0nAfWezww2zywOj2grR7EnR5Q7YGpPKCn+xDIlx6Y2gOrxDUP2DkP7Pd4QNs8oJ0esFYPkk4PmPaAKg/Y6aYG8qUHVHtgl7jmgXPOg+g9HlhtHpidHjitHqSdHujTn20pD5zTHRLkSw8s7UFU4poH8TkPkvd4wNo8IJ0exK0eZJ0e6DOZzZQH8el2C/KlB0x7kJS45kF6zoPsPR7YbR7gTg/SVg/yTg/0Scm2lQfp6d4N8qUHtvYgK3HlgfyYe8sDG73HA6fNA9TlgRRz4gE2ujyQ9YUHcrf/AMWTgwDIlx44ygM1G4lLD9R5Au++W6g4TOijETCaF+cifcoTLCuOePrAKlhanFb12Vuw8uCtPyMEi4tvCP1FJFhUfA7pjzvBnOLLTk8TmF3OUd9+YCwt7r1+LQSLi3dCLxeCOcVaoZdRwVixhurtRTBa7C162xWMFHuuPo4IhoqzSHUOEXpjiYWv5dYsphbLHhTWu5VwIZaDKawXcGFYLHUprNc04W0sp6Cwfs3FbVCzVVg/+eKOxdIYhYtTIZIYPJQ3fpOpMfVX+k8CCyYHalUUVZRVFFfUriipqFNRs6JRRWlF44paFU0qyiqalrQmNythTVdewkpAbpSwGilHJbQriEsYVZCUMKmgWcKsguqs0lgoypz1Ro69kbPfyDlv5KI3cvEbuaQ7J1cRpHIVzEuYltBJSxiXMIpL6JQwdkpY3fCElbB6YlJawtojR0pYPrPw7+pqtEModbMIxwlBGMBwh3dEH8D5C6H8sMN5vQh15rsvMLLBv4DpiL/EIn5JZCx6i8QlgwtU/T9g13Zu
/phr/trunk/codigo/demos/projects/demo1/top_pad.txt
0,0 → 1,130
Release 12.3 - par M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
Wed Apr 30 20:02:53 2014
 
 
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
 
INPUT FILE: top_map.ncd
OUTPUT FILE: top_pad.txt
PART TYPE: xc3s200a
SPEED GRADE: -5
PACKAGE: vq100
 
Pinout by Pin Number:
 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage |Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|P1 | | |TMS | | | | | | | | | | | |
|P2 | | |TDI | | | | | | | | | | | |
|P3 | |DIFFMLR |IO_L01P_3 |UNUSED | |3 | | | | | | | | |
|P4 | |DIFFSLR |IO_L01N_3 |UNUSED | |3 | | | | | | | | |
|P5 | |DIFFMLR |IO_L02P_3 |UNUSED | |3 | | | | | | | | |
|P6 | |DIFFSLR |IO_L02N_3 |UNUSED | |3 | | | | | | | | |
|P7 | |DIFFSI_NDT|IP_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | |
|P9 | |DIFFMLR |IO_L03P_3/LHCLK0 |UNUSED | |3 | | | | | | | | |
|P10 | |DIFFSLR |IO_L03N_3/LHCLK1 |UNUSED | |3 | | | | | | | | |
|P11 | | |VCCO_3 | | |3 | | | | |any******| | | |
|P12 | |DIFFMLR |IO_L04P_3/LHCLK2 |UNUSED | |3 | | | | | | | | |
|P13 | |DIFFSLR |IO_L04N_3/IRDY2/LHCLK3|UNUSED | |3 | | | | | | | | |
|P14 | | |GND | | | | | | | | | | | |
|P15 | |DIFFMLR |IO_L05P_3/TRDY2/LHCLK6|UNUSED | |3 | | | | | | | | |
|P16 | |DIFFSLR |IO_L05N_3/LHCLK7 |UNUSED | |3 | | | | | | | | |
|P17 | | |VCCINT | | | | | | | |1.2 | | | |
|P18 | | |GND | | | | | | | | | | | |
|P19 | |DIFFMLR |IO_L06P_3 |UNUSED | |3 | | | | | | | | |
|P20 | |DIFFSLR |IO_L06N_3 |UNUSED | |3 | | | | | | | | |
|P21 | |DIFFMI_NDT|IP_3 |UNUSED | |3 | | | | | | | | |
|P22 | | |VCCAUX | | | | | | | |2.5 | | | |
|P23 |sw<7> |IBUF |IO_L01P_2/M1 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P24 | |DIFFMTB |IO_L02P_2/M2 |UNUSED | |2 | | | | | | | | |
|P25 |leds<7> |IOB |IO_L01N_2/M0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P26 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P27 |leds<5> |IOB |IO_L02N_2/CSO_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P28 |sw<5> |IBUF |IO_L03P_2/RDWR_B |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P29 |sw<1> |IBUF |IO_L03N_2/VS2 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P30 | |DIFFMTB |IO_L04P_2/VS1 |UNUSED | |2 | | | | | | | | |
|P31 |leds<1> |IOB |IO_L04N_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P32 |sw<3> |IBUF |IO_L05P_2 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P33 |leds<3> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P34 |sw<2> |IBUF |IO_L06P_2/D7 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P35 |leds<2> |IOB |IO_L06N_2/D6 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P36 |leds<6> |IOB |IO_L07P_2/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P37 |sw<6> |IBUF |IO_L07N_2/D4 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P38 | | |VCCINT | | | | | | | |1.2 | | | |
|P39 | |IBUF |IP_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|P40 |leds<4> |IOB |IO_L08P_2/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P41 |sw<4> |IBUF |IO_L08N_2/GCLK15 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P42 | | |GND | | | | | | | | | | | |
|P43 |sw<0> |IBUF |IO_L09P_2/GCLK0 |INPUT |LVCMOS25* |2 | | | |IBUF | |UNLOCATED |NO |NONE |
|P44 |leds<0> |IOB |IO_L09N_2/GCLK1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P46 | |DIFFSTB |IO_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|P47 | | |GND | | | | | | | | | | | |
|P48 | |DIFFMTB |IO_L10P_2/INIT_B |UNUSED | |2 | | | | | | | | |
|P49 | |DIFFSTB |IO_L10N_2/D3 |UNUSED | |2 | | | | | | | | |
|P50 | |DIFFMTB |IO_L11P_2/D2 |UNUSED | |2 | | | | | | | | |
|P51 | |DIFFMTB |IO_L12P_2/D0/DIN/MISO |UNUSED | |2 | | | | | | | | |
|P52 | |DIFFSTB |IO_L11N_2/D1 |UNUSED | |2 | | | | | | | | |
|P53 | |DIFFSTB |IO_L12N_2/CCLK |UNUSED | |2 | | | | | | | | |
|P54 | | |DONE | | | | | | | | | | | |
|P55 | | |VCCAUX | | | | | | | |2.5 | | | |
|P56 | |DIFFMLR |IO_L01P_1 |UNUSED | |1 | | | | | | | | |
|P57 | |DIFFSLR |IO_L01N_1 |UNUSED | |1 | | | | | | | | |
|P58 | | |GND | | | | | | | | | | | |
|P59 | |DIFFMLR |IO_L02P_1/RHCLK0 |UNUSED | |1 | | | | | | | | |
|P60 | |DIFFSLR |IO_L02N_1/RHCLK1 |UNUSED | |1 | | | | | | | | |
|P61 | |DIFFMLR |IO_L03P_1/RHCLK2 |UNUSED | |1 | | | | | | | | |
|P62 | |DIFFSLR |IO_L03N_1/TRDY1/RHCLK3|UNUSED | |1 | | | | | | | | |
|P63 | | |GND | | | | | | | | | | | |
|P64 | |DIFFMLR |IO_L04P_1/IRDY1/RHCLK6|UNUSED | |1 | | | | | | | | |
|P65 | |DIFFSLR |IO_L04N_1/RHCLK7 |UNUSED | |1 | | | | | | | | |
|P66 | | |VCCINT | | | | | | | |1.2 | | | |
|P67 | | |VCCO_1 | | |1 | | | | |any******| | | |
|P68 | |DIFFMI_NDT|IP_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|P69 | | |GND | | | | | | | | | | | |
|P70 | |DIFFMLR |IO_L05P_1 |UNUSED | |1 | | | | | | | | |
|P71 | |DIFFSLR |IO_L05N_1 |UNUSED | |1 | | | | | | | | |
|P72 | |DIFFMLR |IO_L06P_1 |UNUSED | |1 | | | | | | | | |
|P73 | |DIFFSLR |IO_L06N_1 |UNUSED | |1 | | | | | | | | |
|P74 | | |GND | | | | | | | | | | | |
|P75 | | |TDO | | | | | | | | | | | |
|P76 | | |TCK | | | | | | | | | | | |
|P77 | |DIFFMTB |IO_L01P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|P78 | |DIFFSTB |IO_L01N_0 |UNUSED | |0 | | | | | | | | |
|P79 | | |VCCO_0 | | |0 | | | | |any******| | | |
|P80 | | |GND | | | | | | | | | | | |
|P81 | | |VCCINT | | | | | | | |1.2 | | | |
|P82 | |IBUF |IP_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|P83 | |DIFFMTB |IO_L02P_0/GCLK4 |UNUSED | |0 | | | | | | | | |
|P84 | |DIFFSTB |IO_L02N_0/GCLK5 |UNUSED | |0 | | | | | | | | |
|P85 | |DIFFMTB |IO_L03P_0/GCLK6 |UNUSED | |0 | | | | | | | | |
|P86 | |DIFFSTB |IO_L03N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
|P87 | | |GND | | | | | | | | | | | |
|P88 | |DIFFMTB |IO_L04P_0/GCLK8 |UNUSED | |0 | | | | | | | | |
|P89 | |DIFFSTB |IO_L04N_0/GCLK9 |UNUSED | |0 | | | | | | | | |
|P90 | |DIFFSTB |IO_0/GCLK11 |UNUSED | |0 | | | | | | | | |
|P91 | | |GND | | | | | | | | | | | |
|P92 | | |VCCAUX | | | | | | | |2.5 | | | |
|P93 | |DIFFMTB |IO_L05P_0 |UNUSED | |0 | | | | | | | | |
|P94 | |DIFFSTB |IO_L05N_0 |UNUSED | |0 | | | | | | | | |
|P95 | | |GND | | | | | | | | | | | |
|P96 | | |VCCO_0 | | |0 | | | | |any******| | | |
|P97 | |IBUF |IP_0 |UNUSED | |0 | | | | | | | | |
|P98 | |DIFFMTB |IO_L06P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|P99 | |DIFFSTB |IO_L06N_0/PUDC_B |UNUSED | |0 | | | | | | | | |
|P100 | | |PROG_B | | | | | | | | | | | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
 
 
/phr/trunk/codigo/demos/projects/demo1/top.cmd_log
0,0 → 1,5
xst -intstyle ise -ifn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.xst" -ofn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s200a-vq100-5 top.ngc top.ngd
map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf
par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
/phr/trunk/codigo/demos/projects/demo1/iseconfig/demo1.projectmgr
0,0 → 1,89
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="demo1" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>top - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000e5000000020000000000000000000000000000000064ffffffff000000810000000000000002000000e50000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>top - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001e8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000039f000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004f0000000100000000000000290000000100000000000000840000000100000000000002a30000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000124000000010001000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>I/O Pin Planning (PlanAhead) - Pre-Synthesis</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001e8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>I/O Pin Planning (PlanAhead) - Pre-Synthesis</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Edit Constraints (Text)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001e8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Edit Constraints (Text)</CurrentItem>
</ItemView>
<SourceProcessView>000000ff0000000000000002000001440000011d01000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
</Project>
/phr/trunk/codigo/demos/projects/demo1/iseconfig/top.xreport
0,0 → 1,217
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2014-04-30T19:55:22</DateModified>
<ModuleName>top</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/iseconfig/top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1</ImplementationReportsDirectory>
<DateInitialized>2014-04-30T19:55:22</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="top_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="top_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="top_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="top.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="top.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="top.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="top.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="top.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="top_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/top_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="top_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="top.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
/phr/trunk/codigo/demos/projects/demo1/.lso
0,0 → 1,217
work
/phr/trunk/codigo/demos/projects/demo1/top_map.map
0,0 → 1,58
Release 12.3 Map M.70d (lin)
Xilinx Map Application Log File for Design 'top'
 
Design Information
------------------
Command Line : map -intstyle ise -p xc3s200a-vq100-5 -cm area -ir off -pr off
-c 100 -o top_map.ncd top.ngd top.pcf
Target Device : xc3s200a
Target Package : vq100
Target Speed : -5
Mapper Version : spartan3a -- $Revision: 1.52 $
Mapped Date : Wed Apr 30 20:02:32 2014
 
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
 
Design Summary
--------------
 
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic: 0 out of 0 0%
Number of Slices containing unrelated logic: 0 out of 0 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Number of bonded IOBs: 16 out of 68 23%
 
Average Fanout of Non-Clock Nets: 1.00
 
Peak Memory Usage: 159 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 2 secs
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Mapping completed.
See MAP report file "top_map.mrp" for details.
/phr/trunk/codigo/demos/projects/demo1/demo1.xise
0,0 → 1,340
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s200a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="demo1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-30T19:53:45" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E14E4DF5D9E1A20DBB6BE9CAABEC8DB2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/phr/trunk/codigo/demos/projects/demo1/top.twr
0,0 → 1,66
--------------------------------------------------------------------------------
Release 12.3 Trace (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
/opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3
-fastpaths -xml top.twx top.ncd -o top.twr top.pcf
 
Design file: top.ncd
Physical constraint file: top.pcf
Device,package,speed: xc3s200a,vq100,-5 (PRODUCTION 1.41 2010-09-15)
Report level: verbose report
 
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
 
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
sw<0> |leds<0> | 4.987|
sw<1> |leds<1> | 5.256|
sw<2> |leds<2> | 4.987|
sw<3> |leds<3> | 4.991|
sw<4> |leds<4> | 4.980|
sw<5> |leds<5> | 4.993|
sw<6> |leds<6> | 4.980|
sw<7> |leds<7> | 4.987|
---------------+---------------+---------+
 
 
Analysis completed Wed Apr 30 20:02:58 2014
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 97 MB
 
 
 
/phr/trunk/codigo/demos/projects/demo1/top.syr
0,0 → 1,289
Release 12.3 - xst M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Reading design: top.prj
 
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "top.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
 
---- Target Parameters
Output File Name : "top"
Output Format : NGC
Target Device : xc3s200a-5-vq100
 
---- Source Options
Top Module Name : top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
 
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
 
=========================================================================
 
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd" in Library work.
Architecture behavioral of Entity top is up to date.
 
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>).
 
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <top> in library <work> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit <top>.
Related source file is "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd".
WARNING:Xst:647 - Input <clk_div_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_div_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_div_3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <push> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_50M> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <top> synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
 
=========================================================================
Advanced HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
 
Optimizing unit <top> ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Found no macro
=========================================================================
 
=========================================================================
* Partition Report *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : top.ngr
Top Level Output File Name : top
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
 
Design Statistics
# IOs : 24
 
Cell Usage :
# BELS : 8
# INV : 8
# IO Buffers : 16
# IBUF : 8
# OBUF : 8
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s200avq100-5
 
Number of Slices: 4 out of 1792 0%
Number of 4 input LUTs: 8 out of 3584 0%
Number of IOs: 24
Number of bonded IOBs: 16 out of 68 23%
 
---------------------------
Partition Resource Summary:
---------------------------
 
No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
No clock signals found in this design
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -5
 
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.496ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay: 6.496ns (Levels of Logic = 3)
Source: sw<7> (PAD)
Destination: leds<7> (PAD)
 
Data Path: sw<7> to leds<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.824 0.357 sw_7_IBUF (sw_7_IBUF)
INV:I->O 1 0.562 0.357 leds_7_not00001_INV_0 (leds_7_OBUF)
OBUF:I->O 4.396 leds_7_OBUF (leds<7>)
----------------------------------------
Total 6.496ns (5.782ns logic, 0.714ns route)
(89.0% logic, 11.0% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 3.74 secs
-->
 
 
Total memory usage is 147108 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 5 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/phr/trunk/codigo/demos/projects/demo1/top_summary.xml
0,0 → 1,10
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="1">
<CmdHistory>
</CmdHistory>
</DesignSummary>
/phr/trunk/codigo/demos/projects/demo1/top.xst
0,0 → 1,56
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn top.prj
-ifmt mixed
-ofn top
-ofmt NGC
-p xc3s200a-5-vq100
-top top
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-mult_style Auto
-iobuf YES
-max_fanout 500
-bufg 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
/phr/trunk/codigo/demos/projects/demo1/top_map.ngm
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$9`x4>713-Xnzd}foo8#5+439'8%8-*>1:&Qasotafd1,< :2!&g?6u589k}}<>?-432?1<NFY__6}{|h=194;`<03CE\XZ5sv>4>586:221CXZ_UU8oaau;?3:5?6LZF028FPOKLV^J^JK[ASAK<>DR[VCEJB74CNONMQRBL>1H^HO[EEg8@WEX[\IHI^]IUM32?@^WIGNNHRLLD^DJH@733LR[MCJJD^ALJVRUI@D__<?4EYRBJACCW@YNSKGCE59EVDAe3OXJKNAYESGGe>@UINUIM^KKa:DQEBYDG\D_=95HEOGQEQCC(YEXX HCIOV26>ABFLXJXHJ/PNQW)B5792C?7DLZF39JJ==NFOOY^HJ<;HLU<>OI^LX_IIk4IO]MCAYFFMUIOI84INALIU0<AF^R\H:4IQCG3>JNJ[KYU;5CO@FF@2=KGNCHMA;4M/53`2=J&>:oSAl4M@RF\UGILLN=7@O_PDFb?HGWWDEOYAKk;LCS[QOJMZ^JA]l4M@R\R@TTAFD:56CC_FGMAWGSMMU[C^Z"GSCMMQCd3DkacXjrrkljf=JageyZh||inl4?KCS_FX@46@@T^RK]V7<G=1DNXH;;NRB@6=H]]90\LJ;;QCQP==W@PYBOLBn;QKM[GSTAMRi7]GA_CWPJDKB?2XNABXJD028V@KH^LNTX_O\HBCM=>UNOVIDYCZ<;RLH7>UUKm1X^NQGIDPBVFN^n2^J^JK[_QCQPQ_WM11_I_CFN@N7?Q_WMj1^_H\PVHQJFIC>3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK<0TilPIeg8\anXKfxyNaalkr33?]boWJey~Ck{wnphw45<PmbTAl~LospNawabl]e:;6Vkh^ObtFiuz[ofc{kkTscplg=_laU[~dcFnwa8\anXX{cfXt~jf:ZglZVuad\n~~g`n69[`mYSinh0TicPBhlgmka682RoaRCnjnpUawungg;;7Ujb_LkmkwPbzzcdb>5Wsu58gimX=9G27nbd_eku[4?<keaThdxP289`hnYcaU8;6bjdr>3:2=kmmy7=394ldfp87803eoo1=17:nf`v:36>1gii}35?58h`bt4?427akks=594;1<dlnx0:0m;mggwZ6XGK_M=85ceeq\4Zhh|9:;<<QFNW]3f>jblzU:SBLZF078h`btW8Uecy>?013\MKPX8k1gii}P2^MAQC723eooR<Pnnv34566W@D]S=l4ldfp[6YHJ\L:96bjdr]0[kis89:;=RGAV^2a?icc{V>TCO[I149oaauX<Vddx=>?00]JJSY7j2fnh~Q:_N@VB43<dlnxS8Qaou23457XAG\T<o5ceeq\2ZIE]O;>7akks^4\jjr789::SD@Y_1`8h`btW>UDNXH>5:nf`vY0Wge<=>?1^KMRZ643dk{46`hdcwjha1<x|yc0=08;qwpl979?2z~e2=>89sqvn;;3:5;6~zsi>0:<=txhxmc=n5:qt85823z}7=3;4sv>1:0=t59596}x<5<6?vq;=7?0z29>69ps91=87?0z28>89psZ6XAK_M56}x_0]JFP@>3z}T>RGMUG;8wrY4W@H^J45|w^6\MGSA12y|S8QFBTD:?vqX>VCIYK74sv]4[LDRN:1c}64xhnjj}si911s`cvPatvl[5Ylk%hy wbbf~DEv6?h1KLu67:G84>4}Tj3?:6?:512165=c=;19?5v`;f;38j06=>2.?97:<;|Qb>07=:=0:?>;>8d80<62d3Z8:6:>51;30707?m393?8?4S`844?7=9:9>=5k539167>U593<m6?4>3272<`<40:?37^<9:7d966<6;:?:4h4<827b?Vg=>o096<=<50:f>6>4=h1o454?:081Vd==80987?<343;a?5?;=30(5486:J`?k4?2<9==5??8:&13?113-826?=4vU06>5<628094v]m:43961<6;:?:4h4<826:?!252;80Z9m52zw1f?7<};i1<6s+3580?!`=82.o65o4$d82g>d?03:1=54=8;0;M263->;6564Z8803<32<0vb9j50:k67?6=3`??6=44i4794?=n=;0;66a:e;29 61==m1e?;4?;:m6g?6=,:=19i5a3782?>i2j3:1(>955e9m73<532e>m7>5$2591a=i;?0876a:9;29 61==m1e?;4;;:m6<?6=,:=19i5a3786?>i2?3:1(>955e9m73<132e>:7>5$2591a=i;?0<76g85;29 61=?=1e?;4?;:k47?6=,:=1;95a3782?>o0:3:1(>95759m73<532c<=7>5$25931=i;?0876g8f;29 61=?l1e?;4?;:k4`?6=,:=1;h5a3782?>o0k3:1(>957d9m73<532c<n7>5$2593`=i;?0876g8a;29 61=?l1e?;4;;:k4=?6=,:=1;h5a3786?>o003:1(>957d9m73<132c<;7>5$2593`=i;?0<76l77;396?6=8r.?<7?8;I67?M263->i6:5G1e9'5`<602.9<766;o6g>4=#;m0346g>6;29 1d=9110c?h50;&7f?5532wi4;4>:383>5}#<90:;6F;4:J75>"3j3=0D<j4$0g95==#:90356`;d;08 6b=011b=;4?:%6a>4><3f8m6=4+4c806>=zj1?1=7<50;2x 16=9>1C895G409'0g<03A;o7)?j:0:8 76=001e8i4<;%1g>=><a8<1<7*;b;3;?>i5n3:1(9l53398yg>328096=4?{%63>41<@=>0D9?4$5`93>N6l2.:i7?7;%03>=?<f=n186*<d;:;?l71290/8o4>8:9l6c<72->i6><4;|`;7?7=:3:1<v*;0;34?M233A>:7):m:69K5a=#9l0:46*=0;::?k2c2<1/?i478:k22?6=,=h1=554o3d94?"3j39976sm8382>7<729q/8=4>7:J70>N392.?n794H0f8 4c=911/>=479:l7`?0<,:n1455f1783>!2e28207b<i:18'0g<4:21vn5?51;094?6|,=:1=:5G459K04=#<k0<7E?k;%3f>4><,;:1445a4e84?!5c2120e<850;&7f?7?32e9j7>5$5`977=<uk2;6<4=:183!2728=0D9:4H538 1d=?2B:h6*>e;3;?!472130b9j58:&0`?>?3`;=6=4+4c82<>=h:o0;6):m:208?xd1l3;1>7>50z&74?573A>?7E:>;%6a>2=O9m1/=h4<2:&14?>>3g>o645+3e8;<>o6>3:1(9l51998k7`=83.?n7==;:a2g<62;0;6=u+41804>N3<2B?=6*;b;58L4b<,8o1??5+218;=>h3l3k0(>j5899j53<72->i6<64;n0e>5<#<k08>65rb7;95?4=83:p(9>5319K01=O<81/8o48;I3g?!7b2:80(?>5889m0a<e3-9o6564i0494?"3j3;376a=f;29 1d=;;10qo88:081>5<7s->;6>>4H568L17<,=h1;6F>d:&2a?553-8;6574n5f9g>"4l3237d?9:18'0g<6021d>k4?:%6a>64<3th=97?52;294~"3839;7E:;;I62?!2e2>1C=i5+1d806>"583227c:k:e9'7a<?02c::7>5$5`95==<g;l1<7*;b;11?>{e>:0:6?4?:1y'05<482B?86F;1:&7f?1<@8n0(<k5339'65<?12d?h7k4$2f9<==n9?0;6):m:0:8?j4a290/8o4<2:9~f37=9381<7>t$52975=O<=1C8<5+4c84?M7c3-;n6><4$329<<=i<m0m7)=k:9:8m40=83.?n7?7;:m1b?6=,=h1??54}c7e>4<5290;w):?:228L12<@=;0(9l57:J2`>"6m3997)<?:9;8j1b=991/?i478:k22?6=,=h1=554o3d94?"3j39976sm6d82>7<729q/8=4>a:J70>N392.?n794$329<<=i<m0:=6*<d;:;?l71290/8o4>8:9l6c<72->i6><4H5c8?xd1k3;1>7>50z&74?7f3A>?7E:>;%6a>2=#:90356`;d;31?!5c2120e<850;&7f?7?32e9j7>5$5`977=O<h10qo8n:081>5<7s->;6<o4H568L17<,=h1;6*=0;::?k2c2890(>j5899j53<72->i6<64;n0e>5<#<k08>6F;a:9~f3>=9381<7>t$5295d=O<=1C8<5+4c84?!472130b9j5159'7a<?02c::7>5$5`95==<g;l1<7*;b;11?M2f32wi:;4>:383>5}#<90:m6F;4:J75>"3j3=0(?>5889m0a<6=2.8h767;h35>5<#<k0:465`2g83>!2e2:80D9o4;|`50?7=:3:1<v*;0;3b?M233A>:7):m:69'65<?12d?h7?9;%1g>=><a8<1<7*;b;3;?>i5n3:1(9l5339K0d=<uk<96<4=:183!2728k0D9:4H538 1d=?2.9<766;o6g>41<,:n1455f1783>!2e28207b<i:18'0g<4:2B?m65rb7295?4=83:p(9>51`9K01=O<81/8o48;%03>=?<f=n1=55+3e8;<>o6>3:1(9l51998k7`=83.?n7==;I6b?>{e=?0:6<4?:1y'0g<4;2B?=6F>9:&2a?553g>o6<74o2194?"3j39876sm5682>4<729q/8o4<3:J75>N612.:i7==;o6g>4g<g:91<7*;b;10?>{e=10:6<4?:1y'0g<4;2B?=6F>9:&2a?553g>o6<l4o2194?"3j39876sm5882>4<729q/8o4<3:J75>N612.:i7==;o6g>4e<g:91<7*;b;10?>{e=h0:6<4?:1y'0g<4;2B?=6F>9:&2a?553g>o6<j4o2194?"3j39876sm5c82>4<729q/8o4<3:J75>N612.:i7==;o6g>4c<g:91<7*;b;10?>{e=j0:6<4?:1y'0g<4;2B?=6F>9:&2a?553g>o6<h4o2194?"3j39876sm5d82>4<729q/8o4<3:J75>N612.:i7==;o6g>76<g:91<7*;b;10?>{e?>0:6<4?:1y'0g<4;2B?=6F>9:&2a?7?3g>o6??4i2194?"3j39876sm7982>4<729q/8o4<3:J75>N612.:i7?7;o6g>74<a:91<7*;b;10?>{e?00:6<4?:1y'0g<4;2B?=6F>9:&2a?7?3g>o6?=4i2194?"3j39876sm7`82>4<729q/8o4<3:J75>N612.:i7?7;o6g>72<a:91<7*;b;10?>{e?k0:6<4?:1y'0g<4;2B?=6F>9:&2a?7?3g>o6?;4i2194?"3j39876sm7b82>4<729q/8o4<3:J75>N612.:i7?7;o6g>70<a:91<7*;b;10?>{e?m0:6<4?:1y'0g<4;2B?=6F>9:&2a?7?3g>o6?94i2194?"3j39876sm7g82>4<729q/8o4<3:J75>N612.:i7?7;o6g>7><a:91<7*;b;10?>{t=?0;6>uQ579>1c<5n27>:7=<;|q63?6=;rT>;6391;0e?8302:90q~;7:180[3?34<86?h4=4:976=z{<31<7=t^4;8933=:o16944<3:p1d<72:qU9l526681b>;2i3987p}:b;297~X2j27=57<i;<7a>65<uz?h6=4<{_7`?80e2;l018m5329~w0c=839pR8k4=7f96c=:=l08?6s|5g83>7}:=o0::6390;0e?xu193:1>v391;35?8052;l0q~8<:18180428<01;:52g9~w33=838p1;;5179>23<5n2wx::4?:3y>22<6>27=47<i;|q5=?6=:r7=57?9;<4b>7`<uz<i6=4={<4a>40<5?i1>k5rs7f94?4|5?n1=;526d81b>{t?>0;6>uQ769><5<6>27<;7=<;|q4<?6=;rT<46371;35?81?2:90q~96:180[1>34296<84=6;976=z{>k1<7=t^6c89=5=9?16;l4<3:p3g<72:qU;o5285822>;0j3987p}8c;297~X0k27397?9;<5`>65<uz=o6=4<{_5g?8>128<01:j5329~w2`=839pR:h4=95953=:?o08?6s|8183>7}:0909j6390;35?xu?93:1>v371;0e?80528<0q~6=:1818>52;l01;:5179~w=5=838p15=52g9>23<6>2wx494?:3y><1<5n27=47?9;|q;1?6=:r7397<i;<4b>40<uz2=6=4={<:5>7`<5?i1=;5rs9594?4|51=1>k526d822>{t=:0;6<uQ529~w02=83;pR8:4}r76>5<6sW?>7p}:2;295~X2:2wx;84?:0y]30=z{>91<7?t^618yv15290:wS9=;|q45?6=9rT<=6srn9g94?7|@=;0E>=51z09yk2c291vb5h50;3xL17<A:91=v<5}o6g>4=zf0:1<7?tH538M65=9r81qc:k:39~j<7=83;pD9?4I2195~4=ug>o6>5rn8094?7|@=;0E>=51z09yk2c2=1vb4=50;3xL17<A:91=v<5}o6g>0=zf0>1<7?tH538M65=9r81qc:k:79~j<3=83;pD9?4I2195~4=ug>o6:5rn8495?7|@=;0b9j58:&7<?>73td2;7?51zJ75>h3l330(965809~j<>=93;pD9?4n5f9e>"303297p`69;395~N392d?h7l4$5:9<6=zf0k1=7?tH538j1b=k2.?476;;|l:f?7=9rB?=6`;d;f8 1>=0<1vb4m51;3xL17<f=n1i6*;8;:5?xh>l3;1=vF;1:l7`?`<,=214:5rn8g94?7|@=;0E>=51z39yk2c28:0qc7i:182M263@986<u>:|l7`?763tdj<7>51zJ75>O4;3;p=7sa4e826>{ii80;6<uG409J76<6s80vb9j5129~jd4=83;pD9?4I2195~7=ug>o6<:4}oc0>5<6sA>:7D=<:0y2>xh3l3;>7p`n4;295~N392C8?7?t1;m0a<6>2wem84?:0yK04=N;:0:w<4rn5f952=zfh<1=7?tH538j1b=911vbl951;3xL17<f=n1=45rn`:95?7|@=;0b9j51`9~jd?=93;pD9?4n5f95g=zfhk1=7?tH538j1b=9j1vbll51;3xL17<f=n1=i5rn`a95?7|@=;0b9j51d9~jdb=93;pD9?4n5f95c=zfho1<7?tn5f965=zfhl1<7?tn5f964=zfk:1<7?tn5f967=zfk;1<7?tn5f966=zfk81<7?tn5f961=zfk91<7?tn5f960=zfk>1<7?tn5f963=zfk?1<7?tn5f962=zu^:=7>51;395=}Tj3<m6?4>3272<`<40:?j7):=:278 62=;2B:86F=a:J21>d?03:1=54=1;3;_?=;r<187;5}I31?!5b2:1e=>4=0:l0e?7?3g>o6=5f5283>>o2<3:17d;::188m04=831d9h4?:%14>0b<f:<1<65`5b83>!502<n0b>851:9l1g<72-9<68j4n2496>=h=h0;6)=8:4f8j60=;21d944?:%14>0b<f:<1865`5983>!502<n0b>855:9l12<72-9<68j4n2492>=h=?0;6)=8:4f8j60=?21b;84?:%14>22<f:<1<65f7283>!502>>0b>851:9j37<72-9<6::4n2496>=n?80;6)=8:668j60=;21b;k4?:%14>2c<f:<1<65f7e83>!502>o0b>851:9j3f<72-9<6:k4n2496>=n?k0;6)=8:6g8j60=;21b;l4?:%14>2c<f:<1865f7883>!502>o0b>855:9j3=<72-9<6:k4n2492>=n?>0;6)=8:6g8j60=?21i4:4>:383>5}#<90:;6*<d;:;?!7b2820D<>4n5f95>o6>3:17b<i:188yg>128096=4?{%63>41<,:n1455+1d82<>N682d?h7<4i0494?=h:o0;66sm8482>7<729q/8=4>7:&0`?>?3-;n6<64H028j1b=;2c::7>5;n0e>5<<uk2?6<4=:183!2728=0(>j5899'5`<602B:<6`;d;68m40=831d>k4?::a<6<62;0;6=u+41823>"4l3237)?j:0:8L46<f=n196g>6;29?j4a2900qo6=:081>5<7s->;6<94$2f9<==#9l0:46F>0:l7`?0<a8<1<75`2g83>>{e080:6?4?:1y'05<6?2.8h767;%3f>4><@8:0b9j57:k22?6=3f8m6=44}c:3>4<5290;w):?:058 6b=011/=h4>8:J24>h3l320e<850;9l6c<722wi:i4>:383>5}#<908<6*<d;:;?!7b2:80D<>4n5f9=>o6>3:1D<l4;n0e>5<<uk<i6<4=:183!272::0(>j5899'5`<4:2B:<6`;d;c8m40=83B:n65`2g83>>{e>00:6?4?:1y'05<482.8h767;%3f>64<@8:0b9j5b:k22?6=@8h07b<i:188yg0028096=4?{%63>66<,:n1455+1d806>N682d?h7m4i0494?N6j21d>k4?::a20<62;0;6=u+41804>"4l3237)?j:208L46<f=n1h6g>6;29L4d<3f8m6=44}c40>4<5290;w):?:228 6b=011/=h4<2:J24>h3l3o0e<850;J2f>=h:o0;66sm6082>7<729q/8=4<0:&0`?>?3-;n6><4H028j1b=n2c::7>5H0`8?j4a2900qo;i:081>5<7s->;6>>4$2f9<==#9l08>6F>0:l7`?773`;=6=4G1c98k7`=831vn8851;394?6|,=:1?<5+1d806>N682d?h7?>;h1a>5<<uk?<6<4>:183!272:;0(<k5339K55=i<m0:>6g<b;29?xd203;1=7>50z&74?563-;n6><4H028j1b=9:1b?o4?::a1<<6280;6=u+41805>"6m3997E??;o6g>42<a:h1<75rb4c95?7=83:p(9>5309'5`<4:2B:<6`;d;36?l5e2900qo;m:082>5<7s->;6>?4$0g977=O991e8i4>6:k0f?6=3th>o7?51;294~"3839:7)?j:208L46<f=n1=:5f3c83>>{e=l0:6<4?:1y'05<492.:i7==;I33?k2c2820e>l50;9~f21=93;1<7>t$5295c=#9l0:46F>0:l7`?7>3f9h6=44}c5;>4<6290;w):?:0d8 4c=911C==5a4e82e>i4k3:17pl89;395?6=8r.?<7?i;%3f>4><@8:0b9j51c9l7f<722wi;l4>:083>5}#<90:j6*>e;3;?M773g>o6<m4o2a94?=zj>h1=7?50;2x 16=9o1/=h4>8:J24>h3l3;o7b=l:188yg1d280:6=4?{%63>4`<,8o1=55G119m0a<6m2e8o7>5;|`4`?7=93:1<v*;0;3e?!7b2820D<>4n5f95c=h;j0;66sm7g82>4<729q/8=4>f:&2a?7?3A;;7c:k:328k6e=831vn>751;294?6|@=30(9>5399K7c=O:l1e8i4=1:p3c<72:q64:4>6:?4b?5d3W=m7p}77;296~;??38m708k:048yv1c2908w069:04892b=;j1U;i5rs9494?4|51<1>k526c822>{t?j0;6>u284822>;0k39h7S9l;|q;1?6=:r7397<i;<4:>40<uz=i6=4<{<:7>40<5>h1?n5Q7c9~w=2=838p15:52g9>22<6>2wx;l4?:2y><6<6>27<m7=l;_5b?xu?;3:1>v373;0e?80228<0q~96:1808>528<01:753b9]3<=z{181<7<t=9096c=:>:0::6s|7983>6}:080::6388;1`?[1?3ty3=7>52z?;5?4a34<:6<84}r54>5<4s42;6<84=6597f=Y?>1v5>50;0x9=6=:o169k4>6:p1`<72:q6:i4=f:?6a?5e3W?n7p}:c;297~;1j38m70;l:2`8Z0e<uz?i6=4<{<4:>7`<5<h1?o5Q5c9~w0g=839p1;952g9>1d<4j2T>m6s|5883>6}:><09j63:9;1a?[3>3ty>47>53z?57?4a34?36>l4^4:8yv302908w08>:3d8901=;k1U9:5rs4494?5|5<l1>k525780f>X2>2wvb<:n:182k2c291vb<:m:182k2c281vb<:l:182k2c2;1vb<:k:182k2c2:1vb<:j:182k2c2=1vb<:i:182k2c2<1vb<;?:182k2c2?1vb<;>:182k2c2>1vb<;=:182k2c211vb<;<:182k2c201vb<;;:182k2c2h1vb<;::182k2c2k1vb<;9:182k2c2j1vb<;8:182k2c2m1vb<;7:182k2c2l1vb<;6:182k2c2o1vb<;n:182k2c28:0qc?:b;295~h3l3;:7p`>5b83>4}i<m0:>6sa14f94?7|f=n1=>5rn07f>5<6sg>o6<:4}o36b?6=9rd?h7?:;|l225<728qe8i4>6:m537=83;pb9j5169~yx{GHJq:;l4:60`ea06zHIHp>4u;7;294?4=l<0h96st4683>5<52m>1o95r{5594?6=:3n86n=4}z64>5<72;0o>7m=;|y73?6=8381h<4l1:x02<729096i>5c19~11=83:1>7mi:cd8y~20290;6?4le;`f?x}3>3:1<7<5f8812>{|<?0;6=4=:ga96<=zs=<1<7>52;de>7e<ur>=6=4?:38247<5n2wp8;4?:181>4622:80qv:9:183>7<6810896st4783>5<528:i6>64}z65>5<72;0:<h4<b:x03<729096<?>:2g8y~21290;6?4>15875>{|<?0;6=4=:034>12<ur>=6=4?:3825d<3?2wp8;4?:181>47c2=k0qv:9:183>7<6:90?h6st4783>5<5288868>4}z65>5<72;0:>;4:3:x03<729096<<6:7g8y~21290;6?4>2c844>{|<?0;6=4=:00g>24<ur>=6=4?:3826c<0<2wp8;4?:181>4562><0qv:9:183>7<6;:0<46st4783>5<5289>6:o4}z65>5<72;0:?:48c:x03<729096<=6:6g8y~21290;6?4>3c8;4>{|<?0;6=4=:01g>=4<ur>=6=4?:3827c<?<2wp8;4?:181>42621<0qv:9:183>7<6<:0346st4783>5<528>>65o4}z65>5<72;0:8:47c:x03<729026<:6:4491<<2k3?m6;<56485<?0e3twKL]ur@A
/phr/trunk/codigo/demos/projects/demo1/top_pad.csv
0,0 → 1,131
#Release 12.3 - par M.70d (lin)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
#Wed Apr 30 20:02:53 2014
 
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: top_map.ncd
#OUTPUT FILE: top_pad.csv
#PART TYPE: xc3s200a
#SPEED GRADE: -5
#PACKAGE: vq100
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
P1,,,TMS,,,,,,,,,,,,
P2,,,TDI,,,,,,,,,,,,
P3,,DIFFMLR,IO_L01P_3,UNUSED,,3,,,,,,,,,
P4,,DIFFSLR,IO_L01N_3,UNUSED,,3,,,,,,,,,
P5,,DIFFMLR,IO_L02P_3,UNUSED,,3,,,,,,,,,
P6,,DIFFSLR,IO_L02N_3,UNUSED,,3,,,,,,,,,
P7,,DIFFSI_NDT,IP_3/VREF_3,UNUSED,,3,,,,,,,,,
P8,,,GND,,,,,,,,,,,,
P9,,DIFFMLR,IO_L03P_3/LHCLK0,UNUSED,,3,,,,,,,,,
P10,,DIFFSLR,IO_L03N_3/LHCLK1,UNUSED,,3,,,,,,,,,
P11,,,VCCO_3,,,3,,,,,any******,,,,
P12,,DIFFMLR,IO_L04P_3/LHCLK2,UNUSED,,3,,,,,,,,,
P13,,DIFFSLR,IO_L04N_3/IRDY2/LHCLK3,UNUSED,,3,,,,,,,,,
P14,,,GND,,,,,,,,,,,,
P15,,DIFFMLR,IO_L05P_3/TRDY2/LHCLK6,UNUSED,,3,,,,,,,,,
P16,,DIFFSLR,IO_L05N_3/LHCLK7,UNUSED,,3,,,,,,,,,
P17,,,VCCINT,,,,,,,,1.2,,,,
P18,,,GND,,,,,,,,,,,,
P19,,DIFFMLR,IO_L06P_3,UNUSED,,3,,,,,,,,,
P20,,DIFFSLR,IO_L06N_3,UNUSED,,3,,,,,,,,,
P21,,DIFFMI_NDT,IP_3,UNUSED,,3,,,,,,,,,
P22,,,VCCAUX,,,,,,,,2.5,,,,
P23,sw<7>,IBUF,IO_L01P_2/M1,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P24,,DIFFMTB,IO_L02P_2/M2,UNUSED,,2,,,,,,,,,
P25,leds<7>,IOB,IO_L01N_2/M0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P26,,,VCCO_2,,,2,,,,,2.50,,,,
P27,leds<5>,IOB,IO_L02N_2/CSO_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P28,sw<5>,IBUF,IO_L03P_2/RDWR_B,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P29,sw<1>,IBUF,IO_L03N_2/VS2,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P30,,DIFFMTB,IO_L04P_2/VS1,UNUSED,,2,,,,,,,,,
P31,leds<1>,IOB,IO_L04N_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P32,sw<3>,IBUF,IO_L05P_2,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P33,leds<3>,IOB,IO_L05N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P34,sw<2>,IBUF,IO_L06P_2/D7,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P35,leds<2>,IOB,IO_L06N_2/D6,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P36,leds<6>,IOB,IO_L07P_2/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P37,sw<6>,IBUF,IO_L07N_2/D4,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P38,,,VCCINT,,,,,,,,1.2,,,,
P39,,IBUF,IP_2/VREF_2,UNUSED,,2,,,,,,,,,
P40,leds<4>,IOB,IO_L08P_2/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P41,sw<4>,IBUF,IO_L08N_2/GCLK15,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P42,,,GND,,,,,,,,,,,,
P43,sw<0>,IBUF,IO_L09P_2/GCLK0,INPUT,LVCMOS25*,2,,,,IBUF,,UNLOCATED,NO,NONE,
P44,leds<0>,IOB,IO_L09N_2/GCLK1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P45,,,VCCO_2,,,2,,,,,2.50,,,,
P46,,DIFFSTB,IO_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,,
P47,,,GND,,,,,,,,,,,,
P48,,DIFFMTB,IO_L10P_2/INIT_B,UNUSED,,2,,,,,,,,,
P49,,DIFFSTB,IO_L10N_2/D3,UNUSED,,2,,,,,,,,,
P50,,DIFFMTB,IO_L11P_2/D2,UNUSED,,2,,,,,,,,,
P51,,DIFFMTB,IO_L12P_2/D0/DIN/MISO,UNUSED,,2,,,,,,,,,
P52,,DIFFSTB,IO_L11N_2/D1,UNUSED,,2,,,,,,,,,
P53,,DIFFSTB,IO_L12N_2/CCLK,UNUSED,,2,,,,,,,,,
P54,,,DONE,,,,,,,,,,,,
P55,,,VCCAUX,,,,,,,,2.5,,,,
P56,,DIFFMLR,IO_L01P_1,UNUSED,,1,,,,,,,,,
P57,,DIFFSLR,IO_L01N_1,UNUSED,,1,,,,,,,,,
P58,,,GND,,,,,,,,,,,,
P59,,DIFFMLR,IO_L02P_1/RHCLK0,UNUSED,,1,,,,,,,,,
P60,,DIFFSLR,IO_L02N_1/RHCLK1,UNUSED,,1,,,,,,,,,
P61,,DIFFMLR,IO_L03P_1/RHCLK2,UNUSED,,1,,,,,,,,,
P62,,DIFFSLR,IO_L03N_1/TRDY1/RHCLK3,UNUSED,,1,,,,,,,,,
P63,,,GND,,,,,,,,,,,,
P64,,DIFFMLR,IO_L04P_1/IRDY1/RHCLK6,UNUSED,,1,,,,,,,,,
P65,,DIFFSLR,IO_L04N_1/RHCLK7,UNUSED,,1,,,,,,,,,
P66,,,VCCINT,,,,,,,,1.2,,,,
P67,,,VCCO_1,,,1,,,,,any******,,,,
P68,,DIFFMI_NDT,IP_1/VREF_1,UNUSED,,1,,,,,,,,,
P69,,,GND,,,,,,,,,,,,
P70,,DIFFMLR,IO_L05P_1,UNUSED,,1,,,,,,,,,
P71,,DIFFSLR,IO_L05N_1,UNUSED,,1,,,,,,,,,
P72,,DIFFMLR,IO_L06P_1,UNUSED,,1,,,,,,,,,
P73,,DIFFSLR,IO_L06N_1,UNUSED,,1,,,,,,,,,
P74,,,GND,,,,,,,,,,,,
P75,,,TDO,,,,,,,,,,,,
P76,,,TCK,,,,,,,,,,,,
P77,,DIFFMTB,IO_L01P_0/VREF_0,UNUSED,,0,,,,,,,,,
P78,,DIFFSTB,IO_L01N_0,UNUSED,,0,,,,,,,,,
P79,,,VCCO_0,,,0,,,,,any******,,,,
P80,,,GND,,,,,,,,,,,,
P81,,,VCCINT,,,,,,,,1.2,,,,
P82,,IBUF,IP_0/VREF_0,UNUSED,,0,,,,,,,,,
P83,,DIFFMTB,IO_L02P_0/GCLK4,UNUSED,,0,,,,,,,,,
P84,,DIFFSTB,IO_L02N_0/GCLK5,UNUSED,,0,,,,,,,,,
P85,,DIFFMTB,IO_L03P_0/GCLK6,UNUSED,,0,,,,,,,,,
P86,,DIFFSTB,IO_L03N_0/GCLK7,UNUSED,,0,,,,,,,,,
P87,,,GND,,,,,,,,,,,,
P88,,DIFFMTB,IO_L04P_0/GCLK8,UNUSED,,0,,,,,,,,,
P89,,DIFFSTB,IO_L04N_0/GCLK9,UNUSED,,0,,,,,,,,,
P90,,DIFFSTB,IO_0/GCLK11,UNUSED,,0,,,,,,,,,
P91,,,GND,,,,,,,,,,,,
P92,,,VCCAUX,,,,,,,,2.5,,,,
P93,,DIFFMTB,IO_L05P_0,UNUSED,,0,,,,,,,,,
P94,,DIFFSTB,IO_L05N_0,UNUSED,,0,,,,,,,,,
P95,,,GND,,,,,,,,,,,,
P96,,,VCCO_0,,,0,,,,,any******,,,,
P97,,IBUF,IP_0,UNUSED,,0,,,,,,,,,
P98,,DIFFMTB,IO_L06P_0/VREF_0,UNUSED,,0,,,,,,,,,
P99,,DIFFSTB,IO_L06N_0/PUDC_B,UNUSED,,0,,,,,,,,,
P100,,,PROG_B,,,,,,,,,,,,
 
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
/phr/trunk/codigo/demos/projects/demo1/top.vhd
0,0 → 1,54
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:55:21 04/30/2014
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity top is
Port ( clk_50M : in STD_LOGIC;
clk_div_1 : in STD_LOGIC;
clk_div_2 : in STD_LOGIC;
clk_div_3 : in STD_LOGIC;
push : in STD_LOGIC_VECTOR (3 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0);
leds : out STD_LOGIC_VECTOR (7 downto 0));
end top;
 
architecture Behavioral of top is
 
begin
 
sw2leds:
for ii in 0 to 7 generate
begin
leds(ii) <= not sw(ii);
end generate;
 
end Behavioral;
 
 
/phr/trunk/codigo/demos/projects/demo1/top_guide.ncd
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###3792:XlxV32DM 24ec eb8eNqlWNly2zgW/RU96G3KaWIjQKKTiizRCSfaIsmO0w/D4tqtmcR24nS6u2T/+1xs3ETZqYpdJu49F7g4OMRGj9PsgDw53pTf9/f725twhF7Q0RjLMwZ/OYG/z4E82998u//2z6fSR4092t+Xo7O70d85uceel559/4I874yNoMko/Vqmo7P919FtVUElW+YjqDE6ux19u71LPqd3L27yQtkvbn435V1ejaDP/Vd43H6Cx91XoPGNZPLsr1Gv59tPoz/2v/8xOvs2QscJ8yYhl7+sJzPEiDOoM5gzfGv4njOQM1wd39Xhrg53dbjLzIUzAmsIV1m4OoISCSoQSV4g9cAISRrGy/XlLrz78/6PX0novaqksND9X79yABAGZHW5U9Cnsrg3oCfPL+P5LNlNNm8ieEzfCkC2Sby8WOXyvPx0P/JeEJBngYR2w/j88iKZRfPJx2Qy+3dyfr66rlqReAnPogUAYxdfnSdAAMC8AdSAPDmdzJKrOPqQXEWbbbxaBnK6Wizi3S6acTndRBMwCjm9/Xxn+ODRIjWu7iRw9uocyRhEUeAvXZKpATU/YWzo21iKFpbxUrVcPmwvt+toOQvJdgf9PjxAy9X5L4Y51zY09OV8NZlFMyYXL7hXQMvFZJ1MF7N5vIyS1XoHo9imGlysZpfzqND2Ll5EkHaxzrRrhwuN0zsul9Huw2rzDssVpIP+fLmeTN9FMyKVSuq56feAmFzPtsn5fDV9l7xZzpLzeDmLl29QMIwnm+hCZapj6/lkGi2i5a5qgZfbyZuok/pqOh1M3cJ16n4b1fXizQZlGp+tlrvEvM7kcnm5jWbJOl5uTdcw+mQDo4ZUeQ3sPq6j1HhvZkk8M1XXs4WTzvYIaZLoegevDXKqRsjk0JOqPf6raKqJoiasMm8/LqftJu1xuSasFTadJ2rBWDk7+OYCSAMlWErx7Dpz9nKyiBCV63ewgLbxmyV0vUi2q8vNNKoUCm49QXy5jeawnEq5qxVVA6u0b9vrkdI+Au8v2sB6N/BVPI0SNZHgnVZdbLMrOsAClmLLh2UQzSykRhAv1vN4Gu9Mll3rJZi+tASawDw+36JCXscwV6/PrmfnsGrRaLu7NMZkO41jX14XWRIX0MF18TlZpP+9/XpVflVniIP2NzVEpToQuMw//S9h3iLQRrH/nqDGxI0Je2X+ufi0vympVHs8kbDjc6k3Pu+VNZAzsDOIM6gzmDP8V4Gs902L8VeZNhIvWcHmYB3UdnDbIW2Hth3Wdvy2w7VDJBx/RN6lX7nUe7zioA3kDAwE6+3fYgSwe2j0Lb0hKZNwFKiTQRcv6u1R48jgqI9jg+M+TgxO+jg1OO3jzOCsj/sG91s4l/bI0hW4qcBbFWBMf4HkZucHEzUmbkzSmLQxWWP6jcm1SSQc+JmsbwK/f2ZSX0mEdFcUyuRDc65MdrsNHC3hRXwdzdon49VkfhmFs/lHL4wvZkfgwwOuIM8mvopcCoTh9HLO/Gq6WG0xC7fz6AM8Vh8eHmD7eTiu8fDw+Pr1HcJUvn79d0rDi9AP0WGLs5CUIQlCRAhDAkxBWHa48UWI5I0fhL4c+zz0ffm4xelA3VxuiQgFDb027BOpqh/BYhjOh+FCFqnGTjOVY1aErJRjjEKRyhuSh4z4SCB4FWOSKWxMCmgGFYMQZvb3HcUmZYi901l9GsIu/55BcXh8z7AqxgzaFdBVoGJjX/c49r0Qdpsxq8JUaYWVbix1LFL5D/OhCwEl0+WcpKF/GPtVyCBVCAfemIQ+JKIhR5AgFESOhXo+vmVE/uazEB9wHmISPr6luZxTGhLdHtrwkHvyBvjIx8xIBe9NPQ9faCq/UF++pZn8DWNoggEvQ1SFj3s/h6py7xemKE2RqeKWp1CMmQh5AAOB1SXfwtv8kym9JIRFN4x6Yd4N417Y74ZJL8y6YdoL026Y9cKkG/Z7YdwN8054LwIbFsKOGzDexZDC/C6GFca6GAEscDoGQzruA94No16YdcO4FybdMOmFUTdMe0OtumHWCxfdsN8LZ91wV8dMy4zV72HMYNrC2qQ8zOSeemp+/Ysq6lAt09UAO6g48eUNrUL1fUhFSGBpqLZc7gnVs5KqEcEk52bx1s24aYZ0szQwzYTr5fFe1yeHl9AdRfIluPBN9B/4e7wP1CLAOkQoYJ58hPxkiD1sqX36+RD96jn2ZJA9PsmeWPa5YU9a7AvLPm+zp4Ps0RH7Yoh9+Rx7OsienGRPLfvCsKct9qVlX7TZs0H25Ih9OcS+eI49G2RPT7Jnln1p2LMW+8qyL9vs/SH25RH5aoh8/hx5f5A8O0net+QrQ95vyKeeJV+1yfNB6UWfvfCG2GfPseeD7P2T7LlhD71p9rzFHhn2EGqxF4PsvSP2aIh9+hx7Mcien2QvLHtk2IsWe2zZozb7dJB9cMQeD7EPnmOfDrIXJ9mnlj027NMWe2LZ4xZ7YfZxou4kKlWh2efyFlcd8r390jP7pfkxG08qDBkqb4lutGeZGUPQa4x0Y1udHQ1ZU2oNGZshG6XS1DTzmyHr+jDkQG+lL8E9OiOAPtwKVQ0QBVo0MIGqcEdXShRDSsAs70tR/owUxZAU/KQUxaAU6UkpCitFYaQojg8coK+lKKwUZQ23pKgGpcB9KQLvZ6Qoh6TwT0pRDUqRnZSislKURorq+PQC+lqK0kgReDXcSBGgQSnokRT4Z6SohqRgp6TQnI6lyE9JoesrKfSR8RLco6MQ6GspKisFruGWFGRIiuJICfoTSqTekBL0pBJkUInipBL2QpZ6RglyfK4CfaVE6lklaA23lGCDk4IfSeH/jBRoSApyUgo2KEV5Ugp7P0qRkYIdH9JAX0uBrBR+Dbek4ENSVEdKiJ9RAg8pgU8qwQeVqE4qYa8rKTZK8OMDH+hrJbBVQtRwS4l0cFKkR1JkPyMFGZICnZQiHZICeyelsLcH6EZLMXB7APpaCmKlyGq4lsJcQvDhPzx1NxB7rVKYcHcqe1FUGHe3RHv1VZjv7r32Lq8w5i7y9utEYdR9mtjvLYUR97FlvyAVht3nox0mYEHqxmhngcK4mwJ2jSiMuQVitxCFEbd/2A1WYcjtrvb8AUxU7vCxx7PCCnc229uLwjJ3dWl92gJfT8NK1+abkRi4sLD7GKMGrizsvnKYhoGXhuvvB9/AxMJ2zavX4OnRGtguAPXGPC2Mge1kUC/X0xrqF39TGmHtvwL+pCWsUkCzBkUNmjcobtCiQUmDlg1KG7RqUFajldegfoOiBuUNimu0oVuRGmx4VbQGGwIVq8FWT34NigbkNZg2oKjBvAGDGiwb0KzLzkZhYpcUrnr4QAhJc+GVHvwQD1NVBQdP+/A9xZVfEIyGfJcPCcyUD++3yp7iQYEHJWkghKdC3DPtqoBXT/lBwYUqC8/0e+QLEWg+/JQfZKps88x/QK/MyzURpwdCT/upV+hxOX36vsvX5lH8AA8k0qDdDw9S8ZSPRKbzC9vvsW/ytXmUP6RHVbTfC0JP+x6t9HiLAHtDvstXCEwcj+oHeLj548br5sspX3h+aftFQz4SnPT0QJ73Q4KUuCvA075Hi7wrSNd3+VqCIA/9kCI+6yrg06d8IawCdkb0fZevpYj+tzgyPOptR19+DVjUoD4SDJjVYObVYNCAZQ02W26e12CzZxdpDbY2fVGD9akBP69fTw8I4zDNfVFQzgE4P+ADDcxVR36hmXw8UNZ2oc768B42L0++h/6R/II85XxByHiQr1IFgQIq/x8j9yUD
/phr/trunk/codigo/demos/projects/demo1/_ngo/netlist.lst
0,0 → 1,2
/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.ngc 1398898940
OK
/phr/trunk/codigo/demos/projects/demo1/top.twx
0,0 → 1,338
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.3 Trace (lin)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3
-fastpaths -xml top.twx top.ncd -o top.twr top.pcf
 
</twCmdLine><twDesign>top.ncd</twDesign><twDesignPath>top.ncd</twDesignPath><twPCF>top.pcf</twPCF><twPcfPath>top.pcf</twPcfPath><twDevInfo arch="spartan3a" pkg="vq100"><twDevName>xc3s200a</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.41 2010-09-15</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="5">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="6">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="7" twNameLen="15"><twPad2PadList anchorID="8" twSrcWidth="5" twDestWidth="7"><twPad2Pad><twSrc>sw&lt;0&gt;</twSrc><twDest>leds&lt;0&gt;</twDest><twDel>4.987</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;1&gt;</twSrc><twDest>leds&lt;1&gt;</twDest><twDel>5.256</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;2&gt;</twSrc><twDest>leds&lt;2&gt;</twDest><twDel>4.987</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;3&gt;</twSrc><twDest>leds&lt;3&gt;</twDest><twDel>4.991</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;4&gt;</twSrc><twDest>leds&lt;4&gt;</twDest><twDel>4.980</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;5&gt;</twSrc><twDest>leds&lt;5&gt;</twDest><twDel>4.993</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;6&gt;</twSrc><twDest>leds&lt;6&gt;</twDest><twDel>4.980</twDel></twPad2Pad><twPad2Pad><twSrc>sw&lt;7&gt;</twSrc><twDest>leds&lt;7&gt;</twDest><twDel>4.987</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Apr 30 20:02:58 2014 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
 
Peak Memory Usage: 97 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
/phr/trunk/codigo/demos/projects/demo1/webtalk_pn.xml
0,0 → 1,40
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Apr 30 20:02:08 2014">
<section name="Project Information" visible="false">
<property name="ProjectID" value="E14E4DF5D9E1A20DBB6BE9CAABEC8DB2" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/demo1.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2014-04-30T19:53:45" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2014-04-30T19:53:45" type="design"/>
<property name="PROP_intWbtProjectID" value="E14E4DF5D9E1A20DBB6BE9CAABEC8DB2" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan3A and Spartan3AN" type="design"/>
<property name="PROP_DevDevice" value="xc3s200a" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3a" type="design"/>
<property name="PROP_DevPackage" value="vq100" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-5" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_VHDL" value="1" type="source"/>
</section>
</application>
</document>
/phr/trunk/codigo/demos/projects/demo1/top_usage.xml
0,0 → 1,21
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="1">
<DesignStatistics TimeStamp="Wed Apr 30 20:02:37 2014"><group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="1">
<attrib name="value" value="16"/></item>
<item name="AGG_IO" rev="1">
<attrib name="value" value="16"/></item>
<item name="NUM_BONDED_IBUF" rev="1">
<attrib name="value" value="8"/></item>
<item name="NUM_BONDED_IOB" rev="1">
<attrib name="value" value="8"/></item>
</group>
</DesignStatistics>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>
/phr/trunk/codigo/demos/projects/demo1/top.unroutes
0,0 → 1,9
Release 12.3 - par M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
 
Wed Apr 30 20:02:53 2014
 
All signals are completely routed.
 
 
 
/phr/trunk/codigo/demos/projects/demo1/demo1.gise
0,0 → 1,179
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<!-- -->
 
<!-- For tool use only. Do not edit. -->
 
<!-- -->
 
<!-- ProjectNavigator created generated project file. -->
 
<!-- For use in tracking generated file and other information -->
 
<!-- allowing preservation of process status. -->
 
<!-- -->
 
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
 
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="demo1.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6996891260173206920" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3211385631964956724" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1907144562815916640" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8569866560980815065" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898927" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1965690105638978622" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1398898941" xil_pn:in_ck="154288921315" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-3073005103026406395" xil_pn:start_ts="1398898927">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
<outfile xil_pn:name="top.ngc"/>
<outfile xil_pn:name="top.ngr"/>
<outfile xil_pn:name="top.prj"/>
<outfile xil_pn:name="top.stx"/>
<outfile xil_pn:name="top.syr"/>
<outfile xil_pn:name="top.xst"/>
<outfile xil_pn:name="top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1398898941" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1398898941">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
</transform>
<transform xil_pn:end_ts="1398898947" xil_pn:in_ck="154288912569" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5619283267425655681" xil_pn:start_ts="1398898941">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top.bld"/>
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1398898958" xil_pn:in_ck="154288912570" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5662573859661895013" xil_pn:start_ts="1398898947">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top.pcf"/>
<outfile xil_pn:name="top_map.map"/>
<outfile xil_pn:name="top_map.mrp"/>
<outfile xil_pn:name="top_map.ncd"/>
<outfile xil_pn:name="top_map.ngm"/>
<outfile xil_pn:name="top_map.xrpt"/>
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1398898979" xil_pn:in_ck="182976548277359827" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="7122883464624052383" xil_pn:start_ts="1398898958">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top.ncd"/>
<outfile xil_pn:name="top.pad"/>
<outfile xil_pn:name="top.par"/>
<outfile xil_pn:name="top.ptwx"/>
<outfile xil_pn:name="top.unroutes"/>
<outfile xil_pn:name="top.xpi"/>
<outfile xil_pn:name="top_pad.csv"/>
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1398898979" xil_pn:in_ck="154288912438" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1398898974">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/>
</transform>
</transforms>
 
</generated_project>
/phr/trunk/codigo/demos/projects/demo1/top.prj
0,0 → 1,179
vhdl work "top.vhd"
/phr/trunk/codigo/demos/projects/demo1/xlnx_auto_0_xdb/cst.xbcd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/phr/trunk/codigo/demos/projects/demo1/xlnx_auto_0_xdb/cst.xbcd
phr/trunk/codigo/demos/projects/demo1/xlnx_auto_0_xdb/cst.xbcd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/demo1/top_par.xrpt =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top_par.xrpt (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top_par.xrpt (revision 260) @@ -0,0 +1,830 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+ +
+ + + + +
+ + +
+ + +
+ + + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + +
+
+
+ + + +
+ + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/par.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/par.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/par.xmsgs (revision 260) @@ -0,0 +1,12 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/ngdbuild.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/ngdbuild.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/ngdbuild.xmsgs (revision 260) @@ -0,0 +1,9 @@ + + + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/pn_parser.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/pn_parser.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/pn_parser.xmsgs (revision 260) @@ -0,0 +1,12 @@ + + + + + + + + + + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/trce.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/trce.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/trce.xmsgs (revision 260) @@ -0,0 +1,19 @@ + + + +No timing constraints found, doing default enumeration. + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + +This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. + +This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/map.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/map.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/map.xmsgs (revision 260) @@ -0,0 +1,27 @@ + + + +Logical network clk_div_1 has no load. + + +The above info message is repeated 7 more times for the following (max. 5 shown): +clk_div_2, +clk_div_3, +clk_50M, +push<3>, +push<2> +To see the details of these info messages, please use the -detail switch. + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. + + + + Index: phr/trunk/codigo/demos/projects/demo1/_xmsgs/xst.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/demo1/_xmsgs/xst.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/_xmsgs/xst.xmsgs (revision 260) @@ -0,0 +1,24 @@ + + + +Input <clk_div_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <clk_div_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <clk_div_3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <push> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <clk_50M> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + + + Index: phr/trunk/codigo/demos/projects/demo1/top.xpi =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.xpi (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.xpi (revision 260) @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF Index: phr/trunk/codigo/demos/projects/demo1/top.ptwx =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.ptwx (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.ptwx (revision 260) @@ -0,0 +1,332 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> + Index: phr/trunk/codigo/demos/projects/demo1/top.ncd =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.ncd (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.ncd (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###3792:XlxV32DM 24ec eb8eNqlWNly2zgW/RU96G3KaWIjQKKTiizRCSfaIsmO0w/D4tqtmcR24nS6u2T/+1xs3ETZqYpdJu49F7g4OMRGj9PsgDw53pTf9/f725twhF7Q0RjLMwZ/OYG/z4E82998u//2z6fSR4092t+Xo7O70d85uceel559/4I874yNoMko/Vqmo7P919FtVUElW+YjqDE6ux19u71LPqd3L27yQtkvbn435V1ejaDP/Vd43H6Cx91XoPGNZPLsr1Gv59tPoz/2v/8xOvs2QscJ8yYhl7+sJzPEiDOoM5gzfGv4njOQM1wd39Xhrg53dbjLzIUzAmsIV1m4OoISCSoQSV4g9cAISRrGy/XlLrz78/6PX0novaqksND9X79yABAGZHW5U9Cnsrg3oCfPL+P5LNlNNm8ieEzfCkC2Sby8WOXyvPx0P/JeEJBngYR2w/j88iKZRfPJx2Qy+3dyfr66rlqReAnPogUAYxdfnSdAAMC8AdSAPDmdzJKrOPqQXEWbbbxaBnK6Wizi3S6acTndRBMwCjm9/Xxn+ODRIjWu7iRw9uocyRhEUeAvXZKpATU/YWzo21iKFpbxUrVcPmwvt+toOQvJdgf9PjxAy9X5L4Y51zY09OV8NZlFMyYXL7hXQMvFZJ1MF7N5vIyS1XoHo9imGlysZpfzqND2Ll5EkHaxzrRrhwuN0zsul9Huw2rzDssVpIP+fLmeTN9FMyKVSuq56feAmFzPtsn5fDV9l7xZzpLzeDmLl29QMIwnm+hCZapj6/lkGi2i5a5qgZfbyZuok/pqOh1M3cJ16n4b1fXizQZlGp+tlrvEvM7kcnm5jWbJOl5uTdcw+mQDo4ZUeQ3sPq6j1HhvZkk8M1XXs4WTzvYIaZLoegevDXKqRsjk0JOqPf6raKqJoiasMm8/LqftJu1xuSasFTadJ2rBWDk7+OYCSAMlWErx7Dpz9nKyiBCV63ewgLbxmyV0vUi2q8vNNKoUCm49QXy5jeawnEq5qxVVA6u0b9vrkdI+Au8v2sB6N/BVPI0SNZHgnVZdbLMrOsAClmLLh2UQzSykRhAv1vN4Gu9Mll3rJZi+tASawDw+36JCXscwV6/PrmfnsGrRaLu7NMZkO41jX14XWRIX0MF18TlZpP+9/XpVflVniIP2NzVEpToQuMw//S9h3iLQRrH/nqDGxI0Je2X+ufi0vympVHs8kbDjc6k3Pu+VNZAzsDOIM6gzmDP8V4Gs902L8VeZNhIvWcHmYB3UdnDbIW2Hth3Wdvy2w7VDJBx/RN6lX7nUe7zioA3kDAwE6+3fYgSwe2j0Lb0hKZNwFKiTQRcv6u1R48jgqI9jg+M+TgxO+jg1OO3jzOCsj/sG91s4l/bI0hW4qcBbFWBMf4HkZucHEzUmbkzSmLQxWWP6jcm1SSQc+JmsbwK/f2ZSX0mEdFcUyuRDc65MdrsNHC3hRXwdzdon49VkfhmFs/lHL4wvZkfgwwOuIM8mvopcCoTh9HLO/Gq6WG0xC7fz6AM8Vh8eHmD7eTiu8fDw+Pr1HcJUvn79d0rDi9AP0WGLs5CUIQlCRAhDAkxBWHa48UWI5I0fhL4c+zz0ffm4xelA3VxuiQgFDb027BOpqh/BYhjOh+FCFqnGTjOVY1aErJRjjEKRyhuSh4z4SCB4FWOSKWxMCmgGFYMQZvb3HcUmZYi901l9GsIu/55BcXh8z7AqxgzaFdBVoGJjX/c49r0Qdpsxq8JUaYWVbix1LFL5D/OhCwEl0+WcpKF/GPtVyCBVCAfemIQ+JKIhR5AgFESOhXo+vmVE/uazEB9wHmISPr6luZxTGhLdHtrwkHvyBvjIx8xIBe9NPQ9faCq/UF++pZn8DWNoggEvQ1SFj3s/h6py7xemKE2RqeKWp1CMmQh5AAOB1SXfwtv8kym9JIRFN4x6Yd4N417Y74ZJL8y6YdoL026Y9cKkG/Z7YdwN8054LwIbFsKOGzDexZDC/C6GFca6GAEscDoGQzruA94No16YdcO4FybdMOmFUTdMe0OtumHWCxfdsN8LZ91wV8dMy4zV72HMYNrC2qQ8zOSeemp+/Ysq6lAt09UAO6g48eUNrUL1fUhFSGBpqLZc7gnVs5KqEcEk52bx1s24aYZ0szQwzYTr5fFe1yeHl9AdRfIluPBN9B/4e7wP1CLAOkQoYJ58hPxkiD1sqX36+RD96jn2ZJA9PsmeWPa5YU9a7AvLPm+zp4Ps0RH7Yoh9+Rx7OsienGRPLfvCsKct9qVlX7TZs0H25Ih9OcS+eI49G2RPT7Jnln1p2LMW+8qyL9vs/SH25RH5aoh8/hx5f5A8O0net+QrQ95vyKeeJV+1yfNB6UWfvfCG2GfPseeD7P2T7LlhD71p9rzFHhn2EGqxF4PsvSP2aIh9+hx7Mcien2QvLHtk2IsWe2zZozb7dJB9cMQeD7EPnmOfDrIXJ9mnlj027NMWe2LZ4xZ7YfZxou4kKlWh2efyFlcd8r390jP7pfkxG08qDBkqb4lutGeZGUPQa4x0Y1udHQ1ZU2oNGZshG6XS1DTzmyHr+jDkQG+lL8E9OiOAPtwKVQ0QBVo0MIGqcEdXShRDSsAs70tR/owUxZAU/KQUxaAU6UkpCitFYaQojg8coK+lKKwUZQ23pKgGpcB9KQLvZ6Qoh6TwT0pRDUqRnZSislKURorq+PQC+lqK0kgReDXcSBGgQSnokRT4Z6SohqRgp6TQnI6lyE9JoesrKfSR8RLco6MQ6GspKisFruGWFGRIiuJICfoTSqTekBL0pBJkUInipBL2QpZ6RglyfK4CfaVE6lklaA23lGCDk4IfSeH/jBRoSApyUgo2KEV5Ugp7P0qRkYIdH9JAX0uBrBR+Dbek4ENSVEdKiJ9RAg8pgU8qwQeVqE4qYa8rKTZK8OMDH+hrJbBVQtRwS4l0cFKkR1JkPyMFGZICnZQiHZICeyelsLcH6EZLMXB7APpaCmKlyGq4lsJcQvDhPzx1NxB7rVKYcHcqe1FUGHe3RHv1VZjv7r32Lq8w5i7y9utEYdR9mtjvLYUR97FlvyAVht3nox0mYEHqxmhngcK4mwJ2jSiMuQVitxCFEbd/2A1WYcjtrvb8AUxU7vCxx7PCCnc229uLwjJ3dWl92gJfT8NK1+abkRi4sLD7GKMGrizsvnKYhoGXhuvvB9/AxMJ2zavX4OnRGtguAPXGPC2Mge1kUC/X0xrqF39TGmHtvwL+pCWsUkCzBkUNmjcobtCiQUmDlg1KG7RqUFajldegfoOiBuUNimu0oVuRGmx4VbQGGwIVq8FWT34NigbkNZg2oKjBvAGDGiwb0KzLzkZhYpcUrnr4QAhJc+GVHvwQD1NVBQdP+/A9xZVfEIyGfJcPCcyUD++3yp7iQYEHJWkghKdC3DPtqoBXT/lBwYUqC8/0e+QLEWg+/JQfZKps88x/QK/MyzURpwdCT/upV+hxOX36vsvX5lH8AA8k0qDdDw9S8ZSPRKbzC9vvsW/ytXmUP6RHVbTfC0JP+x6t9HiLAHtDvstXCEwcj+oHeLj548br5sspX3h+aftFQz4SnPT0QJ73Q4KUuCvA075Hi7wrSNd3+VqCIA/9kCI+6yrg06d8IawCdkb0fZevpYj+tzgyPOptR19+DVjUoD4SDJjVYObVYNCAZQ02W26e12CzZxdpDbY2fVGD9akBP69fTw8I4zDNfVFQzgE4P+ADDcxVR36hmXw8UNZ2oc768B42L0++h/6R/II85XxByHiQr1IFgQIq/x8j9yUD \ No newline at end of file Index: phr/trunk/codigo/demos/projects/demo1/top.pad =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.pad (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.pad (revision 260) @@ -0,0 +1,130 @@ +Release 12.3 - par M.70d (lin) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +Wed Apr 30 20:02:53 2014 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: top_map.ncd +OUTPUT FILE: top.pad +PART TYPE: xc3s200a +SPEED GRADE: -5 +PACKAGE: vq100 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +P1|||TMS|||||||||||| +P2|||TDI|||||||||||| +P3||DIFFMLR|IO_L01P_3|UNUSED||3||||||||| +P4||DIFFSLR|IO_L01N_3|UNUSED||3||||||||| +P5||DIFFMLR|IO_L02P_3|UNUSED||3||||||||| +P6||DIFFSLR|IO_L02N_3|UNUSED||3||||||||| +P7||DIFFSI_NDT|IP_3/VREF_3|UNUSED||3||||||||| +P8|||GND|||||||||||| +P9||DIFFMLR|IO_L03P_3/LHCLK0|UNUSED||3||||||||| +P10||DIFFSLR|IO_L03N_3/LHCLK1|UNUSED||3||||||||| +P11|||VCCO_3|||3|||||any******|||| +P12||DIFFMLR|IO_L04P_3/LHCLK2|UNUSED||3||||||||| +P13||DIFFSLR|IO_L04N_3/IRDY2/LHCLK3|UNUSED||3||||||||| +P14|||GND|||||||||||| +P15||DIFFMLR|IO_L05P_3/TRDY2/LHCLK6|UNUSED||3||||||||| +P16||DIFFSLR|IO_L05N_3/LHCLK7|UNUSED||3||||||||| +P17|||VCCINT||||||||1.2|||| +P18|||GND|||||||||||| +P19||DIFFMLR|IO_L06P_3|UNUSED||3||||||||| +P20||DIFFSLR|IO_L06N_3|UNUSED||3||||||||| +P21||DIFFMI_NDT|IP_3|UNUSED||3||||||||| +P22|||VCCAUX||||||||2.5|||| +P23|sw<7>|IBUF|IO_L01P_2/M1|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P24||DIFFMTB|IO_L02P_2/M2|UNUSED||2||||||||| +P25|leds<7>|IOB|IO_L01N_2/M0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P26|||VCCO_2|||2|||||2.50|||| +P27|leds<5>|IOB|IO_L02N_2/CSO_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P28|sw<5>|IBUF|IO_L03P_2/RDWR_B|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P29|sw<1>|IBUF|IO_L03N_2/VS2|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P30||DIFFMTB|IO_L04P_2/VS1|UNUSED||2||||||||| +P31|leds<1>|IOB|IO_L04N_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P32|sw<3>|IBUF|IO_L05P_2|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P33|leds<3>|IOB|IO_L05N_2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P34|sw<2>|IBUF|IO_L06P_2/D7|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P35|leds<2>|IOB|IO_L06N_2/D6|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P36|leds<6>|IOB|IO_L07P_2/D5|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P37|sw<6>|IBUF|IO_L07N_2/D4|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P38|||VCCINT||||||||1.2|||| +P39||IBUF|IP_2/VREF_2|UNUSED||2||||||||| +P40|leds<4>|IOB|IO_L08P_2/GCLK14|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P41|sw<4>|IBUF|IO_L08N_2/GCLK15|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P42|||GND|||||||||||| +P43|sw<0>|IBUF|IO_L09P_2/GCLK0|INPUT|LVCMOS25*|2||||IBUF||UNLOCATED|NO|NONE| +P44|leds<0>|IOB|IO_L09N_2/GCLK1|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P45|||VCCO_2|||2|||||2.50|||| +P46||DIFFSTB|IO_2/MOSI/CSI_B|UNUSED||2||||||||| +P47|||GND|||||||||||| +P48||DIFFMTB|IO_L10P_2/INIT_B|UNUSED||2||||||||| +P49||DIFFSTB|IO_L10N_2/D3|UNUSED||2||||||||| +P50||DIFFMTB|IO_L11P_2/D2|UNUSED||2||||||||| +P51||DIFFMTB|IO_L12P_2/D0/DIN/MISO|UNUSED||2||||||||| +P52||DIFFSTB|IO_L11N_2/D1|UNUSED||2||||||||| +P53||DIFFSTB|IO_L12N_2/CCLK|UNUSED||2||||||||| +P54|||DONE|||||||||||| +P55|||VCCAUX||||||||2.5|||| +P56||DIFFMLR|IO_L01P_1|UNUSED||1||||||||| +P57||DIFFSLR|IO_L01N_1|UNUSED||1||||||||| +P58|||GND|||||||||||| +P59||DIFFMLR|IO_L02P_1/RHCLK0|UNUSED||1||||||||| +P60||DIFFSLR|IO_L02N_1/RHCLK1|UNUSED||1||||||||| +P61||DIFFMLR|IO_L03P_1/RHCLK2|UNUSED||1||||||||| +P62||DIFFSLR|IO_L03N_1/TRDY1/RHCLK3|UNUSED||1||||||||| +P63|||GND|||||||||||| +P64||DIFFMLR|IO_L04P_1/IRDY1/RHCLK6|UNUSED||1||||||||| +P65||DIFFSLR|IO_L04N_1/RHCLK7|UNUSED||1||||||||| +P66|||VCCINT||||||||1.2|||| +P67|||VCCO_1|||1|||||any******|||| +P68||DIFFMI_NDT|IP_1/VREF_1|UNUSED||1||||||||| +P69|||GND|||||||||||| +P70||DIFFMLR|IO_L05P_1|UNUSED||1||||||||| +P71||DIFFSLR|IO_L05N_1|UNUSED||1||||||||| +P72||DIFFMLR|IO_L06P_1|UNUSED||1||||||||| +P73||DIFFSLR|IO_L06N_1|UNUSED||1||||||||| +P74|||GND|||||||||||| +P75|||TDO|||||||||||| +P76|||TCK|||||||||||| +P77||DIFFMTB|IO_L01P_0/VREF_0|UNUSED||0||||||||| +P78||DIFFSTB|IO_L01N_0|UNUSED||0||||||||| +P79|||VCCO_0|||0|||||any******|||| +P80|||GND|||||||||||| +P81|||VCCINT||||||||1.2|||| +P82||IBUF|IP_0/VREF_0|UNUSED||0||||||||| +P83||DIFFMTB|IO_L02P_0/GCLK4|UNUSED||0||||||||| +P84||DIFFSTB|IO_L02N_0/GCLK5|UNUSED||0||||||||| +P85||DIFFMTB|IO_L03P_0/GCLK6|UNUSED||0||||||||| +P86||DIFFSTB|IO_L03N_0/GCLK7|UNUSED||0||||||||| +P87|||GND|||||||||||| +P88||DIFFMTB|IO_L04P_0/GCLK8|UNUSED||0||||||||| +P89||DIFFSTB|IO_L04N_0/GCLK9|UNUSED||0||||||||| +P90||DIFFSTB|IO_0/GCLK11|UNUSED||0||||||||| +P91|||GND|||||||||||| +P92|||VCCAUX||||||||2.5|||| +P93||DIFFMTB|IO_L05P_0|UNUSED||0||||||||| +P94||DIFFSTB|IO_L05N_0|UNUSED||0||||||||| +P95|||GND|||||||||||| +P96|||VCCO_0|||0|||||any******|||| +P97||IBUF|IP_0|UNUSED||0||||||||| +P98||DIFFMTB|IO_L06P_0/VREF_0|UNUSED||0||||||||| +P99||DIFFSTB|IO_L06N_0/PUDC_B|UNUSED||0||||||||| +P100|||PROG_B|||||||||||| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + Index: phr/trunk/codigo/demos/projects/demo1/top_ngdbuild.xrpt =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top_ngdbuild.xrpt (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top_ngdbuild.xrpt (revision 260) @@ -0,0 +1,71 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+ +
+ + + +
+ + +
+ + + + + +
+
+ + + +
+
+ + + +
+
+
+
+ + + + Index: phr/trunk/codigo/demos/projects/demo1/top.ngc =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.ngc (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.ngc (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$42x54=32@D[YY4urj?7?69n221EC^ZT;qt82<7688047AZTQWW>icc{5=1<364BTQ\MK@H12IDA@G[TDF4?FTBI]OO=6G;;H@VB6=NF_=0@BIFC@N4?H(08mUG;6@JTVMQO4=H<2EIYK:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI;5\OTP@A1=SQYOh7X]JR^TJWLDKM01]EHYPTXRF5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^T\ECI:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z8;bnh[06J12iggRjfv^3:?fjlWmc}S?74cmi\`lpX;>1gii}30?58h`bt484<7akks=0=3>jblz682:5ceeq?0;1>_HLU[5djblzU9Sca{01235ZOI^V:i7akks^1\KGSA9<1gii}P3^llp56788UBB[Q?b:nf`vY3WFH^J<;4ldfp[1Yig}:;<=?PIOT\4g=kmmyT9RAMUG36?icc{V?Tbbz?0122[LHQW9h0`hj|_7]LFP@6=2fnh~Q9_omw45679VCEZR>m;mggwZ1XGK_M=85ceeq\3Zhh|9:;<vr{a6;2:5urj?5;1>49ps949=2y|0>0:;ru?0;3<{~6>285|w=4=3>up4>0;285|w=5==>upW9UBNXH6;ru\5ZOE]O30zQ=_H@VB<=tV9TEO[I9:qt[1YNJ\L27~yP5^KAQC?<{~U=SDLZF89psZ1XAK_M?6z`p028|f5t:9:j!8#yq023yEFwi11KLu:j:G81>4}T=3;j6l4>3272<`<40:>2wc?7:09m5<<13-;<6<;4}R695d{R795d6>4<01/=946;%g90c=e7:j;[197~4=83;1qd?l:188m4b=831b=h4?::k2f?6=3f8<6=4+11812>ha2910c?;50;&24?413gl1=65`2583>!772;<0bk4=;:m17?6=,8:1>;5af;18?j45290/==4=6:le>1=0;05?k`==21d>=4?:%33>70f;29 46=:?1ej794;h1`>5<#9908n6`i:198m6g=83.:<7=m;od95>=n;00;6)??:2`8jc<532c847>5$0297g=in3907d:::18'55<3<2dm6=54i5194?"683>?7ch51:9j07<72-;;69:4ng81?>o393:1(<>5459mb?5<3`>;6=4+11870>ha2=10e>h50;&24?233gl1965f3d83>!772=>0bk49;:k0`?6=,8:1895af;58?g2c29096=4?{%31>2=O9?1C=>5f6;29?je=831vn9m50;094?6|,881;6F>6:J27>o12900cn4?::a0g<72;0;6=u+1384?M713A;87d850;9lg?6=3th?m7>52;294~"6:3=0D<84H018m3<722eh6=44}c6:>5<5290;w)?=:69K53=O9:1b:7>5;na94?=zj=21<7<50;2x 44=?2B::6F>3:k5>5<7<729q/=?48;I35?M743`<1<75`c;29?xd3>3:1>7>50z&26?1<@8<0D<=4i783>>id2900qo=9:181>5<7s-;96i5G179K56=n>3:17bm50;9~f62=8381<7>t$009`>N6>2B:?6g9:188kf<722wi??4?:383>5}#9;0o7E?9;I30?l0=831do7>5;|`04?6=:3:12;f8L40<@890e;4?::m`>5<N6;2c=6=44ob83>>{e:h0;6?4?:1y'577j4H048L45==O9?1C=>5f6;29?je=831vn>;50;094?6|,88146F>6:J27>o12900cn4?::a76<72;0;6=u+138;?M713A;87d850;9lg?6=3th8=7>52;294~"6:320D<84H018m3<722eh6=44}c0e>5<5290;w)?=:99K53=O9:1b:7>5;na94?=zj;n1<7<50;2x 44=02B::6F>3:k5>5<7<729q/=?47;I35?M743`<1<75`c;29?xd513:1>7>50z&26?><@8<0D<=4i783>>id2900q~?i:181[7a34836n5rs3294?4|V;:01?o5c:p64<72;qU><522b8`?xu5:3:1>vP=2:?1a?e7}Y:<16?94l;|q13?6=:rT9;63<6;a8yv4?2909w0<7:79>6<52z?1e?0<5;h1o6s|2b83>7}::j0=703=:;80h7p}<2;296~;4:3<01>=5c:p71<72;q6?949;<16>f=z{:<1<7;4?3i0q~=k:181[5c34>=6;5rs2g94?4|V:o019956:p7c<72;qU?k524985?xu383:1>vP;0:?7=?0:6=4={_62?82f2?1v9<50;0xZ14<5=h1:6s|4283>7}Y<:168n49;|q71?6=:rT?963;d;48yv212909w0:9:b9>6<<13ty?;7>52z?73?e<5;h1:6s|4983>7}:<10h70j6=4={<6b>f=:;80=7p};b;296~;3j3i01>=56:p0f<72;q68n4l;<16>3=z{=n1<7;4?3<0qp`98;295~N6;2we:44?:0yK56=zf?k1<7?tH018yk0e290:wE?<;|l5g?6=9rB:?6sa6e83>4}O9:1vb;k50;3xL45{I30?xh083:1=vF>3:m34<728qC=>5rn6094?7|@890qc9<:182M743td<87>51zJ27>{i?<0;65<6sA;87p`88;295~N6;2we;44?:0yK56=zf>k1<7?tH018yk1e290:wE?<;|l4g?6=9rB:?6sa7e83>4}O9:1vb:k50;3xL45{I30?xh?83:1=vF>3:m<4<728qC=>5rn9094?7|@890qc6<:182M743td387>51zJ27>{i0<0;65<6sA;87psr}AB@d>=jm}ABA5{GHYqvLM \ No newline at end of file Index: phr/trunk/codigo/demos/projects/demo1/top.pcf =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.pcf (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.pcf (revision 260) @@ -0,0 +1,4 @@ +//! ************************************************************************** +// Written by: Map M.70d on Wed Apr 30 20:02:35 2014 +//! ************************************************************************** + Index: phr/trunk/codigo/demos/projects/demo1/top.ngd =================================================================== --- phr/trunk/codigo/demos/projects/demo1/top.ngd (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/top.ngd (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$7cx4>713-Xnzd}foo8#5+439'8%8-*k;2q145gqy8:;!8?>;58JJUSS2yxd1=50?d8>=G\^[YY4ceeq?3?69;2H^J<>4BTKO@ZRFZNO_M_MG8:@VWZOINF30OBCBIUVF@2=DZLK_IIk4DSA\WPEDMZYMYA64EYRBJACC981NT]OADDF\FFBXN@FN=95JXQCM@@BXKFDXX_OFNUQ25>C_XHDOIIQFSD]EMIC63@>0EO[I2:KM<>OINLXYII=4IOTf?LHXFNNTMCJPBBF5?LIDGDZ=7DA[YQG4?IOEZHXR:6B@AEGG3>JHO@IJ@:5B.62g[IeKnffx]i}foo58J@RPG[A:7B:4OCWE7>IR\:1[MI:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6V\TMKA2>^cjVCon6Vkh^RqmhOi~j1SheQ_rhoW}uca3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv4?fjlW<:F56mck^fjrZ7>3jf`Sigy_3;8gimXl`|T?:5ceeq?4;169oaau;<7=0`hj|<4<4?icc{5<556bjdr>4>5803eoo191b:nf`vY7WFH^J<;4ldfp[5Yig}:;<=?PIOT\4g=kmmyT=RAMUG36?icc{V;Tbbz?0122[LHQW9h0`hj|_3]LFP@6=2fnh~Q=_omw45679VCEZR>m;mggwZ5XGK_M=85ceeq\7Zhh|9:;<jblzU?SBLZF078h`btW=Uecy>?013\MKPX8k1gii}P5^MAQC723eooR;Pnnv34566W@D]S=l4ldfp[3YHJ\L:96bjdr]5[kis89:;=RGAV^2a?icc{V=TCO[I149oaauX?Vddx=>?00]JJSY702dlho{fle58tpuo494<7}{|h=3=3>vr{a69245urj?7?69?2z~e2<>89ptdtsig9j96}x<1<6?vq;97?0z2=>49ps959=2y|090:;ru?1;3<{~6=2:5|w=594;3<{~6<245|w^2\MGSA12y|SupWFGp?=1J7:51zQb>67=9k0:?>;>8d80<62>sg8m6<5a3185?!4e2;30q^753082f?74;<;3i7=735a8W4?=6>4=81X57:i:08276360l084>;<;e44>5<628qXm7=>:0`9565291o1?5=;9:&4>03<@k1}Xn4?:082>7>|[h08=7?m:01014>b2:28845+2982e>P5m38py5uG269'63<1?2P36>u::287>xo4;3:17d=;:188m63=831b??4?::m0a?6=,;?1?i5a2583?>i4k3:1(?;53e9m61<632e8n7>5$3797a=i:=0976a94<;:m0=?6=,;?1?i5a2587?>i403:1(?;53e9m61<232e8;7>5$3797a=i:=0=76a<6;29 73=;m1e>948;:k60?6=,;?19>5a2583?>o2:3:1(?;5529m61<632c>=7>5$37916=i:=0976g:0;29 73==:1e>94<;:k6a?6=,;?19i5a2583?>o2k3:1(?;55e9m61<632c>n7>5$3791a=i:=0976g:a;29 73==m1e>94<;:k6=?6=,;?19i5a2587?>o203:1(?;55e9m61<232c>;7>5$3791a=i:=0=76g:6;29 73==m1e>948;:`52?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`51?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`50?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`57?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`56?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`55?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`54?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`6b?6=:3:10:>6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`7`?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`7f?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`7=?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`73?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`71?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`77?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`75?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`0b?6=:3:109=6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4;|`7a?6=:3:15$3f957=5}#:?0:86F=a:J13>"5l3<0(<65699j55<72-8o6<<4;n3e>5<#:m09=6F=c:9~f1g=8381<7>t$34951=O:h1C>:5+2e85?!7?2?20e<>50;&1`?7532e:j7>5$3f964=O:j10qo:7:181>5<7s-8=6<:4H3c8L71<,;n1:6*>8;4;?l77290/>i4>2:9l5c<72-8o6??4H3a8?xd3>3:1>7>50z&12?733A8j7E<8;%0g>3=#910=46g>0;29 7b=9;10c7<729q/>;4>4:J1e>N5?2.9h784$0:92==n990;6)i4=1:J1g>=zj=81<7<50;2x 70=9=1C>l5G269'6a<13-;36;64i0294?"5l3;976a>f;29 7b=:81C>n54}c63>5<5290;w)<9:068L7g<@;=0(?j56:&2=h9o0;6)51;294~"5l3897E<8;I30?!702;;0c?<50;&1`?4532wi?:4?:083>5}#:m09>6F=7:J27>"6?38:7b<=:18'6a<5:21vn>650;394?6|,;n1>?5G269K56=#9>09=6a=2;29 7b=:;10qo=6:182>5<7s-8o6?<4H358L45<,8=1><5`2383>!4c2;807pl4<729q/>i4=2:J13>N6;2.:;7<>;n01>5<#:m09>65rb2a94?7=83:p(?j5239K62=O9:1/=:4=1:m16?6=,;n1>?54}c1f>5<6290;w)N5?2B:?6*>7;31?l45290/>i4=2:9~f0>=83;1<7>t$3f967=O:>1C=>5+16826>o5:3:1(?j52398yg3>290:6=4?{%0g>74<@;=0D<=4$05957=n:;0;6)50z&1`?453A8<7E?<;%34>44{e=k0;6<4?:1y'6a<5:2B9;6F>3:&23?753`896=4+2e816>=zj:5G129'52<6:2c9>7>5$3f967=:183!4c2;80D?94H018 41=9;1b>?4?:%0g>74<3ty8:7>53z\02>;4n3;m70=9:308yv502908wS=8;<62>4`<5:=1>?5rs2:94?5|V:2019=51g9>7=<5:2wx?44?:2y]7<=:<<0:j63<9;01?xu4i3:1?vP5<4sW9i70:6:0d896d=:;1v>m50;1xZ6e<5=h1=k523b816>{t;l0;6>uQ3d9>0a<6n278i7<=;|q0b?6=:r78j7??;<63>4`:6=4={<62>46<5=81=k5rs5194?4|5=91==524582b>{t<<0;6?u244824>;3>3;m7p};7;296~;3?3;;70:7:0d8yv2>2909w0:6:02891g=9o1v9l50;0x91d=99168n4>f:p0a<72;q68i4>0:?7a?7a3ty>:7>53z\62>;2n3;;70;9:308yv302908wS;8;<43>46<5<=1>?5rs4:94?5|V<201;?5119>1=<5:2wx944?:2y]1<=:>;0:<63:9;01?xu2i3:1?vP:a:?57?7734?j6?<4}r7a>5<4sW?i708;:02890d=:;1v8m50;1xZ0e<5??1==525b816>{t=l0;6>uQ5d9>23<6827>i7<=;|q6b?6=:r7>j7?i;<63>464`<5=81==5rs7394?4|5?;1=k5245824>{t>;0;6?u26382b>;3>3;;7p}93;296~;1;3;m70:7:028yv032909w08;:0d891g=991v;;50;0x933=9o168n4>0:p23<72;q6:;4>f:?7a?773ty8?7>51z\07>{t;=0;6;4}r11>5<6sW997p}:4;295~X2<2wx9?4?:0y]17=z{<;1<7?t^438yv37290:wS;?;|m:5F23827{I04?L4528q96psa8e83>4}O:>1B>?4>{38~yk>b290:wE<8;H01>4}52twe4k4?:0yK62=N:;0:w?4r}o;3>5<6sA8<7D<=:0y1>x{i180;6:5rn8694?7|@;=0qc7::182M403td2:7>51zJ13>{i1>0;6=83;pD?94}o;:>5<6sA8<7p`6a;295~N5?2we5o4?:0yK62=N:;0:w<4r}o;`>5<6sA8<7D<=:0y2>x{i1m0;6:|m=c<728qC>:5F23824{I04?L4528q:6psaa083>4}O:>1B>?4>{08~ykg5290:wE<8;H01>4}62twem>4?:0yK62=zfh>1<7?tH358ykg2290:wE<8;|lb2?6=9rB9;6saa683>4}O:>1vbl650;3xL71{I04?xhfi3:1=vF=7:meg<728qvblm50;3xykgc290:wp`ne;295~{iio0;6{|la6?6=9rwvqpNOCzfa><750:l;ipNOBz2~DEV|uIJ \ No newline at end of file Index: phr/trunk/codigo/demos/projects/demo1/.compxlib.log =================================================================== Index: phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl =================================================================== --- phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/pa.fromHdl.tcl (revision 260) @@ -0,0 +1,14 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name demo1 -dir "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/planAhead_run_1" -part xc3s200avq100-5 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property top top $srcset +set_param project.paUcfFile "top.ucf" +set hdlfile [add_files [list {top.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +add_files "top.ucf" -fileset [get_property constrset [current_run]] +add_files -norecurse { {/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1} } +open_rtl_design -part xc3s200avq100-5 Index: phr/trunk/codigo/demos/projects/demo1/xst/work/hdpdeps.ref =================================================================== --- phr/trunk/codigo/demos/projects/demo1/xst/work/hdpdeps.ref (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/xst/work/hdpdeps.ref (revision 260) @@ -0,0 +1,8 @@ +V3 3 +FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd 2014/04/30.20:01:51 M.70d +EN work/top 1398898936 \ + FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd \ + PB ieee/std_logic_1164 1284609568 +AR work/top/Behavioral 1398898937 \ + FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd \ + EN work/top 1398898936 Index: phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl00.vho =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl00.vho =================================================================== --- phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl00.vho (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl00.vho (revision 260)
phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl00.vho Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl01.vho =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl01.vho =================================================================== --- phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl01.vho (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl01.vho (revision 260)
phr/trunk/codigo/demos/projects/demo1/xst/work/sub00/vhpl01.vho Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/demo1/xst/work/hdllib.ref =================================================================== --- phr/trunk/codigo/demos/projects/demo1/xst/work/hdllib.ref (nonexistent) +++ phr/trunk/codigo/demos/projects/demo1/xst/work/hdllib.ref (revision 260) @@ -0,0 +1,2 @@ +EN top NULL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd sub00/vhpl00 1398898936 +AR top behavioral /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/demo1/top.vhd sub00/vhpl01 1398898937 Index: phr/trunk/codigo/demos/projects/demo1/top.ucf =================================================================== Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.dly =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.dly (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.dly (revision 260) @@ -0,0 +1,22 @@ +Release 5.1i - Par F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + +Thu May 29 12:19:45 2003 + +File: btndemo.dly + + The 20 Worst Net Delays are: +------------------------------- +| Max Delay (ns) | Netname | +------------------------------- + 0.926 bnbuf +--------------------------------- + +------------------------------------------------------------------------------- + Net Delays +------------------------------------------------------------------------------- + +bnbuf + btn.GCLKOUT + 0.926 led.O + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_last_par.ncd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_last_par.ncd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_last_par.ncd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_last_par.ncd (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/btndemo_last_par.ncd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.prj =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.prj (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.prj (revision 260) @@ -0,0 +1 @@ +vhdl work "BtnDemo.vhd" Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_ngdbuild.nav =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_ngdbuild.nav (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_ngdbuild.nav (revision 260) @@ -0,0 +1,2 @@ + + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.mrp =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.mrp (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.mrp (revision 260) @@ -0,0 +1,170 @@ +Release 6.2.03i Map G.31a +Xilinx Mapping Report File for Design 'btndemo' + +Design Information +------------------ +Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-5 -cm +area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +Target Device : x2s200 +Target Package : pq208 +Target Speed : -5 +Mapper Version : spartan2 -- $Revision: 1.16.8.1 $ +Mapped Date : Wed Jul 07 09:50:05 2004 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 1 +Logic Utilization: +Logic Distribution: + Number of Slices containing only related logic: 0 out of 0 0% + Number of Slices containing unrelated logic: 0 out of 0 0% + *See NOTES below for an explanation of the effects of unrelated logic + Number of bonded IOBs: 1 out of 140 1% + Number of GCLKIOBs: 1 out of 4 25% + +Total equivalent gate count for design: 0 +Additional JTAG gate count for IOBs: 96 +Peak Memory Usage: 61 MB + +NOTES: + + Related logic is defined as being logic that shares connectivity - + e.g. two LUTs are "related" if they share common inputs. + When assembling slices, Map gives priority to combine logic that + is related. Doing so results in the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin + packing unrelated logic into a slice once 99% of the slices are + occupied through related logic packing. + + Note that once logic distribution reaches the 99% level through + related logic packing, this does not mean the device is completely + utilized. Unrelated logic packing will then begin, continuing until + all usable LUTs and FFs are occupied. Depending on your timing + budget, increased levels of unrelated logic packing may adversely + affect the overall timing performance of your design. + + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group Summary +Section 10 - Modular Design Summary +Section 11 - Timing Report +Section 12 - Configuration String Information +Section 13 - Additional Device Resource Counts + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT - Dedicated Clock IO IBUFG symbol "U1" (output signal=led_OBUF) is + not driving a global clock buffer of a DLL. This configuration will result in + high clock skew and long net delay. + +Section 3 - Informational +------------------------- +INFO:LIT:95 - All of the external outputs in this design are using slew rate + limited output drivers. The delay on speed critical outputs can be + dramatically reduced by designating them as fast outputs in the schematic. +INFO:MapLib:562 - No environment variables are currently set. + +Section 4 - Removed Logic Summary +--------------------------------- + +Section 5 - Removed Logic +------------------------- + +Section 6 - IOB Properties +-------------------------- + ++------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Strength | Rate | | | Delay | ++------------------------------------------------------------------------------------------------------------------------+ +| btn | GCLKIOB | INPUT | LVTTL | | | | | | +| led | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | ++------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group Summary +------------------------------ +No area groups were found in this design. + +Section 10 - Modular Design Summary +----------------------------------- +Modular Design not used for this design. + +Section 11 - Timing Report +-------------------------- +This design was not run using timing mode. + +Section 12 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 13 - Additional Device Resource Counts +---------------------------------------------- +Number of JTAG Gates for IOBs = 2 +Number of Equivalent Gates for Design = 0 +Number of RPM Macros = 0 +Number of Hard Macros = 0 +PCI IOBs = 0 +PCI LOGICs = 0 +CAPTUREs = 0 +BSCANs = 0 +STARTUPs = 0 +DLLs = 0 +GCLKIOBs = 1 +GCLKs = 0 +Block RAMs = 0 +TBUFs = 0 +Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 0 +IOB Latches not driven by LUTs = 0 +IOB Latches = 0 +IOB Flip Flops not driven by LUTs = 0 +IOB Flip Flops = 0 +Unbonded IOBs = 0 +Bonded IOBs = 1 +Shift Registers = 0 +Static Shift Registers = 0 +Dynamic Shift Registers = 0 +16x1 ROMs = 0 +16x1 RAMs = 0 +32x1 RAMs = 0 +Dual Port RAMs = 0 +MULTANDs = 0 +MUXF5s + MUXF6s = 0 +4 input LUTs used as Route-Thrus = 0 +4 input LUTs = 0 +Slice Latches not driven by LUTs = 0 +Slice Latches = 0 +Slice Flip Flops not driven by LUTs = 0 +Slice Flip Flops = 0 +Slices = 0 +Number of LUT signals with 4 loads = 0 +Number of LUT signals with 3 loads = 0 +Number of LUT signals with 2 loads = 0 +Number of LUT signals with 1 load = 0 +NGM Average fanout of LUT = -1.#J +NGM Maximum fanout of LUT = 0 +NGM Average fanin for LUT = -1.#IND +Number of XVK_GCLKIBUF symbols = 1 +Number of OPAD symbols = 1 +Number of OBUF symbols = 1 +Number of IPAD symbols = 1 Index: phr/trunk/codigo/demos/projects/BtnDemo/automake.log =================================================================== Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xpi =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xpi (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xpi (revision 260) @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pad =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pad (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pad (revision 260) @@ -0,0 +1,237 @@ +Release 6.2.03i - Par G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Wed Jul 07 09:50:28 2004 + + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The | +character is used as the data field separator. This file is also designed +to support parsing. + +INPUT FILE: btndemo_map.ncd +OUTPUT FILE: btndemo.pad +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: pq208 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint| +P1|||GND|||||||||| +P2|||TMS|||||||||| +P3||IOB||UNUSED||(0,7)***||||||| +P4||IOB|IO_VREF_7|UNUSED||(0,7)***||||||| +P5||IOB||UNUSED||(0,7)***||||||| +P6||IOB|IO_VREF_7|UNUSED||(0,7)***||||||| +P7||IOB||UNUSED||(0,7)***||||||| +P8||IOB||UNUSED||(0,7)***||||||| +P9||IOB|IO_VREF_7|UNUSED||(0,7)***||||||| +P10||IOB||UNUSED||(0,7)***||||||| +P11|||GND|||||||||| +P12|||VCCO|||0|||||na|| +P13|||VCCINT||||||||2.5|| +P14||IOB||UNUSED||(0,7)***||||||| +P15||IOB||UNUSED||(0,7)***||||||| +P16||IOB||UNUSED||(0,7)***||||||| +P17||IOB||UNUSED||(0,7)***||||||| +P18||IOB||UNUSED||(0,7)***||||||| +P19|||GND|||||||||| +P20||IOB|IO_VREF_7|UNUSED||(0,7)***||||||| +P21||IOB||UNUSED||(0,7)***||||||| +P22||IOB||UNUSED||(0,7)***||||||| +P23||IOB||UNUSED||(0,7)***||||||| +P24||PCIIOB|IO_IRDY|UNUSED||(0,7)***||||||| +P25|||GND|||||||||| +P26|||VCCO|||0|||||na|| +P27||PCIIOB|IO_TRDY|UNUSED||(0,6)***||||||| +P28|||VCCINT||||||||2.5|| +P29||IOB||UNUSED||(0,6)***||||||| +P30||IOB||UNUSED||(0,6)***||||||| +P31||IOB|IO_VREF_6|UNUSED||(0,6)***||||||| +P32|||GND|||||||||| +P33||IOB||UNUSED||(0,6)***||||||| +P34||IOB||UNUSED||(0,6)***||||||| +P35||IOB||UNUSED||(0,6)***||||||| +P36||IOB||UNUSED||(0,6)***||||||| +P37||IOB||UNUSED||(0,6)***||||||| +P38|||VCCINT||||||||2.5|| +P39|||VCCO|||0|||||na|| +P40|||GND|||||||||| +P41||IOB||UNUSED||(0,6)***||||||| +P42||IOB|IO_VREF_6|UNUSED||(0,6)***||||||| +P43||IOB||UNUSED||(0,6)***||||||| +P44||IOB||UNUSED||(0,6)***||||||| +P45||IOB|IO_VREF_6|UNUSED||(0,6)***||||||| +P46||IOB||UNUSED||(0,6)***||||||| +P47||IOB|IO_VREF_6|UNUSED||(0,6)***||||||| +P48||IOB||UNUSED||(0,6)***||||||| +P49||IOB||UNUSED||(0,6)***||||||| +P50|||M1|||||||||| +P51|||GND|||||||||| +P52|||M0|||||||||| +P53|||VCCO|||0|||||na|| +P54|||M2|||||||||| +P55|||NC|||||||||| +P56|||NC|||||||||| +P57||IOB|IO_VREF_5|UNUSED||(0,5)***||||||| +P58||IOB||UNUSED||(0,5)***||||||| +P59||IOB|IO_VREF_5|UNUSED||(0,5)***||||||| +P60||IOB||UNUSED||(0,5)***||||||| +P61||IOB||UNUSED||(0,5)***||||||| +P62||IOB|IO_VREF_5|UNUSED||(0,5)***||||||| +P63||IOB||UNUSED||(0,5)***||||||| +P64|||GND|||||||||| +P65|||VCCO|||0|||||na|| +P66|||VCCINT||||||||2.5|| +P67||IOB||UNUSED||(0,5)***||||||| +P68||IOB||UNUSED||(0,5)***||||||| +P69||IOB||UNUSED||(0,5)***||||||| +P70||IOB||UNUSED||(0,5)***||||||| +P71|led|IOB||OUTPUT|LVTTL|(0,5)***|12|SLOW|NONE**|||LOCATED| +P72|||GND|||||||||| +P73||IOB|IO_VREF_5|UNUSED||(0,5)***||||||| +P74||IOB||UNUSED||(0,5)***||||||| +P75||IOB||UNUSED||(0,5)***||||||| +P76|||VCCINT||||||||2.5|| +P77|btn|GCLKIOB|GCK1|INPUT|LVTTL|(0,5)***||||||LOCATED| +P78|||VCCO|||0|||||na|| +P79|||GND|||||||||| +P80||GCLKIOB|GCK0|UNUSED||(0,4)***||||||| +P81||IOB||UNUSED||(0,4)***||||||| +P82||IOB||UNUSED||(0,4)***||||||| +P83||IOB||UNUSED||(0,4)***||||||| +P84||IOB|IO_VREF_4|UNUSED||(0,4)***||||||| +P85|||GND|||||||||| +P86||IOB||UNUSED||(0,4)***||||||| +P87||IOB||UNUSED||(0,4)***||||||| +P88||IOB||UNUSED||(0,4)***||||||| +P89||IOB||UNUSED||(0,4)***||||||| +P90||IOB||UNUSED||(0,4)***||||||| +P91|||VCCINT||||||||2.5|| +P92|||VCCO|||0|||||na|| +P93|||GND|||||||||| +P94||IOB||UNUSED||(0,4)***||||||| +P95||IOB|IO_VREF_4|UNUSED||(0,4)***||||||| +P96||IOB||UNUSED||(0,4)***||||||| +P97||IOB||UNUSED||(0,4)***||||||| +P98||IOB|IO_VREF_4|UNUSED||(0,4)***||||||| +P99||IOB||UNUSED||(0,4)***||||||| +P100||IOB|IO_VREF_4|UNUSED||(0,4)***||||||| +P101||IOB||UNUSED||(0,4)***||||||| +P102||IOB||UNUSED||(0,4)***||||||| +P103|||GND|||||||||| +P104|||DONE|||||||||| +P105|||VCCO|||0|||||na|| +P106|||PROGRAM|||||||||| +P107||IOB|IO_INIT|UNUSED||(0,3)***||||||| +P108||IOB|IO_D7|UNUSED||(0,3)***||||||| +P109||IOB|IO_VREF_3|UNUSED||(0,3)***||||||| +P110||IOB||UNUSED||(0,3)***||||||| +P111||IOB|IO_VREF_3|UNUSED||(0,3)***||||||| +P112||IOB||UNUSED||(0,3)***||||||| +P113||IOB||UNUSED||(0,3)***||||||| +P114||IOB|IO_VREF_3|UNUSED||(0,3)***||||||| +P115||IOB|IO_D6|UNUSED||(0,3)***||||||| +P116|||GND|||||||||| +P117|||VCCO|||0|||||na|| +P118|||VCCINT||||||||2.5|| +P119||IOB|IO_D5|UNUSED||(0,3)***||||||| +P120||IOB||UNUSED||(0,3)***||||||| +P121||IOB||UNUSED||(0,3)***||||||| +P122||IOB||UNUSED||(0,3)***||||||| +P123||IOB||UNUSED||(0,3)***||||||| +P124|||GND|||||||||| +P125||IOB|IO_VREF_3|UNUSED||(0,3)***||||||| +P126||IOB|IO_D4|UNUSED||(0,3)***||||||| +P127||IOB||UNUSED||(0,3)***||||||| +P128|||VCCINT||||||||2.5|| +P129||PCIIOB|IO_TRDY|UNUSED||(0,3)***||||||| +P130|||VCCO|||0|||||na|| +P131|||GND|||||||||| +P132||PCIIOB|IO_IRDY|UNUSED||(0,2)***||||||| +P133||IOB||UNUSED||(0,2)***||||||| +P134||IOB||UNUSED||(0,2)***||||||| +P135||IOB|IO_D3|UNUSED||(0,2)***||||||| +P136||IOB|IO_VREF_2|UNUSED||(0,2)***||||||| +P137|||GND|||||||||| +P138||IOB||UNUSED||(0,2)***||||||| +P139||IOB||UNUSED||(0,2)***||||||| +P140||IOB||UNUSED||(0,2)***||||||| +P141||IOB||UNUSED||(0,2)***||||||| +P142||IOB|IO_D2|UNUSED||(0,2)***||||||| +P143|||VCCINT||||||||2.5|| +P144|||VCCO|||0|||||na|| +P145|||GND|||||||||| +P146||IOB|IO_D1|UNUSED||(0,2)***||||||| +P147||IOB|IO_VREF_2|UNUSED||(0,2)***||||||| +P148||IOB||UNUSED||(0,2)***||||||| +P149||IOB||UNUSED||(0,2)***||||||| +P150||IOB|IO_VREF_2|UNUSED||(0,2)***||||||| +P151||IOB||UNUSED||(0,2)***||||||| +P152||IOB|IO_VREF_2|UNUSED||(0,2)***||||||| +P153||IOB|IO_DIN_D0|UNUSED||(0,2)***||||||| +P154||IOB|IO_DOUT_BUSY|UNUSED||(0,2)***||||||| +P155|||CCLK|||||||||| +P156|||VCCO|||0|||||na|| +P157|||TDO|||||||||| +P158|||GND|||||||||| +P159|||TDI|||||||||| +P160||IOB|IO_CS|UNUSED||(0,1)***||||||| +P161||IOB|IO_WRITE|UNUSED||(0,1)***||||||| +P162||IOB|IO_VREF_1|UNUSED||(0,1)***||||||| +P163||IOB||UNUSED||(0,1)***||||||| +P164||IOB|IO_VREF_1|UNUSED||(0,1)***||||||| +P165||IOB||UNUSED||(0,1)***||||||| +P166||IOB||UNUSED||(0,1)***||||||| +P167||IOB|IO_VREF_1|UNUSED||(0,1)***||||||| +P168||IOB||UNUSED||(0,1)***||||||| +P169|||GND|||||||||| +P170|||VCCO|||0|||||na|| +P171|||VCCINT||||||||2.5|| +P172||IOB||UNUSED||(0,1)***||||||| +P173||IOB||UNUSED||(0,1)***||||||| +P174||IOB||UNUSED||(0,1)***||||||| +P175||IOB||UNUSED||(0,1)***||||||| +P176||IOB||UNUSED||(0,1)***||||||| +P177|||GND|||||||||| +P178||IOB|IO_VREF_1|UNUSED||(0,1)***||||||| +P179||IOB||UNUSED||(0,1)***||||||| +P180||IOB||UNUSED||(0,1)***||||||| +P181||IOB||UNUSED||(0,1)***||||||| +P182||GCLKIOB|GCK2|UNUSED||(0,1)***||||||| +P183|||GND|||||||||| +P184|||VCCO|||0|||||na|| +P185||GCLKIOB|GCK3|UNUSED||0||||||| +P186|||VCCINT||||||||2.5|| +P187||IOB||UNUSED||0||||||| +P188||IOB||UNUSED||0||||||| +P189||IOB|IO_VREF_0|UNUSED||0||||||| +P190|||GND|||||||||| +P191||IOB||UNUSED||0||||||| +P192||IOB||UNUSED||0||||||| +P193||IOB||UNUSED||0||||||| +P194||IOB||UNUSED||0||||||| +P195||IOB||UNUSED||0||||||| +P196|||VCCINT||||||||2.5|| +P197|||VCCO|||0|||||na|| +P198|||GND|||||||||| +P199||IOB||UNUSED||0||||||| +P200||IOB|IO_VREF_0|UNUSED||0||||||| +P201||IOB||UNUSED||0||||||| +P202||IOB||UNUSED||0||||||| +P203||IOB|IO_VREF_0|UNUSED||0||||||| +P204||IOB||UNUSED||0||||||| +P205||IOB|IO_VREF_0|UNUSED||0||||||| +P206||IOB||UNUSED||0||||||| +P207|||TCK|||||||||| +P208|||VCCO|||0|||||na|| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +*** In some smaller packages, the VCCO bank number of a pin may trail + the VREF bank number (VCCO,VREF). + Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt (revision 260) @@ -0,0 +1,69 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+ +
+ + + +
+ + +
+ + + + + +
+
+ + +
+
+ + +
+
+
+
+ + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/__projnav.log =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/__projnav.log (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/__projnav.log (revision 260) @@ -0,0 +1,1282 @@ +ISE Auto-Make Log File +----------------------- + +Updating: Edit Implementation Constraints (Constraints Editor) + +Starting: 'exewrap @__constEditor_exewrap.rsp' + + +Creating TCL Process +Starting: 'constraints_editor btndemo.ucf btndemo.ngd' + + +Tcl c:/xilinx_webpack/data/projnav/constEditor.tcl detected that program 'constraints_editor btndemo.ucf btndemo.ngd' completed successfully. + +call Constraints Editor completed +Starting: 'chkdate' + + +Tcl c:/xilinx_webpack/data/projnav/constEditor.tcl detected that program 'chkdate' completed successfully. + + Existing implementation results have been retained ! + To incorporate your constraint changes, right click on the 'Implement Design' process and select 'Rerun All'. +Done: completed successfully. + +Project Navigator Auto-Make Log File +------------------------------------- + +JHDPARSE - VHDL/Verilog Parser. +ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + +Scanning BtnDemo.vhd +Scanning BtnDemo.vhd +Writing BtnDemo.jhd. + +JHDPARSE complete - 0 errors, 0 warnings. + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + + +Started process "Synthesize". + + +========================================================================= +* HDL Compilation * +========================================================================= +WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was C:/Projects/RefDsgn/D2/BtnDemo/BtnDemo.vhd, now is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd +WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was C:/Projects/RefDsgn/D2/BtnDemo/BtnDemo.vhd, now is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd +Compiling vhdl file F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd in Library work. +Architecture behavioral of Entity btndemo is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= + +Analyzing Entity (Architecture ). +WARNING:Xst:766 - F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd. +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +Library "C:/XilinxISE/data/librtl.xst" Consulted + +Optimizing unit ... + +Mapping all equations... +Loading device for application Xst from file 'v200.nph' in environment C:/XilinxISE. +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200pq208-5 + + Number of bonded IOBs: 2 out of 144 1% + + +========================================================================= +TIMING REPORT + + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.404ns + +========================================================================= + +Completed process "Synthesize". + + + +Started process "Translate". + + +Command Line: ngdbuild -quiet -dd f:\engineering\projects\web5.1\d2\btndemo/_ngo +-uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc +btndemo.ngd + +Reading NGO file "F:/Engineering/Projects/web5.1/D2/BtnDemo/btndemo.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "btndemo.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Writing NGD file "btndemo.ngd" ... + +Writing NGDBUILD log file "btndemo.bld"... + +NGDBUILD done. + +Completed process "Translate". + + + +Started process "Map". + +Using target part "2s200pq208-5". +Removing unused or disabled logic... +Running cover... +Running directed packing... +Running delay-based LUT packing... +Running related packing... + +Design Summary: + Number of errors: 0 + Number of warnings: 1 + Number of Slices containing + unrelated logic: 0 out of 0 0% + Number of bonded IOBs: 1 out of 140 1% + Number of GCLKIOBs: 1 out of 4 25% +Total equivalent gate count for design: 0 +Additional JTAG gate count for IOBs: 96 +Peak Memory Usage: 52 MB + +Mapping completed. +See MAP report file "btndemo_map.mrp" for details. + +Completed process "Map". + +Mapping Module btndemo . . . +MAP command line: +map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +Mapping Module btndemo: DONE + + + +Started process "Place & Route". + +Release 5.1i - Par F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + + + + +Constraints file: btndemo.pcf + +Loading device database for application par from file "btndemo_map.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application par from file 'v200.nph' in environment +C:/XilinxISE. +Device speed data version: PRELIMINARY 1.25 2002-06-19. + + +Resolving physical constraints. +Finished resolving physical constraints. + +Device utilization summary: + + Number of External GCLKIOBs 1 out of 4 25% + Number of External IOBs 1 out of 140 1% + Number of LOCed External IOBs 1 out of 1 100% + + + + + +Overall effort level (-ol): 2 (set by user) +Placer effort level (-pl): 2 (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): 2 (set by user) + + +Phase 1.1 +Phase 1.1 (Checksum:989683) REAL time: 2 secs + +Phase 2.23 +Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs + +Phase 3.3 +Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs + +Phase 4.5 +Phase 4.5 (Checksum:26259fc) REAL time: 2 secs + +Phase 5.8 +Phase 5.8 (Checksum:98996d) REAL time: 2 secs + +Phase 6.5 +Phase 6.5 (Checksum:39386fa) REAL time: 2 secs + +Phase 7.18 +Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs + +Writing design to file btndemo.ncd. + +Total REAL time to placer completion: 2 secs +Total CPU time to placer completion: 1 secs + + +Starting Router REAL time: 2 secs + +Phase 1: 1 unrouted; REAL time: 2 secs + +Phase 2: 1 unrouted; REAL time: 2 secs + +Phase 3: 0 unrouted; REAL time: 2 secs + +Phase 4: 0 unrouted; REAL time: 2 secs + +Finished Router REAL time: 2 secs + +Total REAL time to router completion: 2 secs +Total CPU time to router completion: 1 secs + +Generating "par" statistics. + + +All signals are completely routed. + +Total REAL time to par completion: 7 secs +Total CPU time to par completion: 2 secs + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Writing design to file btndemo.ncd. + + +PAR done. + +Completed process "Place & Route". + + +Started process "Generate Post-Place & Route Static Timing". + + +Loading device database for application trce.exe from file "btndemo.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application trce.exe from file 'v200.nph' in environment +C:/XilinxISE. + +Analysis completed Fri Mar 28 16:52:32 2003 +-------------------------------------------------------------------------------- + +Generating Report ... + + +Completed process "Generate Post-Place & Route Static Timing". + +Place & Route Module btndemo . . . +PAR command line: par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +PAR completed successfully + + + + +Started process "Generate Programming File". + +Release 5.1i - Bitgen F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + +Loading device database for application Bitgen from file "btndemo.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application Bitgen from file 'v200.nph' in environment +C:/XilinxISE. +Opened constraints file btndemo.pcf. + +Fri Mar 28 16:52:34 2003 + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "btndemo.bit". +Bitstream generation is complete. + +Completed process "Generate Programming File". + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Started process "Generate Programming File". + +Release 5.1i - Bitgen F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + +Loading device database for application Bitgen from file "btndemo.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application Bitgen from file 'v200.nph' in environment +C:/XilinxISE. +Opened constraints file btndemo.pcf. + +Mon Mar 31 17:13:29 2003 + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "btndemo.bit". +Bitstream generation is complete. + +Completed process "Generate Programming File". + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + + +Started process "Synthesize". + + +========================================================================= +* HDL Compilation * +========================================================================= +WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd +WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd +Compiling vhdl file E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd in Library work. +Architecture behavioral of Entity btndemo is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= + +Analyzing Entity (Architecture ). +WARNING:Xst:766 - E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd. +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +Library "C:/XilinxISE/data/librtl.xst" Consulted + +Optimizing unit ... + +Mapping all equations... +Loading device for application Xst from file 'v200.nph' in environment C:/XilinxISE. +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200pq208-5 + + Number of bonded IOBs: 2 out of 144 1% + + +========================================================================= +TIMING REPORT + + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.404ns + +========================================================================= + +Completed process "Synthesize". + + + +Started process "Translate". + + +Command Line: ngdbuild -quiet -dd e:\engineering\projects\web5.1\d2\btndemo/_ngo +-uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc +btndemo.ngd + +Reading NGO file "E:/Engineering/Projects/web5.1/D2/BtnDemo/btndemo.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "btndemo.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Writing NGD file "btndemo.ngd" ... + +Writing NGDBUILD log file "btndemo.bld"... + +NGDBUILD done. + +Completed process "Translate". + + + +Started process "Map". + +Using target part "2s200pq208-5". +Removing unused or disabled logic... +Running cover... +Running directed packing... +Running delay-based LUT packing... +Running related packing... + +Design Summary: + Number of errors: 0 + Number of warnings: 1 + Number of Slices containing + unrelated logic: 0 out of 0 0% + Number of bonded IOBs: 1 out of 140 1% + Number of GCLKIOBs: 1 out of 4 25% +Total equivalent gate count for design: 0 +Additional JTAG gate count for IOBs: 96 +Peak Memory Usage: 52 MB + +Mapping completed. +See MAP report file "btndemo_map.mrp" for details. + +Completed process "Map". + +Mapping Module btndemo . . . +MAP command line: +map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +Mapping Module btndemo: DONE + + + +Started process "Place & Route". + +Release 5.1i - Par F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + + + + +Constraints file: btndemo.pcf + +Loading device database for application par from file "btndemo_map.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application par from file 'v200.nph' in environment +C:/XilinxISE. +Device speed data version: PRELIMINARY 1.25 2002-06-19. + + +Resolving physical constraints. +Finished resolving physical constraints. + +Device utilization summary: + + Number of External GCLKIOBs 1 out of 4 25% + Number of External IOBs 1 out of 140 1% + Number of LOCed External IOBs 1 out of 1 100% + + + + + +Overall effort level (-ol): 2 (set by user) +Placer effort level (-pl): 2 (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): 2 (set by user) + + +Phase 1.1 +Phase 1.1 (Checksum:989683) REAL time: 2 secs + +Phase 2.23 +Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs + +Phase 3.3 +Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs + +Phase 4.5 +Phase 4.5 (Checksum:26259fc) REAL time: 2 secs + +Phase 5.8 +Phase 5.8 (Checksum:98996d) REAL time: 2 secs + +Phase 6.5 +Phase 6.5 (Checksum:39386fa) REAL time: 2 secs + +Phase 7.18 +Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs + +Writing design to file btndemo.ncd. + +Total REAL time to placer completion: 3 secs +Total CPU time to placer completion: 1 secs + + +Starting Router REAL time: 3 secs + +Phase 1: 1 unrouted; REAL time: 3 secs + +Phase 2: 1 unrouted; REAL time: 3 secs + +Phase 3: 0 unrouted; REAL time: 3 secs + +Phase 4: 0 unrouted; REAL time: 3 secs + +Finished Router REAL time: 3 secs + +Total REAL time to router completion: 3 secs +Total CPU time to router completion: 1 secs + +Generating "par" statistics. + + +All signals are completely routed. + +Total REAL time to par completion: 6 secs +Total CPU time to par completion: 2 secs + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Writing design to file btndemo.ncd. + + +PAR done. + +Completed process "Place & Route". + + +Started process "Generate Post-Place & Route Static Timing". + + +Loading device database for application trce.exe from file "btndemo.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application trce.exe from file 'v200.nph' in environment +C:/XilinxISE. + +Analysis completed Thu May 29 12:19:52 2003 +-------------------------------------------------------------------------------- + +Generating Report ... + + +Completed process "Generate Post-Place & Route Static Timing". + +Place & Route Module btndemo . . . +PAR command line: par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +PAR completed successfully + + + + +Started process "Generate Programming File". + +Release 5.1i - Bitgen F.23 +Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. + +Loading device database for application Bitgen from file "btndemo.ncd". + "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5 +Loading device for application Bitgen from file 'v200.nph' in environment +C:/XilinxISE. +Opened constraints file btndemo.pcf. + +Thu May 29 12:19:55 2003 + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "btndemo.bit". +Bitstream generation is complete. + +Completed process "Generate Programming File". + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + + +Started process "Synthesize". + + +========================================================================= +* HDL Compilation * +========================================================================= +WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd +WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd +Compiling vhdl file X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd in Library work. +Entity (Architecture ) compiled. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:766 - X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd. +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200pq208-5 + + Number of bonded IOBs: 2 out of 144 1% + + +========================================================================= +TIMING REPORT + + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.404ns + +========================================================================= +Completed process "Synthesize". + + + +Started process "Translate". + + +Command Line: ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo +-uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd + +Reading NGO file "X:/Barron/config/D2/BASIC/BtnDemo/btndemo.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "btndemo.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 39036 kilobytes + +Writing NGD file "btndemo.ngd" ... + +Writing NGDBUILD log file "btndemo.bld"... + +NGDBUILD done. +Completed process "Translate". + + + +Started process "Map". + +Using target part "2s200pq208-5". +Removing unused or disabled logic... +Running cover... +Running directed packing... +Running delay-based LUT packing... +Running related packing... + +Design Summary: +Number of errors: 0 +Number of warnings: 1 +Logic Utilization: +Logic Distribution: + Number of Slices containing only related logic: 0 out of 0 0% + Number of Slices containing unrelated logic: 0 out of 0 0% + *See NOTES below for an explanation of the effects of unrelated logic + Number of bonded IOBs: 1 out of 140 1% + Number of GCLKIOBs: 1 out of 4 25% + +Total equivalent gate count for design: 0 +Additional JTAG gate count for IOBs: 96 +Peak Memory Usage: 61 MB + +NOTES: + + Related logic is defined as being logic that shares connectivity - + e.g. two LUTs are "related" if they share common inputs. + When assembling slices, Map gives priority to combine logic that + is related. Doing so results in the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin + packing unrelated logic into a slice once 99% of the slices are + occupied through related logic packing. + + Note that once logic distribution reaches the 99% level through + related logic packing, this does not mean the device is completely + utilized. Unrelated logic packing will then begin, continuing until + all usable LUTs and FFs are occupied. Depending on your timing + budget, increased levels of unrelated logic packing may adversely + affect the overall timing performance of your design. + + +Mapping completed. +See MAP report file "btndemo_map.mrp" for details. +Completed process "Map". + +Mapping Module btndemo . . . +MAP command line: +map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +Mapping Module btndemo: DONE + + + +Started process "Place & Route". + + + + + +Constraints file: btndemo.pcf + +Loading device database for application Par from file "btndemo_map.ncd". + "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5 +Loading device for application Par from file 'v200.nph' in environment +C:/Xilinx. +Device speed data version: PRODUCTION 1.27 2003-12-13. + + +Resolving physical constraints. +Finished resolving physical constraints. + +Device utilization summary: + + Number of External GCLKIOBs 1 out of 4 25% + Number of External IOBs 1 out of 140 1% + Number of LOCed External IOBs 1 out of 1 100% + + + + + +Overall effort level (-ol): Standard (set by user) +Placer effort level (-pl): Standard (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): Standard (set by user) + + +Phase 1.1 +Phase 1.1 (Checksum:989683) REAL time: 3 secs + +Phase 2.23 +Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs + +Phase 3.3 +Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs + +Phase 4.5 +Phase 4.5 (Checksum:26259fc) REAL time: 3 secs + +Phase 5.8 +Phase 5.8 (Checksum:98996d) REAL time: 4 secs + +Phase 6.5 +Phase 6.5 (Checksum:39386fa) REAL time: 4 secs + +Phase 7.18 +Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs + +Writing design to file btndemo.ncd. + +Total REAL time to Placer completion: 6 secs +Total CPU time to Placer completion: 1 secs + + +Phase 1: 1 unrouted; REAL time: 6 secs + +Phase 2: 1 unrouted; REAL time: 6 secs + +Phase 3: 0 unrouted; REAL time: 6 secs + +Phase 4: 0 unrouted; REAL time: 6 secs + +Total REAL time to Router completion: 7 secs +Total CPU time to Router completion: 2 secs + +Generating "par" statistics. + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 16 secs +Total CPU time to PAR completion: 5 secs + +Peak Memory Usage: 50 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Writing design to file btndemo.ncd. + + +PAR done. +Completed process "Place & Route". + + +Started process "Generate Post-Place & Route Static Timing". + +WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This + generally indicates that there is an inconsistency between versions of the + speed and device data files. Please check to ensure that the XILINX + environment variable is set correctly, if the MYXILINX variable is set, make + sure that it is pointing to patch files that are compatable with the version + of software that the XILINX variable points to. +WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This + generally indicates that there is an inconsistency between versions of the + speed and device data files. Please check to ensure that the XILINX + environment variable is set correctly, if the MYXILINX variable is set, make + sure that it is pointing to patch files that are compatable with the version + of software that the XILINX variable points to. + +Analysis completed Tue Jul 06 17:46:21 2004 +-------------------------------------------------------------------------------- + +Generating Report ... + +Completed process "Generate Post-Place & Route Static Timing". + +Place & Route Module btndemo . . . +PAR command line: par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +PAR completed successfully + + + + +Started process "Generate Programming File". + +Completed process "Generate Programming File". + + + +Project Navigator Auto-Make Log File +------------------------------------- + + + + +Started process "Synthesize". + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd in Library work. +Architecture behavioral of Entity btndemo is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:766 - X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd. +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200pq208-5 + + Number of bonded IOBs: 2 out of 144 1% + + +========================================================================= +TIMING REPORT + + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.404ns + +========================================================================= +Completed process "Synthesize". + + + +Started process "Translate". + + +Command Line: ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo +-uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd + +Reading NGO file "X:/Barron/config/D2/BASIC/BtnDemo/btndemo.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "btndemo.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 39036 kilobytes + +Writing NGD file "btndemo.ngd" ... + +Writing NGDBUILD log file "btndemo.bld"... + +NGDBUILD done. +Completed process "Translate". + + + +Started process "Map". + +Using target part "2s200pq208-5". +Removing unused or disabled logic... +Running cover... +Running directed packing... +Running delay-based LUT packing... +Running related packing... + +Design Summary: +Number of errors: 0 +Number of warnings: 1 +Logic Utilization: +Logic Distribution: + Number of Slices containing only related logic: 0 out of 0 0% + Number of Slices containing unrelated logic: 0 out of 0 0% + *See NOTES below for an explanation of the effects of unrelated logic + Number of bonded IOBs: 1 out of 140 1% + Number of GCLKIOBs: 1 out of 4 25% + +Total equivalent gate count for design: 0 +Additional JTAG gate count for IOBs: 96 +Peak Memory Usage: 61 MB + +NOTES: + + Related logic is defined as being logic that shares connectivity - + e.g. two LUTs are "related" if they share common inputs. + When assembling slices, Map gives priority to combine logic that + is related. Doing so results in the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin + packing unrelated logic into a slice once 99% of the slices are + occupied through related logic packing. + + Note that once logic distribution reaches the 99% level through + related logic packing, this does not mean the device is completely + utilized. Unrelated logic packing will then begin, continuing until + all usable LUTs and FFs are occupied. Depending on your timing + budget, increased levels of unrelated logic packing may adversely + affect the overall timing performance of your design. + + +Mapping completed. +See MAP report file "btndemo_map.mrp" for details. +Completed process "Map". + +Mapping Module btndemo . . . +MAP command line: +map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +Mapping Module btndemo: DONE + + + +Started process "Place & Route". + + + + + +Constraints file: btndemo.pcf + +Loading device database for application Par from file "btndemo_map.ncd". + "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5 +Loading device for application Par from file 'v200.nph' in environment +C:/Xilinx. +Device speed data version: PRODUCTION 1.27 2003-12-13. + + +Resolving physical constraints. +Finished resolving physical constraints. + +Device utilization summary: + + Number of External GCLKIOBs 1 out of 4 25% + Number of External IOBs 1 out of 140 1% + Number of LOCed External IOBs 1 out of 1 100% + + + + + +Overall effort level (-ol): Standard (set by user) +Placer effort level (-pl): Standard (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): Standard (set by user) + + +Phase 1.1 +Phase 1.1 (Checksum:989683) REAL time: 3 secs + +Phase 2.23 +Phase 2.23 (Checksum:1312cfe) REAL time: 4 secs + +Phase 3.3 +Phase 3.3 (Checksum:1c9c37d) REAL time: 4 secs + +Phase 4.5 +Phase 4.5 (Checksum:26259fc) REAL time: 4 secs + +Phase 5.8 +Phase 5.8 (Checksum:98996d) REAL time: 4 secs + +Phase 6.5 +Phase 6.5 (Checksum:39386fa) REAL time: 4 secs + +Phase 7.18 +Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs + +Writing design to file btndemo.ncd. + +Total REAL time to Placer completion: 5 secs +Total CPU time to Placer completion: 1 secs + + +Phase 1: 1 unrouted; REAL time: 5 secs + +Phase 2: 1 unrouted; REAL time: 5 secs + +Phase 3: 0 unrouted; REAL time: 5 secs + +Phase 4: 0 unrouted; REAL time: 5 secs + +Total REAL time to Router completion: 5 secs +Total CPU time to Router completion: 1 secs + +Generating "par" statistics. + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 24 secs +Total CPU time to PAR completion: 5 secs + +Peak Memory Usage: 50 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Writing design to file btndemo.ncd. + + +PAR done. +Completed process "Place & Route". + + +Started process "Generate Post-Place & Route Static Timing". + +WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This + generally indicates that there is an inconsistency between versions of the + speed and device data files. Please check to ensure that the XILINX + environment variable is set correctly, if the MYXILINX variable is set, make + sure that it is pointing to patch files that are compatable with the version + of software that the XILINX variable points to. +WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This + generally indicates that there is an inconsistency between versions of the + speed and device data files. Please check to ensure that the XILINX + environment variable is set correctly, if the MYXILINX variable is set, make + sure that it is pointing to patch files that are compatable with the version + of software that the XILINX variable points to. + +Analysis completed Wed Jul 07 09:50:48 2004 +-------------------------------------------------------------------------------- + +Generating Report ... + +Completed process "Generate Post-Place & Route Static Timing". + +Place & Route Module btndemo . . . +PAR command line: par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +PAR completed successfully + + + + +Started process "Generate Programming File". + +Completed process "Generate Programming File". + + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.jid =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.jid (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.jid (revision 260) @@ -0,0 +1 @@ +. btndemo BtnDemo.vhd e:\engineering\projects\refdsgn\d2\btndemo\BtnDemo.vhd Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0cx3>DsfMofc45LOLOJPQCC?2IYILZJD09J1>OE]OM<7AAHIBCO3>K)?9nT@:5AEUULVN7!1!QWQG&7&8*J_NGF6:ZPPIOE>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk50:z`7v7789'?!ki<21CDu713IJs<7H52;3xW7<6=3<1=>=:19g9736b;rd:?7?4n0692>"6:3;;7p]>:0792?74;<;3i7=90d58`5<7280:w^<51485>454=82n6>8?e29uPg<7280:6>u\2;36>3<6;:?:4h4<61g0?!`==2.j6<74b183>7<52:qCi6*l:19j53<722e:;7>5;cf94?4=83:p(n4;;I32?McN692Bn7d=50;9l52z\22>;c2:1v<950;0xZ41<582146s|1983>7}:l3201<653:~j46=83;pDh5rn0394?7|@l1vb<<50;3xL`=zutwKLNu>6;;1<7661=wKLOu?}ABSxFG \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngd (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$26x4>713-Xnzd}foo8#5+439'8%8-*k;2q2456ao:8;!9=4BTD24>DRAENTXL\HEUCQGM11:G[TDHCMMUB_HQIIMG2?L3JHIMOO;6B@GHABH2=J&>:oSAm4M`hlvScu{`eeo6CfnnpUawungg=0BHZXOSI2?J2PNM^U_U]K>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG9;YQWHLD13QniSDjl;Yfk[Utne]s{ik5Wdi]SvlkQm{ybcc??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmm7>^t|:1ixc=4ldf;?iccWFH^J55age`vmib?3zzj~yoa399{mioip|d:46vcny]bqqiX8Vron"m|t/zaga{GHy;o7MNw5;D90?7|[109o7?7:01014>b2:<;i>ua2`82?k4e2?1/>:4=5:P3?4d2821=>=:19g9736b?2Y::7=?:08276360l08:=kk;R5975<628989<6j:243ac=c=3:1=7?tS981g?7?28989<6j:243a6=#<39:7E74vUc94?7=939p_54=c;3;>454=82n6>8?e29'61<6?2\957s6i3:0q)uG229'64<23`8o6=44o3g94?=e:;0;6?4?:1y'643=#9=0:<6F>3:&21?553`o1<7*=8;33?>i6k3:1(?651d98yg4a29096=4?{%02>4b<@;<0D?=4$3:97>N6;2.:87?j;%36>6454>e:9~f7b=83;1<7>t$3:95c=O::1C=<5+15824>o6n3:1(?651g98yg4b290:6=4?{%0;>4`<@;90D6`<6n2wx>k4?:3y>67<6k279j7k4}|l23?6=9rB9?6G>f;3x5?{zf821<7?tH318M4`=9r81qp`>9;295~N5;2wvqpNOCz3g>=`bk=:8ipNOBz2~DEV|uIJ \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ucf =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ucf (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ucf (revision 260) @@ -0,0 +1,298 @@ +############################################## +# BASIC UCF SYNTAX EXAMPLES V2.1.5 # +############################################## +# +# TIMING SPECIFICATIONS +# +# Timing specifications can be applied to the entire device (global) or to +# specific groups of login in your PLD design (called "time groups'). +# The time groups are declared in two basic ways. +# +# Method 1: Based on a net name, where 'my_net' is a net that touchs all the +# logic to be grouped in to 'logic_grp'. Example: +#NET my_net TNM_NET = logic_grp ; +# +# Method 2: Group uing the key word 'TIMEGRP' and declare using the names of +# logic in your design. Example: +#TIMEGRP group_name = FFS ("U1/*"); +# creates a group called 'group_name' for all flip-flops with in +# the hierarchical block called U1. Wildcards are valid. +# +# Grouping is very important because it lets you tell the software which parts +# of a design run at which speeds. For the majority of the designs with only +# one clock the very simple global constraints. +# +# The type of grouping constraint you use can vary depending on the synthesis +# tools you are using. For example, Synplicity does well with Method 1, while +# FPGA Express does beter with Method 2. +# +# +############################################################ +# Internal to the device clock speed specifications - Tsys # +############################################################ +# +# data _________ /^^^^^\ _________ out +# ----------| D Q |-----{ LOGIC } -----| D Q |------ +# | | \vvvvv/ | | +# ---|> CLK | ---|> CLK | +# clock | --------- | --------- +# ------------------------------------ +# +# --------------- +# Single Clock +# --------------- +# +# ---------------- +# PERIOD TIME-SPEC +# ---------------- +# The PERIOD spec. covers all timing paths that start or end at a +# register, latch, or synchronous RAM which are clocked by the reference +# net (excluding pad destinations). Also covered is the setup +# requirement of the synchronous element relative to other elements +# (ex. flip flops, pads, etc...). +# NOTE: The default unit for time is nanoseconds. +# +#NET clock PERIOD = 50ns ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +# FROM:TO style timespecs can be used to constrain paths between time +# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined +# time groups used to specify all elements of each type in a design. +#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS +#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS +#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge +#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge +#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge +# +# --------------- +# Multiple Clocks +# --------------- +# Requires a combination of the 'Period' and 'FROM:TO' type time specifications +#NET clock1 TNM_NET = clk1_grp ; +#NET clock2 TNM_NET = clk2_grp ; +# +#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ; +#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ; +#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ; +#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ; +# +# +############################################################ +# CLOCK TO OUT specifications - Tco # +############################################################ +# +# from _________ /^^^^^\ --------\ +# ----------| D Q |-----{ LOGIC } -----| Pad > +# PLD | | \vvvvv/ --------/ +# ---|> CLK | +# clock | --------- +# -------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically include clock buffer/routing delay in your +# clock-to-out timing specifications, use OFFSET constraints . +# For an output where the maximum clock-to-out (Tco) is 25 ns: +#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns; +# Note that FROM: FFS : TO: PADS constraints start the delay analysis +# at the flip flop itself, and not the clock input pin. The recommended +# method to create a clock-to-out constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Flip-Flop speed specifications - Tsu # +############################################################ +# +# ------\ /^^^^^\ _________ into PLD +# |pad >-------{ LOGIC } -----| D Q |------ +# ------/ \vvvvv/ | | +# ---|> CLK | +# clock | --------- +# ---------------------------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically account for clock delay in your input setup timing +# specifications, use OFFSET constraints. +# For an input where the maximum setup time is 25 ns: +#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns; +# Note that FROM: PADS : TO: FFS constraints do not take into account any +# delay for the clock path. The recommended method to create an input +# setup time constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Pad speed specifications - Tpd # +############################################################ +# +# ------\ /^^^^^\ -------\ +# |pad >-------{ LOGIC } -----| pad > +# ------/ \vvvvv/ -------/ +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns; +# +# +############################################################ +# Other timing specifications # +############################################################ +# +# ------------- +# TIMING IGNORE +# ------------- +# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The +# "*" character is a wild-card which can be used for bus names. A "?" +# character can be used to wild-card one character. +# Ignore timing of net reset_n: +#NET : reset_n : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem: +#NET : mux_mem/data_reg* : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC +# named TS01 only: +#NET : mux_mem/data_reg* : TIG = TS01 ; +# +# Ignore data1_sig and data2_sig nets: +#NET : data?_sig : TIG ; +# +# --------------- +# PATH EXCEPTIONS +# --------------- +# If your design has outputs that can be slower than others, you can +# create specific timespecs similar to this example for output nets +# named out_data(7:0) and irq_n: +#TIMEGRP slow_outs = PADS(out_data* : irq_n) ; +#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ; +#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ; +#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ; +# +# If you have multi-cycle FF to FF paths, you can create a time group +# using either the TIMEGRP or TNM statements. +# +# WARNING: Many VHDL/verilog synthesizers do not predictably name flip +# flop Q output nets. Most synthesizers do assign predictable instance +# names to flip flops, however. +# +# TIMEGRP example: +#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* : +#inst_path/ff_q_output_net2*); +# +# TNM attached to instance example: +#INST inst_path/ff_instance_name1_reg* TNM = slowffs ; +#INST inst_path/ff_instance_name2_reg* TNM = slowffs ; +# +# If a FF clock-enable is used on all flip flops of a multi-cycle path, +# you can attach TNM to the clock enable net. NOTE: TNM attached to a +# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the +# net. +#NET ff_clock_enable_net TNM = slowffs ; +# +# Example of using "slowffs" timegroup, in a FROM:TO timespec, with +# either of the three timegroup methods shown above: +#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ; +# +# Constrain the skew or delay associate with a net. +#NET any_net_name MAXSKEW = 7 ; +#NET any_net_name MAXDELAY = 20 ns; +# +# +# Constraint priority in your .ucf file is as follows: +# +# highest 1. Timing Ignore (TIG) +# 2. FROM : THRU : TO specs +# 3. FROM : TO specs +# lowest 4. PERIOD specs +# +# See the on-line "Library Reference Guide" document for +# additional timespec features and more information. +# +# +############################################################ +# # +# LOCATION and ATTRIBUTE SPECIFICATIONS # +# # +############################################################ +# Pin and CLB location locking constraints # +############################################################ +# +# ----------------------- +# Assign an IO pin number +# ----------------------- +#INST io_buf_instance_name LOC = P110 ; +#NET io_net_name LOC = P111 ; +# +# ----------------------- +# Assign a signal to a range of I/O pins +# ----------------------- +#NET "signal_name" LOC=P32, P33, P34; +# +# ----------------------- +# Place a logic element(called a BEL) in a specific CLB location. BEL = FF, LUT, RAM, etc... +# ----------------------- +#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ; +# +# ----------------------- +# Place CLB in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Place Heirarchial logic block in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1* LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Prohibit IO pin P26 or CLBR5C3 from being used: +# ----------------------- +#CONFIG PROHIBIT = P26 ; +#CONFIG PROHIBIT = CLB_R5C3 ; +# Config Prohibit is very important for frocing the software to not use critical +# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG +# Pins require a special pad so they will not be availabe to this constraint +# +# ----------------------- +# Assign an OBUF to be FAST or SLOW: +# ----------------------- +#INST obuf_instance_name FAST ; +#INST obuf_instance_name SLOW ; +# +# ----------------------- +# FPGAs only: IOB input Flip-flop delay specifcation +# ----------------------- +# Declare an IOB input FF delay (default = MAXDELAY). +# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed +# into an IOB by the "map -pr i" option. +#INST input_ff_instance_name MEDDELAY ; +#INST input_ff_instance_name NODELAY ; +# +# ----------------------- +# Assign Global Clock Buffers Lower Left Right Side +# ----------------------- +# INST gbuf1 LOC=SSW +# +# # +NET "btn" LOC = "P77"; +NET "led" LOC = "P71"; Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.stx =================================================================== Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bit =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bit (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bit (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_summary.html =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_summary.html (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_summary.html (revision 260) @@ -0,0 +1,86 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BtnDemo Project Status
Project File:BtnDemo.xiseParser Errors: No Errors
Module Name:BtnDemoImplementation State:Mapped
Target Device:xc3s1000-4fg320
  • Errors:
 +X +1 Error (1 new)
Product Version:ISE 12.3
  • Warnings:
1 Warning (1 new)
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
  
+ + + + 
+ +
Device Utilization Summary [-]
+ + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentmié abr 30 19:14:15 201401 Warning (1 new)1 Info (1 new)
Translation ReportCurrentmié abr 30 19:14:23 2014000
Map ReportCurrentmié abr 30 19:14:28 2014X 1 Error (1 new)00
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 04/30/2014 - 19:48:37
+ must be placed at site P71. +Resolved that GCLKIOB must be placed at site P77. + + +Device utilization summary: + + Number of External GCLKIOBs 1 out of 4 25% + Number of External IOBs 1 out of 140 1% + Number of LOCed External IOBs 1 out of 1 100% + + + + + +Overall effort level (-ol): Standard (set by user) +Placer effort level (-pl): Standard (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): Standard (set by user) + + +Phase 1.1 +Phase 1.1 (Checksum:989683) REAL time: 3 secs + +Phase 2.23 +Phase 2.23 (Checksum:1312cfe) REAL time: 4 secs + +Phase 3.3 +Phase 3.3 (Checksum:1c9c37d) REAL time: 4 secs + +Phase 4.5 +Phase 4.5 (Checksum:26259fc) REAL time: 4 secs + +Phase 5.8 +Phase 5.8 (Checksum:98996d) REAL time: 4 secs + +Phase 6.5 +Phase 6.5 (Checksum:39386fa) REAL time: 4 secs + +Phase 7.18 +Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs + +Writing design to file btndemo.ncd. + +Total REAL time to Placer completion: 5 secs +Total CPU time to Placer completion: 1 secs + + +Phase 1: 1 unrouted; REAL time: 5 secs + +Phase 2: 1 unrouted; REAL time: 5 secs + +Phase 3: 0 unrouted; REAL time: 5 secs + +Phase 4: 0 unrouted; REAL time: 5 secs + +Total REAL time to Router completion: 5 secs +Total CPU time to Router completion: 1 secs + +Generating "par" statistics. + + + The Delay Summary Report + + The SCORE FOR THIS DESIGN is: 100 + + +The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 + + The AVERAGE CONNECTION DELAY for this design is: 0.935 + The MAXIMUM PIN DELAY IS: 0.935 + The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.312 + + Listing Pin Delays by value: (nsec) + + d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 + --------- --------- --------- --------- --------- --------- + 1 0 0 0 0 0 + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 24 secs +Total CPU time to PAR completion: 5 secs + +Peak Memory Usage: 50 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Writing design to file btndemo.ncd. + + +PAR done. Index: phr/trunk/codigo/demos/projects/BtnDemo/d2but.cdf =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/d2but.cdf (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/d2but.cdf (revision 260) @@ -0,0 +1,16 @@ +JedecChain; +FileRevision(JESDxxA); +/* NoviceMode */ +/* Active Mode BS */ +/* Mode BS */ +/* Cable Parallel lpt1 */ + P ActionCode(Cfg) + Device + PartName(xc2s200) + File("E:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit") + ; +/* Mode SS */ +/* Mode SM */ +/* Mode BSFILE */ +/* Mode HW140 */ +ChainEnd; Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngr (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0ax0f=(`fgn#aizaow`k*iwmgid~h} pip,pwsic&idhdi`/egnkv)wzf`noy} BulGahi(J}dOi`a!vifg?6u689:mk>;H78MGSAO>1GCJGLAM58I+17lVF:7B:4P@PW7>TSD=1_U]K=;T3:?SOB_V^R\H?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED?j;YQW[LKWDLGNBYO[INL\GJHT\[KBBY]>0:ZPPZTSDVZYC]K]TX48\adXAm;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaa3:Zpp<=_{}MFcikc3:`wj6=kmml0b{}cd]emiciidoo7~azrbg\hlhbfk;;7um3L1>7?tS5821?>=9:9>=5k5372f7~h6;3;0b<:56:&26?`b2:<;i:5k2;295?7|[=0:976512165=c=;?:n?6xIb;295?7=8rY?6<;58;30707?m39=5<5290;wA?>:3ym5d<3>2.:57>4}%a92>o22900c44?::p52<72;qU=:52d;78yv7?2909wS?7;{zutwKLNu>2;;5b3?amtJKNv>r@ARxyEF \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo._prj =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo._prj (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo._prj (revision 260) @@ -0,0 +1,2 @@ +plslib +pls BtnDemo.vhd Index: phr/trunk/codigo/demos/projects/BtnDemo/_ngo/netlist.lst =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_ngo/netlist.lst (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_ngo/netlist.lst (revision 260) @@ -0,0 +1,2 @@ +/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc 1398896055 +OK Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_xst.xrpt =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_xst.xrpt (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_xst.xrpt (revision 260) @@ -0,0 +1,137 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ +
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+ + + + +
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+ + + +
+ + + Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_envsettings.html =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_envsettings.html (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_envsettings.html (revision 260) @@ -0,0 +1,391 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin/opt/Xilinx/12.3/ISE_DS/ISE//lib/lin< data not available >< data not available >
PATH/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/games:
/usr/games		/opt/Xilinx/12.3/ISE_DS/ISE//bin/lin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/games:
/usr/games		< data not available >< data not available >
XILINX/opt/Xilinx/12.3/ISE_DS/ISE//opt/Xilinx/12.3/ISE_DS/ISE/< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn BtnDemo.prj 
-ifmt mixedMIXED
-ofn BtnDemo 
-ofmt NGCNGC
-p xc3s1000-4-fg320 
-top BtnDemo 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyNoNO
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style AutoAUTO
-iobuf YESYES
-max_fanout 500500
-bufg 88
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc3s1000-fg320-4None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedAMD Athlon(tm) II X2 255 Processor/3100.000 MHzAMD Athlon(tm) II X2 255 Processor/3100.000 MHz<  data not available  ><  data not available  >
Hostcudar75cudar75<  data not available  ><  data not available  >
OS NameDebianDebian<  data not available  ><  data not available  >
OS ReleaseDebian GNU/Linux 7.4 (wheezy)Debian GNU/Linux 7.4 (wheezy)<  data not available  ><  data not available  >
+ \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.lso =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.lso (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.lso (revision 260) @@ -0,0 +1 @@ +work Index: phr/trunk/codigo/demos/projects/BtnDemo/webtalk_pn.xml =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/webtalk_pn.xml (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/webtalk_pn.xml (revision 260) @@ -0,0 +1,43 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.bld =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.bld (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.bld (revision 260) @@ -0,0 +1,36 @@ +Release 12.3 ngdbuild M.70d (lin) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle +ise -dd _ngo -nt timestamp -i -p xc3s1000-fg320-4 BtnDemo.ngc BtnDemo.ngd + +Reading NGO file +"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc" +... +Gathering constraint information from source properties... +Done. + +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 84120 kilobytes + +Writing NGD file "BtnDemo.ngd" ... +Total REAL time to NGDBUILD completion: 4 sec +Total CPU time to NGDBUILD completion: 2 sec + +Writing NGDBUILD log file "BtnDemo.bld"... Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.cmd_log =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.cmd_log (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.cmd_log (revision 260) @@ -0,0 +1,3 @@ +xst -intstyle ise -ifn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xst" -ofn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-fg320-4 BtnDemo.ngc BtnDemo.ngd +map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off -c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf Index: phr/trunk/codigo/demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xise =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xise (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xise (revision 260) @@ -0,0 +1,334 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/bitgen.ut =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/bitgen.ut (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/bitgen.ut (revision 260) @@ -0,0 +1,30 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:JtagClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.drc =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.drc (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.drc (revision 260) @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.map =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.map (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.map (revision 260) @@ -0,0 +1,54 @@ +Release 12.3 Map M.70d (lin) +Xilinx Map Application Log File for Design 'BtnDemo' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off +-c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf +Target Device : xc3s1000 +Target Package : fg320 +Target Speed : -4 +Mapper Version : spartan3 -- $Revision: 1.52 $ +Mapped Date : Wed Apr 30 19:14:28 2014 + +vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. +INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set. +INFO:Security:54 - 'xc3s1000' is a WebPack part. +INFO:Security:68 - Please run the Xilinx License Configuration Manager + (xlcm or "Manage Xilinx Licenses") + to assist in obtaining a license. +WARNING:Security:43 - No license file was found in the standard Xilinx license +directory. +WARNING:Security:44 - No license file was found. + Please run the Xilinx License Configuration Manager + (xlcm or "Manage Xilinx Licenses") + to assist in obtaining a license. +ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part +'xc3s1000'. +---------------------------------------------------------------------- +No such feature exists. +Feature: WebPack +License path: +/home/lguanuco/.Xilinx/*.lic:/opt/Xilinx/12.3/ISE_DS/ISE//data/*.lic:/opt/Xilinx +/12.3/ISE_DS/ISE//coregen/core_licenses/Xilinx.lic:/opt/Xilinx/12.3/ISE_DS/ISE// +coregen/core_licenses/XilinxFree.lic: +FLEXnet Licensing error:-5,357. System Error: 2 "No such file or directory" +For further information, refer to the FLEXnet Licensing documentation, +available at "www.acresso.com".No such feature exists. +Feature: ISE +License path: +/home/lguanuco/.Xilinx/*.lic:/opt/Xilinx/12.3/ISE_DS/ISE//data/*.lic:/opt/Xilinx +/12.3/ISE_DS/ISE//coregen/core_licenses/Xilinx.lic:/opt/Xilinx/12.3/ISE_DS/ISE// +coregen/core_licenses/XilinxFree.lic: +FLEXnet Licensing error:-5,357 +For further information, refer to the FLEXnet Licensing documentation, +available at "www.acresso.com". +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +ERROR:Map:258 - A problem was encountered attempting to get the license for this + architecture. + +Design Summary +-------------- +Number of errors : 1 +Number of warnings : 0 Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.dhp =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.dhp (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.dhp (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$2dx4>763-Xnzd}foo8#5+72(-k0==661733=<>DsfMofc#xgd,1:?FIJE@^_II94CSGBP@B?3Jef|D`|t`9Fjqosq@dxxl5Jnukw}Kgjmk1MeakKeqgm`v>Wriecmeh|9;Rgqr`ue3]oxx[kltnppf>RhxOcgiAg|t99VjlrIidoo7X}jSucwahci|z;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@<0TilPIe33?]bjWDkacXjrrklj4665d8wqbXdfmboRo}iuj26>uslVfdkdmPuoqjckcc:2:96{>-026?pub%C<328qXm7=9:08274ed8:0:=;ltn3795>h5>380(?:5229~W<<4>3;1=>?lc11957003Z;>6>851;305fe7;3838>?4S8802?7=9:;ho==5296ef>b4>3:1=7?tS`802?7=9:;ho==5104a?k552h1D>=4?;N33>5=qN>0;6<4>:1yPe?51280:?3<7sg9>6<5a5;38K4c=82.:57>4$g85?!76291/=n4?;%3a>7=Hm3:0C<<50:M00?7|uk9:6=4?:183k522olmjkhif:l6>7673F;n6=5@2380xI603:0qo=l:183>5<7sg9>6<84n48245=H9l0;7)?8:228 4g=;>1/=i4=7:M1g?61=vs@1282x{e;m0;6=4?:1ym70<6?2d>6<>?;N3f>5=#9>08<6*>a;1;?!7c2;=0C?m50:M00?7|uF;865<7290;wc=::0:8j0<6891D=h4?;%34>66<,8k1?45+1e813>I5k3:0C>:51zL56<6stwi>h4?:183>5}i;<0:m6`::39L5`<73-n1>i5@4;28K62=9rwD=>4>{|a6<<7290:6=ua34815>h22=1D=h4?;%196==#9o0;7)j52e9Lf?65<7290;wc=::548j0"5938m7B7?j;N34>g=H910:<6A>c;`8K4b=991D><4m;N01>46h4=8:M07?d1>55r@A \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.syr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.syr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.syr (revision 260) @@ -0,0 +1,283 @@ +Release 12.3 - xst M.70d (lin) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> +Reading design: BtnDemo.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "BtnDemo.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "BtnDemo" +Output Format : NGC +Target Device : xc3s1000-4-fg320 + +---- Source Options +Top Module Name : BtnDemo +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 8 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for entity in library (architecture ). + +INFO:Xst:2555 - '-hierarchy_separator' switch is being deprecated in a future release. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity in library (Architecture ). +WARNING:Xst:2211 - "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" line 70: Instantiating black box module . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd". +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block BtnDemo, actual ratio is 0. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Found no macro +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : BtnDemo.ngr +Top Level Output File Name : BtnDemo +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : No + +Design Statistics +# IOs : 2 + +Cell Usage : +# IO Buffers : 2 +# IBUFG : 1 +# OBUF : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 3s1000fg320-4 + + Number of Slices: 0 out of 7680 0% + Number of IOs: 2 + Number of bonded IOBs: 2 out of 221 0% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -4 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 7.667ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Delay: 7.667ns (Levels of Logic = 2) + Source: btn (PAD) + Destination: led (PAD) + + Data Path: btn to led + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUFG:I->O 1 1.222 0.801 U1 (led_OBUF) + OBUF:I->O 5.644 led_OBUF (led) + ---------------------------------------- + Total 7.667ns (6.866ns logic, 0.801ns route) + (89.6% logic, 10.4% route) + +========================================================================= + + +Total REAL time to Xst completion: 8.00 secs +Total CPU time to Xst completion: 3.66 secs + +--> + + +Total memory usage is 147212 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1 ( 0 filtered) +Number of infos : 1 ( 0 filtered) + Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xst =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xst (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xst (revision 260) @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn BtnDemo.prj +-ifmt mixed +-ofn BtnDemo +-ofmt NGC +-p xc3s1000-4-fg320 +-top BtnDemo +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator _ +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.sprj =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.sprj (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.sprj (revision 260) @@ -0,0 +1 @@ +work BtnDemo.vhd Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd (revision 260) @@ -0,0 +1,79 @@ +------------------------------------------------------------------------ +-- BtnDemo.vhd -- Demonstrate D2 On-Board Button and LED +------------------------------------------------------------------------ +-- Author: Gene Apperson +-- Copyright 2002 Digilent, Inc. +------------------------------------------------------------------------ +-- This module is an example to demonstrate the use of the on-board +-- button and LED on the D2 board. +-- +-- Inputs: +-- btn - button on the D2 board +-- +-- Outputs: +-- led - discrete LED on the D2 board +-- +------------------------------------------------------------------------ +-- Revision History: +-- 03/31/2002(GeneA): created +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity BtnDemo is + Port ( + btn : in std_logic; + led : out std_logic + ); +end BtnDemo; + +architecture Behavioral of BtnDemo is + + ------------------------------------------------------------------------ + -- Component Declarations + ------------------------------------------------------------------------ + + -- System Library Components + + component IBUFG + port ( + I : in STD_LOGIC; + O : out std_logic + ); + end component; + + ------------------------------------------------------------------------ + -- Signal Declarations + ------------------------------------------------------------------------ + + signal bnbuf: std_logic; + + ------------------------------------------------------------------------ + -- Module Implementation + ------------------------------------------------------------------------ + +begin + + -- Instantiate an IBUFG for the button. The button on the D2 board is + -- connected to a global clock input. The Xilinx ISE tools will + -- automatically insert input and output buffers to connect the signal + -- defined in the VHDL modules port. However, for non-clock signals, the + -- tool will automatically try to insert an IBUF. This will generate an + -- errror, as it isn't possible to instantiate an IBUF on a global clock + -- line. To prevent this error, it is necessary to manually instantiate + -- a clock input buffer for this line. The output of this buffer can then + -- be used as a normal logic signal. + +U1: IBUFG port map (I => btn, O => bnbuf); + + -- Connect the D2 button to the D2 LED. The button on the D2 + -- is wired to generate a logic 1 when it is pressed. The LED on the + -- D2 will illuminate when it is driven with a logic 1. + led <= bnbuf; + + ------------------------------------------------------------------------ + +end Behavioral; Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.gise =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.gise (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.gise (revision 260) @@ -0,0 +1,117 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdpdeps.ref =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdpdeps.ref (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdpdeps.ref (revision 260) @@ -0,0 +1,9 @@ +V3 4 +FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd 2004/07/06.17:44:56 M.70d +EN work/BtnDemo 1398896049 \ + FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd \ + PB ieee/std_logic_1164 1284609568 PB ieee/std_logic_arith 1284609569 \ + PB ieee/STD_LOGIC_UNSIGNED 1284609570 +AR work/BtnDemo/Behavioral 1398896050 \ + FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd \ + EN work/BtnDemo 1398896049 CP IBUFG Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdllib.ref =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdllib.ref (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/xst/work/hdllib.ref (revision 260) @@ -0,0 +1,2 @@ +EN btndemo NULL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd sub00/vhpl00 1398896049 +AR btndemo behavioral /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd sub00/vhpl01 1398896050 Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ptf =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ptf (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ptf (revision 260) @@ -0,0 +1,4 @@ +[btndemo] +Design Entry Utilities=true +Generate Programming File=true +User Constraints=true Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.prj =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.prj (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.prj (revision 260) @@ -0,0 +1 @@ +vhdl work BtnDemo.vhd Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ncd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ncd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ncd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ncd (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ncd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bgn =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bgn (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bgn (revision 260) @@ -0,0 +1,103 @@ +Release 6.2.03i - Bitgen G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Loading device database for application Bitgen from file "btndemo.ncd". + "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5 +Loading device for application Bitgen from file 'v200.nph' in environment +C:/Xilinx. +Opened constraints file btndemo.pcf. + +Wed Jul 07 09:50:55 2004 + +C:/Xilinx/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:JtagClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No btndemo.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 4** | ++----------------------+----------------------+ +| StartupClk | JtagClk | ++----------------------+----------------------+ +| CclkPin | Pullup** | ++----------------------+----------------------+ +| DonePin | Pullup** | ++----------------------+----------------------+ +| M0Pin | Pullup** | ++----------------------+----------------------+ +| M1Pin | Pullup** | ++----------------------+----------------------+ +| M2Pin | Pullup** | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GSR_cycle | 6** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | No** | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| Gclkdel0 | 11111** | ++----------------------+----------------------+ +| Gclkdel1 | 11111** | ++----------------------+----------------------+ +| Gclkdel2 | 11111** | ++----------------------+----------------------+ +| Gclkdel3 | 11111** | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| ActivateGclk | No* | ++----------------------+----------------------+ +| PartialMask0 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask1 | (Not Specified)* | ++----------------------+----------------------+ +| PartialGclk | (Not Specified)* | ++----------------------+----------------------+ +| PartialLeft | (Not Specified)* | ++----------------------+----------------------+ +| PartialRight | (Not Specified)* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "btndemo.bit". +Bitstream generation is complete. Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngc =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngc (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngc (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$0cx=>EHEDC_XHJ8;BPFEQCC=2M%?;H78MGSAO>1GCJGLAM58J@RPG[A:7B:4OCWE0>VFZ]<0_B[]CD68P\VB:2_:o6[\ES]UMVOEDL30ZDKX_U[SA4b{R3951<5289:on><:3:713}i9;0:7c?<:39'544;09567dk991>5::6:&f>0=#13;27o?9:181>7<4s-h1=;5Gd:k21?6=3f;<6=44bb83>7<729q/n7:4He9K55=n;3:17b950;9~f4>=8381<7>t$c8;?Mb<@8:0e>4?::m4>5<6=4={_36?8e=;2wx=54?:3y>g?1<5821?6s|1683>7}Y9>16=548;|m55<728qCh6sa1083>4}Ol2we=?4?:0yK`>{zutJKOv?9:cag7<04itJKNv>r@ARxyEF \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngd (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$26x50=#Zl|bdaa:!3-=5(3&:*/o6<|212su76?%<90NXH>0:@VMIBX\HXLIYO]CI78GNDRN01HC@CFTUGG3>EUMH^NHh5KRB]PQFEB[ZL^@55JXQCM@@B?3OXDAR[LF49D*67f92C>7DLZFF08MK>2CDXT^J7:NJFWGUQ?1GCLJJD29OKF1I33FH^J>5@UU18T2743Y=3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK<0TilPIea8\anXX{cfXt~jf:ZglZVuad\n~~g`n028\akXEh`d~[k}shmm55=_ldUFeca}Vdppmjh43Qy?6l{n69apkbbef90`hj7;mgg[JDRN11ekilzimf;?vvfz}ke>k5wc3q145+2%y{9<564xhnjj}siuIJ{=i5O@y0g>C<328qX:74=i:h097)<9:368yV3=:k0j6<=>cb20>7>3=>1X=?4<0;29567dk991>5::c:Q6>66=83;8=nm?3;0;0=?7d=i3;8=nm?3;0;000<,:08=6F8;wV;>5<62808w^852c8b>456kj:86?6;579'66<6<2\947s6>3:0q)?j:09a6a<72;0?6>u+2181`>N5:2c9o7>5;n0f>5<6F=5:&13?2<,8:1h6Fi;%32>65=83.9;7?n;:a6c<72;0;6=u+2182=>N5:2B996*=7;08Lc=#990:m6*>1;10?ld=83.9;7j4;n3;>5<#:>0:m65rb3a94?7=83:p(?951e9K67=Om2.:<7j4$0195f=n9m0;6)<8:0f8?xd5m3:1=7>50z&13?7c3A897Ek4$0295d=#9:0:n6a>d;29 71=9m10q~{t:o0;6?u22082<>;5n3h0q~{I01?L7c28q:6pT6:0y27?{zf821<7?tH308yk7>290:wE<=;H3g>4}52tP263;~yx{GHJq:h7:l092f<7{GHKq;qMN_{|BC \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pcf =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pcf (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.pcf (revision 260) @@ -0,0 +1,5 @@ +SCHEMATIC START ; +// created by map version G.31a on Wed Jul 07 09:50:09 2004 +COMP "led" LOCATE = SITE "P71" LEVEL 1; +COMP "btn" LOCATE = SITE "P77" LEVEL 1; +SCHEMATIC END ; Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.stx =================================================================== Index: phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr (revision 260) @@ -0,0 +1,63 @@ + + + + + + + + + 2 + + + BtnDemo - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000147000000020000000000000000000000000000000064ffffffff000000810000000000000002000001470000000100000000000000000000000100000000 + false + BtnDemo - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd) + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + Implement Design + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000 + false + Implement Design + + + + 1 + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000039f000000040101000100000000000000000000000064ffffffff0000008100000000000000040000007400000001000000000000005c00000001000000000000008400000001000000000000024b0000000100000000 + false + BtnDemo.vhd + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000124000000010001000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000 + false + work + + 000000ff0000000000000002000001440000011d01000000060100000002 + Implementation + Index: phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.xreport =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.xreport (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.xreport (revision 260) @@ -0,0 +1,217 @@ + + +
+ 2014-04-30T19:48:38 + BtnDemo + Unknown + /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.xreport + /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/ + 2014-04-30T19:13:54 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngm =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngm (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngm (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$40x50=#Zl|bdaa:!3-53(?&8*/=85+Rdtjwlii2);%5= ;.2"'g>4t:9:{}?>7-418FP@682H^EAJPT@PDAQGUKA?0OFLZF89@KHKN\]OO;6M]E@VF@`=CZJUXYNMJSRDVH==BPYKEHHJ;;GPBCg=AZHMHC[K]EEc8BWG@WKKXIIo4FSCD[FIRF]20J_AB_TAE55=AzhmGeo ctm8JTDB682LymjBfb/nwh?IE]O;;7K|ngMka*irk2FZJH<64FscdHld)d}f1T[EPGBNHMGSA=2M%?4:EFJ@TF\LN+\B][-GNJJQ753NOEI_O[EE"SKVR*O:::7D;4ICWEC7=NF11BBKK]RDF5?LIDGDZ=7DA[YQG7?LVFL>1GEO\NRX48HJGCMM90@BM8;MMDMFGK02FoaRZvpd`8IDVBPYKEHHJ9;LCST@Bf3DK[S@AKUMGg?HGWW]CFI^ZNMQ`8IDVX^LXXEB@l;LcikwPbzzcdbn5BiomqR`ttafd<7CK[WNPH5>I33FH^J95@P@F0?JSS;2Z<=>5_7618TDB33YKYX55_HXQJGDJ>3ZCLSNAZNU18WKM13ZE^^NK<;RP@b>RFZNO_S]O]TU[SA1=SQYO97X?l;TQFVZPN[@HGI45YIDU\P\VB9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGMc:ZUOZADDBCIYK84Xe`\Mac^c`VZye`Zvpdd8\anXX{cfZh||inl4?]boW]kln6Vkm^@jjaoio8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`<;Yqw7>dsf>1ixcjjmn18h`b?3eooSBLZF29neu>0?47?<:012gf642;2?9;ua4782?k202;1/?k4?lc1196=22?2Y:i7:j:08274ed8:0949;l;R490`<6289:on><:3:7<<=T9l0?h7>5123`g55=:1>3h6]=3;6g>45=9:;ho==5296;b>U12=n1<7?<1ba37?4?<1l0h9o50;396~U02=21=>4>30a`46<50=?=7):54g9K<>h5=3>;in<6be9'61<3n2.9:7?<;wV16?6=93;1?v]8:5:956<6;8ih<>4=8575?!5e2;:0Z9=52zw13?7<};21<6s+3081?g2f2909694<{%1;>1g<@:k0b9:50:k7=?6=3f>i6=44b2;95?4=83:p(>65169K7d=O;m1/8?4:;%3a>4><@8k0(=h:h0:6):=:3f8?xd3k3;1>7>50z&06=O9h1/=o4=d:&2`?363g>?6?5f1782>!2528207bf;0e?k232:1b?=4>:%61>66<3th?n7?51;294~"3:39;7E=n;I3:?!7e2;n0(=z{=31<7=t^5;896?=9?16844<0:p0f<72;q6?44=a:?7g?713ty?n7>53z\7f>;3k38j70:m:228yxh6i3:1=vFc;295~N4i2C8<7?t2;Ya?7|9o0vb9:52:~rQd=83;1=7=tS687`?6=9:;ho==5296;a>"4j3997)=>:39K51=O9<1i8l4?:387>6}Ok2.8;7<4ne87?k542:1e894?;h6:>5<7<729q/?54=:k1/=o4=d:Jb?k232;1/><4>0:k22?7=3f8j6<44}c6:>4<6290;w)=7:0a8 4d=911/=k4=f:Jb?k232:1/><4i;n15>4<i6<4>:183!5?2;i0(602;k019m5179~w1d=839p19m52`9>0g<4<2T?n6srn3d94?7|f=>1<6sa3183>4}i<=0:7p`<1;295~h3<380qpsr@AAx70<>::o=597r@A@x55}383:1<7<524824>{|<80;6=4=:34954=zs=;1<7>52;04>44;6=4?:38150;096<<6<2wp8<4?:181>7g=9<1vw9>50;296?4e28<0qv:>:183>7<5k3;<7pu;0;294?4=:m0:46st4083>5<52;o1=45r}ABSxFG \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ngr (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$0cx=>EHEDC_XHJ8;BPFEQCC=2M%?;H78MGSAO>1GCJGLAM38K1=WI[^87_ZC4:VZT@4<]830ZDKX_U[SA7b7}ABs57=GHq;>6K4=:0yP5?742;0:?3;09567dk991>5::4:f21?6=93;p_<4>3;09567dk991>5::3:tE:0196?749ji;?7<74418 g<23k;>6=4=:081!?=9<1Gi7?t$682=>{Kn3;p(<95c:j51<722e::7>5;cc94?4=83:p(44;;Md95~h603>=7pg<:188k3<722wx=94?:3y]51=:i390q~?9:181[7134k1:6sr}|CDF}6:3im>hj>c1CDG}7uIJ[wpNO \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/_impact.cmd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_impact.cmd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_impact.cmd (revision 260) @@ -0,0 +1,15 @@ +setpreference -novice +setpreference -stop_on_failure +setPreference -fixClock +setPreference -PC4_200K +setMode -bs +setMode -bs +setMode -bs +setCable -port auto +setMode -bs +setMode -bs +Identify +setAttribute -position 1 -attr configFileName -value E:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit +setMode -bs +setMode -bs +Program -p 1 Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cup =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cup (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cup (revision 260) @@ -0,0 +1 @@ +cleaned up XST temp files Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ut =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ut (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.ut (revision 260) @@ -0,0 +1,30 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:JtagClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.mrp =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.mrp (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_map.mrp (revision 260) @@ -0,0 +1,37 @@ +Release 12.3 Map M.70d (lin) +Xilinx Mapping Report File for Design 'BtnDemo' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off +-c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf +Target Device : xc3s1000 +Target Package : fg320 +Target Speed : -4 +Mapper Version : spartan3 -- $Revision: 1.52 $ +Mapped Date : Wed Apr 30 19:14:28 2014 + +Design Summary +-------------- +Number of errors : 1 +Number of warnings : 0 + +Section 1 - Errors +------------------ +ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part +'xc3s1000'. +ERROR:Map:258 - A problem was encountered attempting to get the license for this + architecture. + +Section 2 - Warnings +-------------------- +WARNING:Security:43 - No license file was found in the standard Xilinx license +directory. +WARNING:Security:44 - No license file was found. + +Section 3 - Informational +------------------------- +INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. +INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set. +INFO:Security:54 - 'xc3s1000' is a WebPack part. +INFO:Security:68 - Please run the Xilinx License Configuration Manager Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.lso =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.lso (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.lso (revision 260) @@ -0,0 +1 @@ +work Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bld =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bld (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.bld (revision 260) @@ -0,0 +1,23 @@ +Release 6.2.03i - ngdbuild G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo +-uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd + +Reading NGO file "X:/Barron/config/D2/BASIC/BtnDemo/btndemo.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "btndemo.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 39036 kilobytes + +Writing NGD file "btndemo.ngd" ... + +Writing NGDBUILD log file "btndemo.bld"... Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ncd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ncd =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ncd (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ncd (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ncd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.zip =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.zip (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.zip (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.txt =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.txt (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.txt (revision 260) @@ -0,0 +1,232 @@ +Release 6.2.03i - Par G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Wed Jul 07 09:50:35 2004 + + +INPUT FILE: btndemo_map.ncd +OUTPUT FILE: btndemo_pad.txt +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: pq208 + +Pinout by Pin Number: + +----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- | +Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint| +P1 | | |GND | | | | | | | | | | +P2 | | |TMS | | | | | | | | | | +P3 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P4 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | +P5 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P6 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | +P7 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P8 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P9 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | +P10 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P11 | | |GND | | | | | | | | | | +P12 | | |VCCO | | |0 | | | | |na | | +P13 | | |VCCINT | | | | | | | |2.5 | | +P14 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P15 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P16 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P17 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P18 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P19 | | |GND | | | | | | | | | | +P20 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | +P21 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P22 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P23 | |IOB | |UNUSED | |(0,7)*** | | | | | | | +P24 | |PCIIOB |IO_IRDY |UNUSED | |(0,7)*** | | | | | | | +P25 | | |GND | | | | | | | | | | +P26 | | |VCCO | | |0 | | | | |na | | +P27 | |PCIIOB |IO_TRDY |UNUSED | |(0,6)*** | | | | | | | +P28 | | |VCCINT | | | | | | | |2.5 | | +P29 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P30 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P31 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | +P32 | | |GND | | | | | | | | | | +P33 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P34 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P35 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P36 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P37 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P38 | | |VCCINT | | | | | | | |2.5 | | +P39 | | |VCCO | | |0 | | | | |na | | +P40 | | |GND | | | | | | | | | | +P41 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P42 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | +P43 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P44 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P45 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | +P46 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P47 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | +P48 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P49 | |IOB | |UNUSED | |(0,6)*** | | | | | | | +P50 | | |M1 | | | | | | | | | | +P51 | | |GND | | | | | | | | | | +P52 | | |M0 | | | | | | | | | | +P53 | | |VCCO | | |0 | | | | |na | | +P54 | | |M2 | | | | | | | | | | +P55 | | |NC | | | | | | | | | | +P56 | | |NC | | | | | | | | | | +P57 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | +P58 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P59 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | +P60 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P61 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P62 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | +P63 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P64 | | |GND | | | | | | | | | | +P65 | | |VCCO | | |0 | | | | |na | | +P66 | | |VCCINT | | | | | | | |2.5 | | +P67 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P68 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P69 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P70 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P71 |led |IOB | |OUTPUT |LVTTL |(0,5)*** |12 |SLOW |NONE** | | |LOCATED | +P72 | | |GND | | | | | | | | | | +P73 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | +P74 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P75 | |IOB | |UNUSED | |(0,5)*** | | | | | | | +P76 | | |VCCINT | | | | | | | |2.5 | | +P77 |btn |GCLKIOB |GCK1 |INPUT |LVTTL |(0,5)*** | | | | | |LOCATED | +P78 | | |VCCO | | |0 | | | | |na | | +P79 | | |GND | | | | | | | | | | +P80 | |GCLKIOB |GCK0 |UNUSED | |(0,4)*** | | | | | | | +P81 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P82 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P83 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P84 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | +P85 | | |GND | | | | | | | | | | +P86 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P87 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P88 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P89 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P90 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P91 | | |VCCINT | | | | | | | |2.5 | | +P92 | | |VCCO | | |0 | | | | |na | | +P93 | | |GND | | | | | | | | | | +P94 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P95 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | +P96 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P97 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P98 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | +P99 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P100 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | +P101 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P102 | |IOB | |UNUSED | |(0,4)*** | | | | | | | +P103 | | |GND | | | | | | | | | | +P104 | | |DONE | | | | | | | | | | +P105 | | |VCCO | | |0 | | | | |na | | +P106 | | |PROGRAM | | | | | | | | | | +P107 | |IOB |IO_INIT |UNUSED | |(0,3)*** | | | | | | | +P108 | |IOB |IO_D7 |UNUSED | |(0,3)*** | | | | | | | +P109 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | +P110 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P111 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | +P112 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P113 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P114 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | +P115 | |IOB |IO_D6 |UNUSED | |(0,3)*** | | | | | | | +P116 | | |GND | | | | | | | | | | +P117 | | |VCCO | | |0 | | | | |na | | +P118 | | |VCCINT | | | | | | | |2.5 | | +P119 | |IOB |IO_D5 |UNUSED | |(0,3)*** | | | | | | | +P120 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P121 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P122 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P123 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P124 | | |GND | | | | | | | | | | +P125 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | +P126 | |IOB |IO_D4 |UNUSED | |(0,3)*** | | | | | | | +P127 | |IOB | |UNUSED | |(0,3)*** | | | | | | | +P128 | | |VCCINT | | | | | | | |2.5 | | +P129 | |PCIIOB |IO_TRDY |UNUSED | |(0,3)*** | | | | | | | +P130 | | |VCCO | | |0 | | | | |na | | +P131 | | |GND | | | | | | | | | | +P132 | |PCIIOB |IO_IRDY |UNUSED | |(0,2)*** | | | | | | | +P133 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P134 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P135 | |IOB |IO_D3 |UNUSED | |(0,2)*** | | | | | | | +P136 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | +P137 | | |GND | | | | | | | | | | +P138 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P139 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P140 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P141 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P142 | |IOB |IO_D2 |UNUSED | |(0,2)*** | | | | | | | +P143 | | |VCCINT | | | | | | | |2.5 | | +P144 | | |VCCO | | |0 | | | | |na | | +P145 | | |GND | | | | | | | | | | +P146 | |IOB |IO_D1 |UNUSED | |(0,2)*** | | | | | | | +P147 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | +P148 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P149 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P150 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | +P151 | |IOB | |UNUSED | |(0,2)*** | | | | | | | +P152 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | +P153 | |IOB |IO_DIN_D0 |UNUSED | |(0,2)*** | | | | | | | +P154 | |IOB |IO_DOUT_BUSY|UNUSED | |(0,2)*** | | | | | | | +P155 | | |CCLK | | | | | | | | | | +P156 | | |VCCO | | |0 | | | | |na | | +P157 | | |TDO | | | | | | | | | | +P158 | | |GND | | | | | | | | | | +P159 | | |TDI | | | | | | | | | | +P160 | |IOB |IO_CS |UNUSED | |(0,1)*** | | | | | | | +P161 | |IOB |IO_WRITE |UNUSED | |(0,1)*** | | | | | | | +P162 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | +P163 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P164 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | +P165 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P166 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P167 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | +P168 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P169 | | |GND | | | | | | | | | | +P170 | | |VCCO | | |0 | | | | |na | | +P171 | | |VCCINT | | | | | | | |2.5 | | +P172 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P173 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P174 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P175 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P176 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P177 | | |GND | | | | | | | | | | +P178 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | +P179 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P180 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P181 | |IOB | |UNUSED | |(0,1)*** | | | | | | | +P182 | |GCLKIOB |GCK2 |UNUSED | |(0,1)*** | | | | | | | +P183 | | |GND | | | | | | | | | | +P184 | | |VCCO | | |0 | | | | |na | | +P185 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | | +P186 | | |VCCINT | | | | | | | |2.5 | | +P187 | |IOB | |UNUSED | |0 | | | | | | | +P188 | |IOB | |UNUSED | |0 | | | | | | | +P189 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | +P190 | | |GND | | | | | | | | | | +P191 | |IOB | |UNUSED | |0 | | | | | | | +P192 | |IOB | |UNUSED | |0 | | | | | | | +P193 | |IOB | |UNUSED | |0 | | | | | | | +P194 | |IOB | |UNUSED | |0 | | | | | | | +P195 | |IOB | |UNUSED | |0 | | | | | | | +P196 | | |VCCINT | | | | | | | |2.5 | | +P197 | | |VCCO | | |0 | | | | |na | | +P198 | | |GND | | | | | | | | | | +P199 | |IOB | |UNUSED | |0 | | | | | | | +P200 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | +P201 | |IOB | |UNUSED | |0 | | | | | | | +P202 | |IOB | |UNUSED | |0 | | | | | | | +P203 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | +P204 | |IOB | |UNUSED | |0 | | | | | | | +P205 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | +P206 | |IOB | |UNUSED | |0 | | | | | | | +P207 | | |TCK | | | | | | | | | | +P208 | | |VCCO | | |0 | | | | |na | | + +----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- | + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +*** In some smaller packages, the VCCO bank number of a pin may trail + the VREF bank number (VCCO,VREF). + Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ise5_bak.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ise5_bak.zip =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ise5_bak.zip (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ise5_bak.zip (revision 260)
phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo_ise5_bak.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cmd_log =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cmd_log (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.cmd_log (revision 260) @@ -0,0 +1,25 @@ +xst -quiet -ifn __projnav/btndemo.xst -ofn btndemo.syr +ngdbuild -quiet -dd f:\engineering\projects\web5.1\d2\btndemo/_ngo -uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd +map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +trce -quiet -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf +bitgen -f btndemo.ut btndemo.ncd +bitgen -f btndemo.ut btndemo.ncd +xst -quiet -ifn __projnav/btndemo.xst -ofn btndemo.syr +ngdbuild -quiet -dd e:\engineering\projects\web5.1\d2\btndemo/_ngo -uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd +map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +trce -quiet -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf +bitgen -f btndemo.ut btndemo.ncd +xst -intstyle ise -ifn __projnav/btndemo.xst -ofn btndemo.syr +ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo -uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd +map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +trce -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf +bitgen -intstyle ise -f btndemo.ut btndemo.ncd +xst -intstyle ise -ifn __projnav/btndemo.xst -ofn btndemo.syr +ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo -uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd +map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf +par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf +trce -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf +bitgen -intstyle ise -f btndemo.ut btndemo.ncd Index: phr/trunk/codigo/demos/projects/BtnDemo/_impact.log =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_impact.log (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_impact.log (revision 260) @@ -0,0 +1,60 @@ +iMPACT Version: F.23 +iMPACT log file Started on 2003/05/29 12:20:14 +// *** BATCH CMD : setpreference -novice +// *** BATCH CMD : setpreference -stop_on_failure +// *** BATCH CMD : setPreference -fixClock +// *** BATCH CMD : setPreference -PC4_200K +GUI --- Boundary Scan Mode selected +// *** BATCH CMD : setMode -bs +// *** BATCH CMD : setMode -bs +// *** BATCH CMD : setMode -bs +GUI --- Auto connect to cable... +AutoDetecting cable. Please wait. +CB_PROGRESS_START - Starting Operation. +Connecting to cable (USB Port). +Cable connection failed. +Connecting to cable (Parallel Port - LPT1). +Checking cable driver. + Driver Version = 505. +Cable connection established. +CB_PROGRESS_END - End Operation. +Elapsed time = 0 sec. +// *** BATCH CMD : setCable -port auto +// *** BATCH CMD : setMode -bs +// *** BATCH CMD : setMode -bs +PROGRESS_START - Starting Operation. +Identifying chain contents ....Identified xc2s200. +INFO:iMPACT:1366 - + Reading C:/XilinxISE/spartan2/data\xc2s200.bsd... + Reading C:/XilinxISE/spartan2/data\xc2s200.bsd... +INFO:iMPACT:501 - '1': Added Device xc2s200 successfully. +---------------------------------------------------------------------- +---------------------------------------------------------------------- +done. +PROGRESS_END - End Operation. +Elapsed time = 1 sec. +// *** BATCH CMD : Identify +'1': Loading file 'E:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit' ... +done. +INFO:iMPACT:1366 - + Reading C:/XilinxISE/spartan2/data\xc2s200.bsd... + Reading C:/XilinxISE/spartan2/data\xc2s200.bsd... +INFO:iMPACT:501 - '1': Added Device xc2s200 successfully. +---------------------------------------------------------------------- +---------------------------------------------------------------------- +---------------------------------------------------------------------- +---------------------------------------------------------------------- +// *** BATCH CMD : setAttribute -position 1 -attr configFileName -valueE:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit +// *** BATCH CMD : setMode -bs +// *** BATCH CMD : setMode -bs +PROGRESS_START - Starting Operation. +Validating chain... +Boundary-scan chain validated successfully. +'1':Programming device...done. +INFO:iMPACT:579 - '1': Completed downloading bit file to device. +INFO:iMPACT:580 - '1':Checking done pin ....done. +'1': Programmed successfully. +PROGRESS_END - End Operation. +Elapsed time = 8 sec. +// *** BATCH CMD : Program -p 1 +***** Closing iMPACT program. ***** Index: phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/ngdbuild.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/ngdbuild.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/ngdbuild.xmsgs (revision 260) @@ -0,0 +1,9 @@ + + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/pn_parser.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/pn_parser.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/pn_parser.xmsgs (revision 260) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" into library work + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/map.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/map.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/map.xmsgs (revision 260) @@ -0,0 +1,12 @@ + + + +A problem was encountered attempting to get the license for this architecture. + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/xst.xmsgs =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/xst.xmsgs (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/_xmsgs/xst.xmsgs (revision 260) @@ -0,0 +1,15 @@ + + + +'-hierarchy_separator' switch is being deprecated in a future release. + + +"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" line 70: Instantiating black box module <IBUFG>. + + + + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twr (revision 260) @@ -0,0 +1,39 @@ +-------------------------------------------------------------------------------- +Release 6.2.03i Trace G.28 +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o +btndemo.twr btndemo.pcf + + +Design file: btndemo.ncd +Physical constraint file: btndemo.pcf +Device,speed: xc2s200,-5 (PRODUCTION 1.27 2003-12-13) +Report level: error report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Pad to Pad +---------------+---------------+---------+ +Source Pad |Destination Pad| Delay | +---------------+---------------+---------+ +btn |led | 7.273| +---------------+---------------+---------+ + +Analysis completed Wed Jul 07 09:50:48 2004 +-------------------------------------------------------------------------------- + +Peak Memory Usage: 47 MB Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.syr =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.syr (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.syr (revision 260) @@ -0,0 +1,214 @@ +Release 6.2.03i - xst G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.02 / 2.23 s | Elapsed : 0.00 / 2.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.01 / 2.27 s | Elapsed : 0.00 / 2.00 s + +--> Reading design: btndemo.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : btndemo.prj +Input Format : mixed +Ignore Synthesis Constraint File : NO +Verilog Include Directory : + +---- Target Parameters +Output File Name : btndemo +Output Format : NGC +Target Device : xc2s200-5-pq208 + +---- Source Options +Top Module Name : btndemo +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : lut +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100 +Add Generic Clock Buffer(BUFG) : 4 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : btndemo.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +Optimize Instantiated Primitives : NO +tristate2logic : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd in Library work. +Architecture behavioral of Entity btndemo is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:766 - X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component . +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd. +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : btndemo.ngr +Top Level Output File Name : btndemo +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 2 + +Cell Usage : +# IO Buffers : 2 +# IBUFG : 1 +# OBUF : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200pq208-5 + + Number of bonded IOBs: 2 out of 144 1% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.404ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +------------------------------------------------------------------------- +Timing constraint: Default path analysis +Delay: 8.404ns (Levels of Logic = 2) + Source: btn (PAD) + Destination: led (PAD) + + Data Path: btn to led + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUFG:I->O 1 1.697 1.150 U1 (led_OBUF) + OBUF:I->O 5.557 led_OBUF (led) + ---------------------------------------- + Total 8.404ns (7.254ns logic, 1.150ns route) + (86.3% logic, 13.7% route) + +========================================================================= +CPU : 8.38 / 12.41 s | Elapsed : 8.00 / 12.00 s + +--> + +Total memory usage is 58968 kilobytes + + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xst =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xst (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.xst (revision 260) @@ -0,0 +1,41 @@ +set -tmpdir . +set -overwrite YES +set -xsthdpdir ./xst +run +-ifmt VHDL +-ent btndemo +-p xc2s200-pq208-5 +-ifn btndemo.prj +-opt_mode Speed +-opt_level 1 +-check_attribute_syntax YES +-keep_hierarchy No +-glob_opt AllClockNets +-write_timing_constraints No +-fsm_extract YES -fsm_encoding Auto +-fsm_fftype D +-mux_extract YES +-resource_sharing YES +-complex_clken YES +-rom_extract Yes +-ram_extract Yes +-ram_style Auto +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-iobuf YES +-equivalent_register_removal YES +-bufg 4 +-max_fanout 100 +-incremental_synthesis NO +-register_duplication YES +-register_balancing No +-move_first_stage YES +-move_last_stage YES +-slice_packing YES +-iob auto +-ofn btndemo +-ofmt NGC Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ngm =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ngm (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_map.ngm (revision 260) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$40x50=#Zl|bdaa:!3-53(?&8*/=85+Rdtjwlii2);%5= ;.2"'g>4t:9:{}?>7-418FP@682H^EAJPT@PDAQGUKA?0OFLZF89@KHKN\]OO;6M]E@VF@`=CZJUXYNMJSRDVH==BPYKEHHJ;;GPBCg=AZHMHC[K]EEc8BWG@WKKXIIo4FSCD[FIRF]20J_AB_TAE55=AzhmGeo ctm8JTDB682LymjBfb/nwh?IE]O;;7K|ngMka*irk2FZJH<64FscdHld)d}f1T[EPGBNHMGSA=2M%?4:EFJ@TF\LN+\B][-GNJJQ753NOEI_O[EE"SKVR*O:::7D;4ICWEC7=NF11BBKK]RDF5?LIDGDZ=7DA[YQG7?LVFL>1GEO\NRX48HJGCMM90@BM8;MMDMFGK02FoaRZvpd`8IDVBPYKEHHJ9;LCST@Bf3DK[S@AKUMGg?HGWW]CFI^ZNMQ`8IDVX^LXXEB@l;LcikwPbzzcdbn5BiomqR`ttafd<7CK[WNPH5>I33FH^J95@P@F0?JSS;2Z<=>5_7618TDB33YKYX55_HXQJGDJ>3ZCLSNAZNU18WKM13ZE^^NK<;RP@b>RFZNO_S]O]TU[SA1=SQYO97X?l;TQFVZPN[@HGI45YIDU\P\VB9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGMc:ZUOZADDBCIYK84Xe`\Mac^c`VZye`Zvpdd8\anXX{cfZh||inl4?]boW]kln6Vkm^@jjaoio8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`<;Yqw7>dsf>1ixcjjmn18h`b?3eooSBLZF29neu>0?47?<:012gf642;2?9;ua4782?k202;1/?k4?lc1196=22?2Y:i7:j:08274ed8:0949;l;R490`<6289:on><:3:7<<=T9l0?h7>5123`g55=:1>3h6]=3;6g>45=9:;ho==5296;b>U12=n1<7?<1ba37?4?<1l0h9o50;396~U02=21=>4>30a`46<50=?=7):54g9K<>h5=3>;in<6be9'61<3n2.9:7?<;wV16?6=93;1?v]8:5:956<6;8ih<>4=8575?!5e2;:0Z9=52zw13?7<};21<6s+3081?g2f2909694<{%1;>1g<@:k0b9:50:k7=?6=3f>i6=44b2;95?4=83:p(>65169K7d=O;m1/8?4:;%3a>4><@8k0(=h:h0:6):=:3f8?xd3k3;1>7>50z&06=O9h1/=o4=d:&2`?363g>?6?5f1782>!2528207bf;0e?k232:1b?=4>:%61>66<3th?n7?51;294~"3:39;7E=n;I3:?!7e2;n0(=z{=31<7=t^5;896?=9?16844<0:p0f<72;q6?44=a:?7g?713ty?n7>53z\7f>;3k38j70:m:228yxh6i3:1=vFc;295~N4i2C8<7?t2;Ya?7|9o0vb9:52:~rQd=83;1=7=tS687`?6=9:;ho==5296;a>"4j3997)=>:39K51=O9<1i8l4?:387>6}Ok2.8;7<4ne87?k542:1e894?;h6:>5<7<729q/?54=:k1/=o4=d:Jb?k232;1/><4>0:k22?7=3f8j6<44}c6:>4<6290;w)=7:0a8 4d=911/=k4=f:Jb?k232:1/><4i;n15>4<i6<4>:183!5?2;i0(602;k019m5179~w1d=839p19m52`9>0g<4<2T?n6srn3d94?7|f=>1<6sa3183>4}i<=0:7p`<1;295~h3<380qpsr@AAx70<>::o=597r@A@x55}383:1<7<524824>{|<80;6=4=:34954=zs=;1<7>52;04>44;6=4?:38150;096<<6<2wp8<4?:181>7g=9<1vw9>50;296?4e28<0qv:>:183>7<5k3;<7pu;0;294?4=:m0:46st4083>5<52;o1=45r}ABSxFG \ No newline at end of file Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.csv =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.csv (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo_pad.csv (revision 260) @@ -0,0 +1,237 @@ +Release 6.2.03i - Par G.31a +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Wed Jul 07 09:50:22 2004 + + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The , +character is used as the data field separator. This file is also designed +to support parsing. + +INPUT FILE: btndemo_map.ncd +OUTPUT FILE: btndemo_pad.csv +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: pq208 + +Pinout by Pin Number: + +-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint, +P1,,,GND,,,,,,,,,, +P2,,,TMS,,,,,,,,,, +P3,,IOB,,UNUSED,,(0,7)***,,,,,,, +P4,,IOB,IO_VREF_7,UNUSED,,(0,7)***,,,,,,, +P5,,IOB,,UNUSED,,(0,7)***,,,,,,, +P6,,IOB,IO_VREF_7,UNUSED,,(0,7)***,,,,,,, +P7,,IOB,,UNUSED,,(0,7)***,,,,,,, +P8,,IOB,,UNUSED,,(0,7)***,,,,,,, +P9,,IOB,IO_VREF_7,UNUSED,,(0,7)***,,,,,,, +P10,,IOB,,UNUSED,,(0,7)***,,,,,,, +P11,,,GND,,,,,,,,,, +P12,,,VCCO,,,0,,,,,na,, +P13,,,VCCINT,,,,,,,,2.5,, +P14,,IOB,,UNUSED,,(0,7)***,,,,,,, +P15,,IOB,,UNUSED,,(0,7)***,,,,,,, +P16,,IOB,,UNUSED,,(0,7)***,,,,,,, +P17,,IOB,,UNUSED,,(0,7)***,,,,,,, +P18,,IOB,,UNUSED,,(0,7)***,,,,,,, +P19,,,GND,,,,,,,,,, +P20,,IOB,IO_VREF_7,UNUSED,,(0,7)***,,,,,,, +P21,,IOB,,UNUSED,,(0,7)***,,,,,,, +P22,,IOB,,UNUSED,,(0,7)***,,,,,,, +P23,,IOB,,UNUSED,,(0,7)***,,,,,,, +P24,,PCIIOB,IO_IRDY,UNUSED,,(0,7)***,,,,,,, +P25,,,GND,,,,,,,,,, +P26,,,VCCO,,,0,,,,,na,, +P27,,PCIIOB,IO_TRDY,UNUSED,,(0,6)***,,,,,,, +P28,,,VCCINT,,,,,,,,2.5,, +P29,,IOB,,UNUSED,,(0,6)***,,,,,,, +P30,,IOB,,UNUSED,,(0,6)***,,,,,,, +P31,,IOB,IO_VREF_6,UNUSED,,(0,6)***,,,,,,, +P32,,,GND,,,,,,,,,, +P33,,IOB,,UNUSED,,(0,6)***,,,,,,, +P34,,IOB,,UNUSED,,(0,6)***,,,,,,, +P35,,IOB,,UNUSED,,(0,6)***,,,,,,, +P36,,IOB,,UNUSED,,(0,6)***,,,,,,, +P37,,IOB,,UNUSED,,(0,6)***,,,,,,, +P38,,,VCCINT,,,,,,,,2.5,, +P39,,,VCCO,,,0,,,,,na,, +P40,,,GND,,,,,,,,,, +P41,,IOB,,UNUSED,,(0,6)***,,,,,,, +P42,,IOB,IO_VREF_6,UNUSED,,(0,6)***,,,,,,, +P43,,IOB,,UNUSED,,(0,6)***,,,,,,, +P44,,IOB,,UNUSED,,(0,6)***,,,,,,, +P45,,IOB,IO_VREF_6,UNUSED,,(0,6)***,,,,,,, +P46,,IOB,,UNUSED,,(0,6)***,,,,,,, +P47,,IOB,IO_VREF_6,UNUSED,,(0,6)***,,,,,,, +P48,,IOB,,UNUSED,,(0,6)***,,,,,,, +P49,,IOB,,UNUSED,,(0,6)***,,,,,,, +P50,,,M1,,,,,,,,,, +P51,,,GND,,,,,,,,,, +P52,,,M0,,,,,,,,,, +P53,,,VCCO,,,0,,,,,na,, +P54,,,M2,,,,,,,,,, +P55,,,NC,,,,,,,,,, +P56,,,NC,,,,,,,,,, +P57,,IOB,IO_VREF_5,UNUSED,,(0,5)***,,,,,,, +P58,,IOB,,UNUSED,,(0,5)***,,,,,,, +P59,,IOB,IO_VREF_5,UNUSED,,(0,5)***,,,,,,, +P60,,IOB,,UNUSED,,(0,5)***,,,,,,, +P61,,IOB,,UNUSED,,(0,5)***,,,,,,, +P62,,IOB,IO_VREF_5,UNUSED,,(0,5)***,,,,,,, +P63,,IOB,,UNUSED,,(0,5)***,,,,,,, +P64,,,GND,,,,,,,,,, +P65,,,VCCO,,,0,,,,,na,, +P66,,,VCCINT,,,,,,,,2.5,, +P67,,IOB,,UNUSED,,(0,5)***,,,,,,, +P68,,IOB,,UNUSED,,(0,5)***,,,,,,, +P69,,IOB,,UNUSED,,(0,5)***,,,,,,, +P70,,IOB,,UNUSED,,(0,5)***,,,,,,, +P71,led,IOB,,OUTPUT,LVTTL,(0,5)***,12,SLOW,NONE**,,,LOCATED, +P72,,,GND,,,,,,,,,, +P73,,IOB,IO_VREF_5,UNUSED,,(0,5)***,,,,,,, +P74,,IOB,,UNUSED,,(0,5)***,,,,,,, +P75,,IOB,,UNUSED,,(0,5)***,,,,,,, +P76,,,VCCINT,,,,,,,,2.5,, +P77,btn,GCLKIOB,GCK1,INPUT,LVTTL,(0,5)***,,,,,,LOCATED, +P78,,,VCCO,,,0,,,,,na,, +P79,,,GND,,,,,,,,,, +P80,,GCLKIOB,GCK0,UNUSED,,(0,4)***,,,,,,, +P81,,IOB,,UNUSED,,(0,4)***,,,,,,, +P82,,IOB,,UNUSED,,(0,4)***,,,,,,, +P83,,IOB,,UNUSED,,(0,4)***,,,,,,, +P84,,IOB,IO_VREF_4,UNUSED,,(0,4)***,,,,,,, +P85,,,GND,,,,,,,,,, +P86,,IOB,,UNUSED,,(0,4)***,,,,,,, +P87,,IOB,,UNUSED,,(0,4)***,,,,,,, +P88,,IOB,,UNUSED,,(0,4)***,,,,,,, +P89,,IOB,,UNUSED,,(0,4)***,,,,,,, +P90,,IOB,,UNUSED,,(0,4)***,,,,,,, +P91,,,VCCINT,,,,,,,,2.5,, +P92,,,VCCO,,,0,,,,,na,, +P93,,,GND,,,,,,,,,, +P94,,IOB,,UNUSED,,(0,4)***,,,,,,, +P95,,IOB,IO_VREF_4,UNUSED,,(0,4)***,,,,,,, +P96,,IOB,,UNUSED,,(0,4)***,,,,,,, +P97,,IOB,,UNUSED,,(0,4)***,,,,,,, +P98,,IOB,IO_VREF_4,UNUSED,,(0,4)***,,,,,,, +P99,,IOB,,UNUSED,,(0,4)***,,,,,,, +P100,,IOB,IO_VREF_4,UNUSED,,(0,4)***,,,,,,, +P101,,IOB,,UNUSED,,(0,4)***,,,,,,, +P102,,IOB,,UNUSED,,(0,4)***,,,,,,, +P103,,,GND,,,,,,,,,, +P104,,,DONE,,,,,,,,,, +P105,,,VCCO,,,0,,,,,na,, +P106,,,PROGRAM,,,,,,,,,, +P107,,IOB,IO_INIT,UNUSED,,(0,3)***,,,,,,, +P108,,IOB,IO_D7,UNUSED,,(0,3)***,,,,,,, +P109,,IOB,IO_VREF_3,UNUSED,,(0,3)***,,,,,,, +P110,,IOB,,UNUSED,,(0,3)***,,,,,,, +P111,,IOB,IO_VREF_3,UNUSED,,(0,3)***,,,,,,, +P112,,IOB,,UNUSED,,(0,3)***,,,,,,, +P113,,IOB,,UNUSED,,(0,3)***,,,,,,, +P114,,IOB,IO_VREF_3,UNUSED,,(0,3)***,,,,,,, +P115,,IOB,IO_D6,UNUSED,,(0,3)***,,,,,,, +P116,,,GND,,,,,,,,,, +P117,,,VCCO,,,0,,,,,na,, +P118,,,VCCINT,,,,,,,,2.5,, +P119,,IOB,IO_D5,UNUSED,,(0,3)***,,,,,,, +P120,,IOB,,UNUSED,,(0,3)***,,,,,,, +P121,,IOB,,UNUSED,,(0,3)***,,,,,,, +P122,,IOB,,UNUSED,,(0,3)***,,,,,,, +P123,,IOB,,UNUSED,,(0,3)***,,,,,,, +P124,,,GND,,,,,,,,,, +P125,,IOB,IO_VREF_3,UNUSED,,(0,3)***,,,,,,, +P126,,IOB,IO_D4,UNUSED,,(0,3)***,,,,,,, +P127,,IOB,,UNUSED,,(0,3)***,,,,,,, +P128,,,VCCINT,,,,,,,,2.5,, +P129,,PCIIOB,IO_TRDY,UNUSED,,(0,3)***,,,,,,, +P130,,,VCCO,,,0,,,,,na,, +P131,,,GND,,,,,,,,,, +P132,,PCIIOB,IO_IRDY,UNUSED,,(0,2)***,,,,,,, +P133,,IOB,,UNUSED,,(0,2)***,,,,,,, +P134,,IOB,,UNUSED,,(0,2)***,,,,,,, +P135,,IOB,IO_D3,UNUSED,,(0,2)***,,,,,,, +P136,,IOB,IO_VREF_2,UNUSED,,(0,2)***,,,,,,, +P137,,,GND,,,,,,,,,, +P138,,IOB,,UNUSED,,(0,2)***,,,,,,, +P139,,IOB,,UNUSED,,(0,2)***,,,,,,, +P140,,IOB,,UNUSED,,(0,2)***,,,,,,, +P141,,IOB,,UNUSED,,(0,2)***,,,,,,, +P142,,IOB,IO_D2,UNUSED,,(0,2)***,,,,,,, +P143,,,VCCINT,,,,,,,,2.5,, +P144,,,VCCO,,,0,,,,,na,, +P145,,,GND,,,,,,,,,, +P146,,IOB,IO_D1,UNUSED,,(0,2)***,,,,,,, +P147,,IOB,IO_VREF_2,UNUSED,,(0,2)***,,,,,,, +P148,,IOB,,UNUSED,,(0,2)***,,,,,,, +P149,,IOB,,UNUSED,,(0,2)***,,,,,,, +P150,,IOB,IO_VREF_2,UNUSED,,(0,2)***,,,,,,, +P151,,IOB,,UNUSED,,(0,2)***,,,,,,, +P152,,IOB,IO_VREF_2,UNUSED,,(0,2)***,,,,,,, +P153,,IOB,IO_DIN_D0,UNUSED,,(0,2)***,,,,,,, +P154,,IOB,IO_DOUT_BUSY,UNUSED,,(0,2)***,,,,,,, +P155,,,CCLK,,,,,,,,,, +P156,,,VCCO,,,0,,,,,na,, +P157,,,TDO,,,,,,,,,, +P158,,,GND,,,,,,,,,, +P159,,,TDI,,,,,,,,,, +P160,,IOB,IO_CS,UNUSED,,(0,1)***,,,,,,, +P161,,IOB,IO_WRITE,UNUSED,,(0,1)***,,,,,,, +P162,,IOB,IO_VREF_1,UNUSED,,(0,1)***,,,,,,, +P163,,IOB,,UNUSED,,(0,1)***,,,,,,, +P164,,IOB,IO_VREF_1,UNUSED,,(0,1)***,,,,,,, +P165,,IOB,,UNUSED,,(0,1)***,,,,,,, +P166,,IOB,,UNUSED,,(0,1)***,,,,,,, +P167,,IOB,IO_VREF_1,UNUSED,,(0,1)***,,,,,,, +P168,,IOB,,UNUSED,,(0,1)***,,,,,,, +P169,,,GND,,,,,,,,,, +P170,,,VCCO,,,0,,,,,na,, +P171,,,VCCINT,,,,,,,,2.5,, +P172,,IOB,,UNUSED,,(0,1)***,,,,,,, +P173,,IOB,,UNUSED,,(0,1)***,,,,,,, +P174,,IOB,,UNUSED,,(0,1)***,,,,,,, +P175,,IOB,,UNUSED,,(0,1)***,,,,,,, +P176,,IOB,,UNUSED,,(0,1)***,,,,,,, +P177,,,GND,,,,,,,,,, +P178,,IOB,IO_VREF_1,UNUSED,,(0,1)***,,,,,,, +P179,,IOB,,UNUSED,,(0,1)***,,,,,,, +P180,,IOB,,UNUSED,,(0,1)***,,,,,,, +P181,,IOB,,UNUSED,,(0,1)***,,,,,,, +P182,,GCLKIOB,GCK2,UNUSED,,(0,1)***,,,,,,, +P183,,,GND,,,,,,,,,, +P184,,,VCCO,,,0,,,,,na,, +P185,,GCLKIOB,GCK3,UNUSED,,0,,,,,,, +P186,,,VCCINT,,,,,,,,2.5,, +P187,,IOB,,UNUSED,,0,,,,,,, +P188,,IOB,,UNUSED,,0,,,,,,, +P189,,IOB,IO_VREF_0,UNUSED,,0,,,,,,, +P190,,,GND,,,,,,,,,, +P191,,IOB,,UNUSED,,0,,,,,,, +P192,,IOB,,UNUSED,,0,,,,,,, +P193,,IOB,,UNUSED,,0,,,,,,, +P194,,IOB,,UNUSED,,0,,,,,,, +P195,,IOB,,UNUSED,,0,,,,,,, +P196,,,VCCINT,,,,,,,,2.5,, +P197,,,VCCO,,,0,,,,,na,, +P198,,,GND,,,,,,,,,, +P199,,IOB,,UNUSED,,0,,,,,,, +P200,,IOB,IO_VREF_0,UNUSED,,0,,,,,,, +P201,,IOB,,UNUSED,,0,,,,,,, +P202,,IOB,,UNUSED,,0,,,,,,, +P203,,IOB,IO_VREF_0,UNUSED,,0,,,,,,, +P204,,IOB,,UNUSED,,0,,,,,,, +P205,,IOB,IO_VREF_0,UNUSED,,0,,,,,,, +P206,,IOB,,UNUSED,,0,,,,,,, +P207,,,TCK,,,,,,,,,, +P208,,,VCCO,,,0,,,,,na,, + +-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +*** In some smaller packages, the VCCO bank number of a pin may trail + the VREF bank number (VCCO,VREF). + Index: phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twx =================================================================== --- phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twx (nonexistent) +++ phr/trunk/codigo/demos/projects/BtnDemo/btndemo.twx (revision 260) @@ -0,0 +1,237 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 6.2.03i Trace G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o +btndemo.twr btndemo.pcf + +btndemo.ncdbtndemo.pcfxc2s200-5PRODUCTION 1.27 2003-12-13INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.btnled7.273Wed Jul 07 09:50:48 2004TraceTrace SettingsPeak Memory Usage: 47 MB + Index: phr/trunk/codigo/demos/ref/DIO1_rm.pdf =================================================================== --- phr/trunk/codigo/demos/ref/DIO1_rm.pdf (nonexistent) +++ phr/trunk/codigo/demos/ref/DIO1_rm.pdf (revision 260) @@ -0,0 +1,1026 @@ +%PDF-1.4 +% +45 0 obj<> +endobj + +xref +45 32 +0000000016 00000 n +0000001269 00000 n +0000000936 00000 n +0000001349 00000 n +0000001528 00000 n +0000001725 00000 n +0000001946 00000 n +0000002022 00000 n +0000002258 00000 n +0000002503 00000 n +0000002742 00000 n +0000002969 00000 n +0000003003 00000 n +0000003395 00000 n +0000003835 00000 n +0000004352 00000 n +0000005023 00000 n +0000005421 00000 n +0000006098 00000 n +0000006228 00000 n +0000006533 00000 n +0000007893 00000 n +0000009058 00000 n +0000009831 00000 n +0000010568 00000 n +0000011400 00000 n +0000012385 00000 n +0000013729 00000 n +0000016398 00000 n +0000023832 00000 n +0000024061 00000 n +0000024258 00000 n +trailer +<]>> +startxref +0 +%%EOF + +47 0 obj<>stream +xb``` cc`ať̓9U ]]u0$j89'~werf3)K]vC EŠ;A/ `'}3wa0O";:t7 D#0I@qF - Ī`%^eL R}$d`l֑3kQqM0\PcMGc\ +x/,@bkEZ{ +endstream +endobj +46 0 obj<> +endobj +48 0 obj<> +endobj +49 0 obj<>/Font<>/XObject<>/ProcSet[/PDF/Text/ImageC]/ExtGState<>>> +endobj +50 0 obj<> +endobj +51 0 obj<> +endobj +52 0 obj<> +endobj +53 0 obj<> +endobj +54 0 obj<> +endobj +55 0 obj<> +endobj +56 0 obj[/ICCBased 72 0 R] +endobj +57 0 obj<> +endobj +58 0 obj<> +endobj +59 0 obj<> +endobj +60 0 obj<> +endobj +61 0 obj<> +endobj +62 0 obj<>stream +H̗n@~9R/7 )*hDF#3ݵS5  WȒwdٯ%b(aQ(@( zs, MJ/7 +HvS6}S0.Z ;R+o\aХfxRH8_2K>bx=7 |>"9c<0}j/OꑁGC;BS0@^uSn zVߞkRO=dK> +endobj +64 0 obj<>stream +HTPn -(Ia\b'=kR ;4;C9~F{L0Zg".~ጓuӎgfq- ΍ږЯ\\Ra8b@O`nԳL3 #jFW *ƨ܄2Y7 :i/*{`Fe$xX !Iv5ųL| sijo >$?/p` + +endstream +endobj +65 0 obj<>stream +HVn6}Ẉ\Čݢ@l]H}-16Zi%l آL93,?!$Yy/3|=n(S"Mu {n']#9pfY|8d3o6y$ͨ\ [[[z}Gˎ5,~]qN +€fl]`;@0$B!UIgNQ-T2j*I zj%s0AHl3*@M\*}5 Ddk0PjHk+xvm͒zf-vM%5ju#WjI"yQP9iqw06-OӞZ:s9VH 20:CPFf_Mc ejZ'mR/\MlUS;L ޶ݓ/v\ Z'e5BVcHjk/L?l9)_r0 +(.5=e5fzd(x3t,hLv^nfLnw %V.;# X!X.pɁB݀+[[</ +E%@/KK&C려xzIV`4ZC6>stream +HVMo8WQ.jV($b?{H{P,fX$'!)Sif +!~d$˲]]_t쾝صTHiwM"^|^=LYl>Gs:Gz?4cC׿Eî98`NrdIS54YҤE ?I0ɠ~b[ŷvnK<38/jº1_-R3KbaHKKe~]ܐEHkx~{86zD^"mN^xf24A,nR ;l0QR~1 +N%d\mΪmPПiwL>\M\ݚ23a .&ow_2hsReS*H&܆rFP! +e$akdA>I$7,',81A*1R2\uڞ ]i8RᐫԢcc&D혓 +CX\"UYH!ʥcQ$HLRkH<|(ixP `!Qa +:$9 + Qki:xˎQ +BA$Hu %tA(`=(z5/u ji9Lx[n7VŋEd9Cy~hś Q,=Wέq5Rm?aJ,SÔE:i:D\-&@pZ-#q-Pb04kU!jqL%>stream +HWA +:F:oS6C ]H8HЁ\ʬ6٭n{ׅ 1DJy>9>X~=XH}zy8S_/Oln kooF4Śo (lRʆ +:D +(hfy(h +਱|"% C~kIe-__ +N"U Cu dX6A"ݕnKT8"UE 1۝&ߡaDW!-6$ +ɹ? )A.YGtT>L[`9B(1f +٘dBnT +vX*I>stream +HU@ [0}r \%M\?JZ\psY>"h%r9@\ UPMtdŖ4b ~X?>L_S)W +( w".˷y{y>^Z>/|2$p"w ?ؚMpXdKÿ_ӧSu4DJg:A,e1/Pu@+CkS-V-PY z*.e(\BhvaXF@3fh=y]!$PCuQĎmġ>stream +HVnAWqL%oQDdC#E=5lqwuUmZF[:k/W:*rsȓqGp'ވOФ4k(-w۽2u@ +Wߥ"I>I=%-Z +d)kp*-()l+FGgd 'gĞMCKyƑt,! ;w +! +вYʱ9eCѳ9igQٕF5(+&mf/H +V<&w87fs%Vڐv^n.J7V`moPl]uVwˌCr8;O-BlۀOZ7wͩ<@U9?Cdt’oDN: rK(:>2H qYxhDx<*0++ 9xI +B,V.LȁF R3C2})_^ºЦ()_󊤢W2P®laKTow{@ȾqrWbRkұu5S~'WDfNG+h?d_1pTPxFh''ܼ.qJ< l-`(9W3UѾdJXcY⁰UCCJc~cHVcc 'z&zƎ'N/?\U"GSMx8dlZ*6HUnWѲ:dz RO,0TJ +endstream +endobj +70 0 obj<>stream +HWMo1 ϯq&v'J9VPG&Cة!bD9] +P .'M㋈g_ G! r(ye)حř.#'D B3{@Ch +ûdY\s#R~]6swu3SsqiF 5K`~yO+E;B/&z8Ǥkq|T!FERu +$\"|g@]U[g^(R~%82.XX +^;÷y+NTԪk]Xm~)ǡz#i!ߗlzۿk"]jCmЕӞ-GC4RP? j,WXdfiY^X12W[m?.nonn=r!nwm3C"r]kW TV3ai[exu16:ׁ{&hAadz/j14X](4!7; VGAzpT^0gX'hۛ%z<̞:!.߇W}s* T!&)8&pHZ/`d +endstream +endobj +71 0 obj<>stream +HWMoG ﯘ*&C1۴KڱFm}V@-9#ݣWѪ}f'vNW7J05toݧ>/}X,r˱~yJ@K5YIOWUOG}jcl-9נzۑ~}|iΜؼW,jr73wlM,n0CE6l +l.gQfP# + +Bq|{ss_/aAމzFCT[نd#4Rt==@q'rg~u蔠'v A pd)iʍ'~DY׻/7xPo*3.!IFHAn+ +@vG+:HZKXjYڙ0e=} a D64ga:1w3];2FfoK_OJb1r*jg>{)HNe?|(uBh-9=)v$ob^_ x}?ȧhKt3H;6W"l(p$a  L^p +endstream +endobj +72 0 obj<>stream +HyTSwoɞc +[5laQIBHADED2mtFOE.c}08׎8GNg9w߽'0 ֠Jb  + 2y.-;!KZ ^i"L0- +@8(r;q7Ly&Qq4j|9 +V)gB0iW8#8wթ8_٥ʨQQj@&A)/g>'Kt;\ +ӥ$պFZUn(4T%)뫔0C&Zi8bxEB;Pӓ̹A om?W= +x-[0}y)7ta>jT7@tܛ`q2ʀ&6ZLĄ?_yxg)˔zçLU*uSkSeO4?׸c. R +߁-25 S>ӣVd`rn~Y&+`;A4 A9=-tl`;~p Gp| [`L`< "A YA+Cb(R,*T2B- +ꇆnQt}MA0alSx k&^>0|>_',G!"F$H:R!zFQd?r 9\A&G rQ hE]a4zBgE#H *B=0HIpp0MxJ$D1D, VĭKĻYdE"EI2EBGt4MzNr!YK ?%_&#(0J:EAiQ(()ӔWT6U@P+!~mD eԴ!hӦh/']B/ҏӿ?a0nhF!X8܌kc&5S6lIa2cKMA!E#ƒdV(kel +}}Cq9 +N')].uJr + wG xR^[oƜchg`>b$*~ :Eb~,m,-ݖ,Y¬*6X[ݱF=3뭷Y~dó ti zf6~`{v.Ng#{}}jc1X6fm;'_9 r:8q:˜O:ϸ8uJqnv=MmR 4 +n3ܣkGݯz=[==<=GTB(/S,]6*-W:#7*e^YDY}UjAyT`#D="b{ų+ʯ:!kJ4Gmt}uC%K7YVfFY .=b?SƕƩȺy +چ k5%4m7lqlioZlG+Zz͹mzy]?uuw|"űNwW&e֥ﺱ*|j5kyݭǯg^ykEklD_p߶7Dmo꿻1ml{Mś +nLl<9O[$h՛BdҞ@iءG&vVǥ8nRĩ7u\ЭD-u`ֲK³8%yhYѹJº;.! +zpg_XQKFAǿ=ȼ:ɹ8ʷ6˶5̵5͵6ζ7ϸ9к<Ѿ?DINU\dlvۀ܊ݖޢ)߯6DScs +2F[p(@Xr4Pm8Ww)Km + +endstream +endobj +73 0 obj<>stream +HW Tg뼀#YaYSb+)lpVBμ/6y7>x~՜ֲq+7l9%>ɂIZJ 89O,,>ᶢ.Nļ-ï|(+0>_WpᾓU3<#> +_&2N,˄{d5ObsmlÒ7y71&%. +Z\i;N= G 3ŝΔyM)啡wxtx?b7ߢ|x?;ԗxbv +'8j~ҋ`)]oӰ}qejc%WsX\3jo9.RoGS/r1{4L]ҢS%[|oik{uCI0g=r'C7uqK6gm:_~?OM2/ݽ`BBۦuݧ/N;#!C!G)a'o+˓yFt|t~NU¢ KX׽BT~vrBʙQGA͇ލF1߷R 7}K[J>Y.xzLxΛrgX4u{m÷d0~E9;[2޲46y3aB~hTpl8a@ȡ + +2V i (=)9 +!Aї)IQѲXY$͘'!MA{ %А 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+# Y/Y'Y+Y+Y#Y-Y%Y%X?G^$%= kõFZz*"52Y `ddddddd` X9OgxrsHL7e#ZQ7mxf)l,w.X8KvM5Cb'b9rY|wWӞZqw-LKra>4oxW +TmYeU+#K E#- >w1L7kxM +$IEjaEŵ;Zaŕz͆C3'3= Yf D#ɕNNVFZZzI 2T_%dq|*z_V|Xqe},WWR*U̜U9W $ $'Wb*YY_SuOuS 9,XjI`n/$1*{T@GK}ӹGe4_{Pc'l?5MNNtﵓRB=DJeNRۜqVJ >7U8&xb lѸIяS$N¨V5\mU!Qw⼣֝%{Gɧ*qRv(4\(iܳ}8,Dz::Zjj*"%qYEVl +$ +VJz.K`u\$$%$k%[zB@J +5ePoY㘆q\}ӗ`l6BEZz12L!#i*O9υ_d[qZ!8k.AbLx:Ñ;lU}J]r!ՉܻN։C??H|CSC#eP +Cje^>03Sg$^feJe2[ɮH Őo!.H>oi1}uEƼ ~.q{\neXtZk\ 1Y۽,dr5MwD_m+md6uT'̮% ͆6(KjV}6%r(W0L|YRn\ѵ/)vu"`g( b=8ߖjqD#irqoƠ/oկMҿm7, )D}OeFѬ!dFb'bOvѭn2kV@)>vf tfz@Fa;eT/)oT0bL~iH-(ZSp5DI&˚,)g-!s],u$>vC1"2b@qz8!4c}dQpps:)n+}RF>.boV-;x)cSFVrƳ`T,M9]>W!,!pGRѣca}uf3.](MZڪz#g\z+v.[Vc[b/\:9gu/&\paݛ,ug[ >lSuf OIS6㎿\_GwGD=moNꔏ9tt규 b$Rx4(`*hI970 +S+Q^ZUsgz9aDC^V٤1ߕ9SP.n]ZG-Ť|=ɜ`a)q;ֽco؀/B -&5txdL"ʫe7n9zta=-A)zCKZiˏ[jL.Eq8LD$&q~zҀN'(7g#MI\^[o^ x%=6 x#ɭ9#{W#6V{woו :jZhoV(;6D1iGMYPYs&Qx_G|2<ҪH5'!m!u0@ږ]|yXXr.E1;%w`uA63[m)3Wl>WcQder࣡2(?tVE1D8ߒx:+-~۪ۊlMźzn4<fIu/96^@} Uleɑss;)Džٽù}"< +g/d{ۗۧ/S5}cĵĆf$$+2׀#*/CBm:3q{Cנ(6[4t$ZO0G+r4T0rvotPÑ9^݃RN8Hd +Hv7Z5-<Q'&4&Yƍͯ(<,H>L՘M + +endstream +endobj +29 0 obj<> +endobj +30 0 obj<>/Font<>/ProcSet[/PDF/Text]/ExtGState<>>> +endobj +31 0 obj<>stream +Hr8b8/+TVeBh +e<ϻ8$v\%h|xffx^szRrŸ{4UD˔JE/EuHI)YogrI֏ɪ)Eu$_~esq]j[~'3)4",Sz#%YH2M5 +9H墸Q\]\.8yO +F!v|#%;KP1*}!&`Zr%kES{7g~qtUoiͱ/I% uN3rlP9;0QM +Ǩu/@Qci0*e}f &MNE7 V KH`R\@GTj#R0i $Q XhK# %`HO83F sqyd̨NJն,RdMS_ï=9 2\Yhv M!8} . mnejaK .2DvQ=ʛx{b + +'ST +`]u,%o;ԻlBsHdD{)`lV9ĝrtCxbgdLaȷ]JA+ u#5\ȻzCClǐIFa }"mSf12ʢn"-,9>֐EDT}DUUV7nB]%m[WGn*L}I<> YD6d!ewHq1|zC$rWGJ.kr,,~s,몹- cӇnk|AqM~"w{/Wz`ەkZ6y)b4m+Ȱ +ߙ:SnجM:4%ϷLHv_ElSqmBo-vv4O֧㦀mvikǃ +z[vF+=Ɗw^= + {WV=hzׁ|I'`m8s(Hs[?"{KzUm`$~)o{H^ݦiΎvvA +jx(UH׷zsFGѭg9rqu[as({9H +j[4J*?I;EbaO/ӧw?cM%L(ByN^>I0`[9'pgb:(h+!苙38ϰ:ҹ~@,CGg=''o~_p6 i ᨆӽ\ F;.AE$KS,m?|[v ̂ 25X6vu\cr +:ds'J3530;gwD~^8|g(-&V6atOeE@1rDzTgne=x>lD&Kc}A&N*yD@tWWE=ELn32f91+yr1lrԣG=pX!T*w0G 9;gx  ܈\ba,4x0w2r^r;8^&P ]+qЇ}noK)4Os8 +,/7f6$ +Fn]aJ|prai'3h`c1{:jPX|!uQ_?3)dAL 'W-2sT%XYjs$!9+QGVj^lwpra쑃}⫑MԨ9=v3z,{rf8lk0kQg6f _Ƭo9 +򾱿-,syYfERY^ ̳+xw􊌻k^ s\c1+&"VogC:C8daA=3q?q1V|yK+;V|$i0`O/W'Q|qeɸlvg(v33[G$x#kQ7f _&l JNo o8dSɳVuEY_uMDuwi͛϶}kk^9 FogGިxcEj~~/W)]ʮhU#5AvU']ʮW<2|"LAFECR5[488> +endobj +33 0 obj<> +endobj +34 0 obj<> +endobj +35 0 obj<> +endobj +36 0 obj<> +endobj +37 0 obj<> +endobj +38 0 obj<> +endobj +39 0 obj<> +endobj +40 0 obj<> +endobj +41 0 obj<> +endobj +42 0 obj<> +endobj +43 0 obj<>stream + + + + + + + +Microsoft Word - DIO1 rm final.doctomis + + + + + + + + + + + + + + + + + + + + + + + + +endstream +endobj +44 0 obj<> +endobj +xref +0 45 +0000000000 65535 f +0000030709 00000 n +0000030835 00000 n +0000030978 00000 n +0000034739 00000 n +0000034865 00000 n +0000035044 00000 n +0000057377 00000 n +0000057614 00000 n +0000057741 00000 n +0000057895 00000 n +0000064696 00000 n +0000064825 00000 n +0000064981 00000 n +0000075852 00000 n +0000076114 00000 n +0000076243 00000 n +0000076423 00000 n +0000079839 00000 n +0000080074 00000 n +0000080315 00000 n +0000080444 00000 n +0000080600 00000 n +0000087356 00000 n +0000087485 00000 n +0000087629 00000 n +0000096219 00000 n +0000096348 00000 n +0000096504 00000 n +0000105675 00000 n +0000105804 00000 n +0000105948 00000 n +0000109054 00000 n +0000109406 00000 n +0000109764 00000 n +0000109996 00000 n +0000110360 00000 n +0000110620 00000 n +0000110781 00000 n +0000111036 00000 n +0000111404 00000 n +0000111439 00000 n +0000111463 00000 n +0000111576 00000 n +0000114986 00000 n +trailer +<> +startxref +116 +%%EOF Index: phr/trunk/codigo/demos/ref/Dio1b_sch.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: phr/trunk/codigo/demos/ref/Dio1b_sch.pdf =================================================================== --- phr/trunk/codigo/demos/ref/Dio1b_sch.pdf (nonexistent) +++ phr/trunk/codigo/demos/ref/Dio1b_sch.pdf (revision 260)
phr/trunk/codigo/demos/ref/Dio1b_sch.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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