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/trunk/rtl/verilog/T6507LP_FSM.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2009/03/06 19:58:07 creep
// Added some simple logic to a few states. Connection with the ALU is pending.
//
// Revision 1.4 2009/03/06 18:57:12 creep
// Updated file header standard.
//
63,7 → 66,7
`timescale 1ns / 1ps
 
parameter FETCH_OP = 3'b000;
parameter FETCH_1 = 3'b001;
parameter FETCH_LOW = 3'b001;
parameter FETCH_HIGH_TO_PC = 3'b010;
parameter FETCH_HIGH_TO_TEMP = 3'b011;
parameter READ_EFFECTIVE = 3'b100;
70,14 → 73,20
parameter DO_OPERATION = 3'b101;
parameter WRITE_EFFECTIVE = 3'b110;
 
parameter READ = 1'b0;
parameter WRITE = 1'b1;
 
 
 
module t6507lp_fsm(clk_in, n_rst_in, data, address);
module t6507lp_fsm(clk_in, n_rst_in, alu_result, alu_status, data, address, control, alu_opcode, alu_a);
input clk_in;
input n_rst_in;
input [7:0] alu_result;
input alu_status;
inout [7:0] data;
output [12:0] address;
output control; // one bit is enough? read = 0, write = 1
output [7:0] alu_op;
output [7:0] alu_a;
 
reg [12:0] pc;
reg [7:0] sp;
86,9 → 95,9
reg [7:0] temphigh;
reg [7:0] tempdata;
 
reg [3:0] state; // not sure if this will be 4 bits wide
reg [3:0] state, next_state; // not sure if this will be 4 bits wide
always @ (posedge clk_in) begin
always @ (posedge clk_in or negedge n_rst_in) begin
if (n_rst_in == 1'b0) begin
// TODO: all the reset stuff
pc <= 8'h00; // TODO: this is written somewhere. something about a reset vector. must be checked.
99,47 → 108,53
tempdata <= 8'h00;
 
state <= FETCH_OP;
 
end
else begin
 
pc <= pc + 1'b1;
pc <= pc + 1'b1; // TODO: check synthesis for this line
state <= next_state;
 
address <= pc; // this secures the pipelining will happen by default
control <= READ; // but whenever this is not true each cycle must setup these signals
case (state)
FETCH_OP: begin // this state is the simplest one. whenever a instruction is done you must fetch the next op.
FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
// the last cycle was a memory write.
// TODO: bus controller enables memory or cpu enables it?
address = pc;
ir <= data;
//address <= pc;
//control <= READ;
end
FETCH_1: begin
address = pc;
templow <= data;
FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
if (accumulator or implied) begin // the ALU must be used
alu_opcode <= data;
end
else begin
ir <= data; // opcode must be saved in the instruction register
end
end
FETCH_HIGH_TO_PC: begin
address = pc;
pc <= {data[4:0],templow};
FETCH_HIGH: begin
templow <= data; // data from previous cycle is ready and must be saved
if (immediate) begin
alu_opcode <= ir;
alu_a <= data;
end
end
FETCH_HIGH_TO_TEMP: begin
temphigh <= data;
SET_PC: begin
pc <= {data[4:0], templow};
end
READ_EFFECTIVE: begin
address = {temphigh[4:0],templow};
tempdata <= data;
address <= {data[4:0], templow};
end
DO_OPERATION: begin
address = 1'bZ; // TODO: the spec says to write the value again... this means more power used. not sure it is necessay.
// TODO: connect alu here and perform the desired operation
alu_opcode <= ir;
alu_a <= data;
end
WRITE_EFFECTIVE: begin
address = {temphigh[4:0],templow};
data = alu.output;
end
endcase
end
end
 
always @ (*) begin
always @ (state) begin
if (n_rst_in == 1'b0) begin
next_state = FETCH_OP;
end
146,60 → 161,53
else begin
case (state)
FETCH_OP: begin
next_state = FETCH_1;
next_state = FETCH_LOW;
end
FETCH_1: begin
if (implied or immediate) begin
next_state = FETCH_OP;
FETCH_LOW: begin
if (accumulator or implied) begin
next_state = FETCH_OP; // not sure
end
else begin
next_state = FETCH_HIGH;
end
end
FETCH_HIGH: begin
if (immediate) begin
next_state = FETCH_LOW;
end
else if (absolute) begin
if (jump) begin
next_state = FETCH_HIGH_TO_PC;
next_state = SET_PC;
end
else
next_state = FETCH_HIGH_TO_TEMP;
end
else if (zeropage) begin
if (write_operations) begin // STA, STX, STY, SAX
next_state = WRITE_EFFECTIVE;
else if (read) begin // (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, NOP)
next_state = READ_EFFECTIVE;
end
else begin
else if (read_modify_write) begin // (ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP)
next_state = READ_EFFECTIVE;
end
else if (write) begin //(STA, STX, STY, SAX)
 
end
end
end
FETCH_HIGH_TO_PC: begin
next_state = FETCH_OP;
SET_PC, DO_OPERATION: begin
next_state = FETCH_LOW;
end
FETCH_HIGH_TO_TEMP: begin
if (write_operations) begin // STA, STX, STY, SAX
next_state = WRITE_EFFECTIVE;
READ_EFFECTIVE: begin
if (read) begin
next_state = DO_OPERATION;
end
else begin
next_state = READ_EFFECTIVE;
next_state =
end
end
READ_EFFECTIVE: begin
if (read_instructions) begin // (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, ?NOP?)
next_state = FETCH_OP;
end
else begin // this are the Read_Modify_Write_(ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP)
next_state = DO_OPERATION;
end
end
DO_OPERATION: begin
next_state = WRITE_EFFECTIVE;
end
WRITE_EFFECTIVE: begin
next_state = FETCH_OP;
end
 
endcase
end
end
 
// this always block is responsible for updating the address mode
always @ (opcode) begin
always @ (data) begin // TODO: the sensitivity list is not correct
if (state == )
case
end
endmodule

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