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Rev 260 → Rev 261

/trunk/vhdl/reg_bank.vhd
14,9 → 14,6
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--Uncomment following two lines for Xilinx RAM16X1D
library UNISIM; --Xilinx
use UNISIM.vcomponents.all; --Xilinx
 
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
149,6 → 146,7
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
284,167 → 282,4
);
end generate; --altera_mem
 
 
-- Option #5
-- dual_port_mem_coregen:
-- if memory_type = "DUAL_PORT_XILINX" generate
-- reg_file_dp_ram_1: reg_file_dp_ram
-- port map (
-- addra => addr_read1,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out1,
-- web => write_enable);
--
-- reg_file_dp_ram_2: reg_file_dp_ram
-- port map (
-- addra => addr_read2,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out2,
-- web => write_enable);
-- end generate; --dual_port_mem
 
 
-- dual_port_mem_xc4000xla: if memory_type = "DUAL_PORT_XILINX_XC4000XLA" generate
-- reg_file_dp_ram_1: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read1,
-- SPO => open,
-- DPO => data_out1);
--
-- reg_file_dp_ram_2: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read2,
-- SPO => open,
-- DPO => data_out2);
-- end generate; --dual_port_mem
 
 
-- Option #6
-- Generic Two-Port Synchronous RAM
-- generic_tpram can be obtained from:
-- http://www.opencores.org/cvsweb.shtml/generic_memories/
-- Supports ASICs (Artisan, Avant, and Virage) and Xilinx FPGA
-- generic_mem:
-- if memory_type = "OPENCORES_MEM" generate
-- bank1 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read1,
-- di_a => ZERO,
-- do_a => data_out1,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
--
-- bank2 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read2,
-- di_a => ZERO,
-- do_a => data_out2,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
-- end generate; --generic_mem
 
 
-- Option #7
-- Xilinx mode using four 16x16 banks
-- xilinx_mem:
-- if memory_type = "XILINX" generate
-- bank1_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank1_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
-- end generate; --xilinx_mem
 
end; --architecture ram_block

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