URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
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- This comparison shows the changes necessary to convert path
/
- from Rev 261 to Rev 262
- ↔ Reverse comparison
Rev 261 → Rev 262
/t6507lp/trunk/syn/cadence/scripts/LP_io.cmd
1,11 → 1,16
# script written by Samuel N. Pagliarini |
# Cadence Encounter(R) RTL Compiler |
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#set_attr information_level 9 |
#dont use level nine unless you are evaluating the synthesis |
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set SVNPATH /home/nscad/samuel/Desktop/svn_atari/trunk/ |
set FILE_LIST {t6507lp_io.v t6507lp.v t6507lp_alu.v t6507lp_fsm.v} |
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set_attr lp_insert_clock_gating true / |
set_attr lp_insert_operand_isolation true / |
set_attr lp_power_analysis_effort high / |
# controls the switching activity propagation |
set_attr dft_scan_style muxed_scan / |
#set_attr dft_scan_map_mode tdrc_pass / |
# this will force the mapping of all registers that passed dft rules into scannable registers |
18,7 → 23,7
set_attribute avoid false [find / -libcell LGC*] |
set_attribute avoid false [find / -libcell LSG*] |
set_attribute avoid false [find / -libcell LSOGC*] |
#set_attribute avoid true [find / -libcell EN2LX1] |
set_attribute avoid true [find / -libcell EN2LX1] |
# the EN2LX1 cell always reports violations. i have also declared the dont use attribute of the cell in the .lib file |
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set_attribute lef_library {xc06_m3_FE.lef D_CELLSL.lef IO_CELLS.lef} |
28,7 → 33,7
elaborate |
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define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp_io] -port clk] |
set_attribute slew {0 0 1 1} [find / -clock 1MHz] |
set_attribute slew {0 0 100 100} [find / -clock 1MHz] |
external_delay -clock [find / -clock 1MHz] -output 100 [all_outputs] |
external_delay -clock [find / -clock 1MHz] -input 100 [all_inputs] |
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35,12 → 40,13
define_dft shift_enable -active high [find / -port scan_enable] -name SE |
set_attribute lp_clock_gating_test_signal SE /des*/* |
set_attribute lp_clock_gating_extract_common_enable true /des*/* |
set_attribute max_dynamic_power 3000000 /des*/* |
# this command sets the max power at 3mV. The tool will optimize a bit but it wont necessarily reach that goal. |
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#read_vcd simvision.vcd -module t6507lp -static |
#argh |
#check_design -all |
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#report timing -lint |
report timing -lint |
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check_dft_rules |
synthesize -to_generic -effort high |
53,6 → 59,10
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synthesize -incremental -effort high |
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#write_hdl t6507lp_io > gates.v |
check_design -all |
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report timing > ../reports/RC_timing.txt |
report area > ../reports/RC_area.txt |
report power > ../reports/RC_power.txt |
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io t6507lp_io |