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  • This comparison shows the changes necessary to convert path 
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    from Rev 263 to Rev 264
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Rev 263 → Rev 264

/trunk/vhdl/mem_ctrl.vhd
28,10 → 28,13
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
 
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
 
architecture logic of mem_ctrl is
39,6 → 42,8
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
 
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
48,17 → 53,18
 
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
mem_data_r, opcode_reg, next_opcode_reg, mem_state_reg)
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_sel_var : std_logic_vector(3 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_sel_var := "0000";
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
67,13 → 73,13
 
case mem_source is
when MEM_READ32 =>
data_read_var := mem_data_r;
data_read_var := data_r;
 
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := mem_data_r(31 downto 16);
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := mem_data_r(15 downto 0);
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
84,10 → 90,10
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := mem_data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := mem_data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := mem_data_r(15 downto 8);
when others => data_read_var(7 downto 0) := mem_data_r(7 downto 0);
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
97,14 → 103,14
 
when MEM_WRITE32 =>
data_write_var := data_write;
byte_sel_var := "1111";
byte_we_var := "1111";
 
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_sel_var := "1100";
byte_we_var := "1100";
else
byte_sel_var := "0011";
byte_we_var := "0011";
end if;
 
when MEM_WRITE8 =>
113,13 → 119,13
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_sel_var := "1000";
byte_we_var := "1000";
when "01" =>
byte_sel_var := "0100";
byte_we_var := "0100";
when "10" =>
byte_sel_var := "0010";
byte_we_var := "0010";
when others =>
byte_sel_var := "0001";
byte_we_var := "0001";
end case;
 
when others =>
127,7 → 133,7
 
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := mem_data_r;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
137,7 → 143,7
pause_var := '1';
else
address_var := address_pc;
byte_sel_var := "0000";
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
144,10 → 150,10
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_sel_var := "0000";
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_sel_var := "0000";
byte_we_var := "0000";
end if;
end if;
end if;
160,23 → 166,31
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= mem_data_r;
next_opcode_reg <= data_r;
end if;
end if;
end if;
 
mem_address <= address_var;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
mem_data_w <= data_write_var;
mem_byte_we <= byte_sel_var;
 
address_next <= address_var;
byte_we_next <= byte_we_var;
 
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
 
end process; --data_proc
 
end; --architecture logic
/trunk/vhdl/mlite_pack.vhd
109,20 → 109,6
) return std_logic_vector;
 
-- For Altera
COMPONENT lpm_add_sub
GENERIC (
lpm_width : NATURAL;
lpm_direction : STRING := "UNUSED";
lpm_type : STRING;
lpm_hint : STRING);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
add_sub : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
END COMPONENT;
 
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
168,47 → 154,24
end component;
 
-- For Xilinx
component ramb4_s16_s16
port (
clka : in std_logic;
rsta : in std_logic;
addra : in std_logic_vector;
dia : in std_logic_vector;
ena : in std_logic;
wea : in std_logic;
doa : out std_logic_vector;
 
clkb : in std_logic;
rstb : in std_logic;
addrb : in std_logic_vector;
dib : in std_logic_vector;
enb : in std_logic;
web : in std_logic);
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"16");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
 
-- For Xilinx
component reg_file_dp_ram
port (
addra : IN std_logic_VECTOR(4 downto 0);
addrb : IN std_logic_VECTOR(4 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
dinb : IN std_logic_VECTOR(31 downto 0);
douta : OUT std_logic_VECTOR(31 downto 0);
web : IN std_logic);
end component;
 
-- For Xilinx
component reg_file_dp_ram_xc4000xla
port (
A : IN std_logic_vector(4 DOWNTO 0);
DI : IN std_logic_vector(31 DOWNTO 0);
WR_EN : IN std_logic;
WR_CLK : IN std_logic;
DPRA : IN std_logic_vector(4 DOWNTO 0);
SPO : OUT std_logic_vector(31 DOWNTO 0);
DPO : OUT std_logic_vector(31 DOWNTO 0));
end component;
component pc_next
port(clk : in std_logic;
236,11 → 199,14
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
 
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
 
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
 
component control
363,11 → 329,14
reset_in : in std_logic;
intr_in : in std_logic;
 
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
 
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
 
component ram
379,7 → 348,37
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
 
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
pause : out std_logic;
 
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
 
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
 
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
403,9 → 402,9
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
/trunk/vhdl/plasma.vhd
44,9 → 44,9
uart_read : in std_logic;
 
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
54,19 → 54,17
end; --entity plasma
 
architecture logic of plasma is
signal address_reg : std_logic_vector(31 downto 2);
signal data_write_reg : std_logic_vector(31 downto 0);
signal write_byte_enable_reg : std_logic_vector(3 downto 0);
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal mem_address : std_logic_vector(31 downto 2);
signal mem_byte_we : std_logic_vector(3 downto 0);
signal data_r : std_logic_vector(31 downto 0);
signal data_w : std_logic_vector(31 downto 0);
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal mem_pause : std_logic;
 
signal mem_address : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal mem_write_byte_enable : std_logic_vector(3 downto 0);
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal mem_pause : std_logic;
 
signal enable_internal_ram : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
83,11 → 81,10
signal counter_reg : std_logic_vector(31 downto 0);
 
begin --architecture
write_byte_enable <= write_byte_enable_reg;
data_write <= data_write_reg;
address <= address_reg;
 
write_enable <= '1' when write_byte_enable_reg /= "0000" else '0';
address <= mem_address;
byte_we <= mem_byte_we;
data_write <= data_w;
write_enable <= '1' when mem_byte_we /= "0000" else '0';
mem_pause <= mem_pause_in or (uart_write_busy and enable_uart and write_enable);
irq_status <= gpioA_in(31 downto 30) & (gpioA_in(31 downto 30) xor "11") &
counter_reg(18) & not counter_reg(18) &
95,9 → 92,9
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out <= gpio0_reg;
 
enable_internal_ram <= '1' when mem_address(30 downto 28) = "000" else '0';
enable_misc <= '1' when address_reg(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and address_reg(7 downto 4) = "0000" else '0';
enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
 
108,60 → 105,57
reset_in => reset,
intr_in => irq,
mem_address => mem_address,
mem_data_w => mem_data_write,
mem_data_r => mem_data_read,
mem_byte_we => mem_write_byte_enable,
address_next => address_next,
byte_we_next => byte_we_next,
 
address => mem_address,
byte_we => mem_byte_we,
data_w => data_w,
data_r => data_r,
mem_pause => mem_pause);
 
misc_proc: process(clk, reset, mem_address, address_reg, enable_misc,
misc_proc: process(clk, reset, address_next, mem_address, enable_misc,
data_read_ram, data_read, data_read_uart, mem_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
gpioA_in, counter_reg, mem_data_write, data_write_reg)
gpioA_in, counter_reg, data_w)
begin
case address_reg(30 downto 28) is
case mem_address(30 downto 28) is
when "000" => --internal RAM
mem_data_read <= data_read_ram;
data_r <= data_read_ram;
when "001" => --external RAM
mem_data_read <= data_read;
data_r <= data_read;
when "010" => --misc
case address_reg(6 downto 4) is
case mem_address(6 downto 4) is
when "000" => --uart
mem_data_read <= ZERO(31 downto 8) & data_read_uart;
data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
mem_data_read <= ZERO(31 downto 8) & irq_mask_reg;
data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
mem_data_read <= ZERO(31 downto 8) & irq_status;
data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
mem_data_read <= gpio0_reg;
data_r <= gpio0_reg;
when "101" => --gpioA
mem_data_read <= gpioA_in;
data_r <= gpioA_in;
when "110" => --counter
mem_data_read <= counter_reg;
data_r <= counter_reg;
when others =>
mem_data_read <= gpioA_in;
data_r <= gpioA_in;
end case;
when others =>
mem_data_read <= ZERO;
data_r <= ZERO;
end case;
 
if reset = '1' then
address_reg <= ZERO(31 downto 2);
data_write_reg <= ZERO;
write_byte_enable_reg <= ZERO(3 downto 0);
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if mem_pause = '0' then
address_reg <= mem_address(31 downto 2);
data_write_reg <= mem_data_write;
write_byte_enable_reg <= mem_write_byte_enable;
if enable_misc = '1' and write_enable = '1' then
if address_reg(6 downto 4) = "001" then
irq_mask_reg <= data_write_reg(7 downto 0);
elsif address_reg(6 downto 4) = "011" then
gpio0_reg <= data_write_reg;
if mem_address(6 downto 4) = "001" then
irq_mask_reg <= data_w(7 downto 0);
elsif mem_address(6 downto 4) = "011" then
gpio0_reg <= data_w;
end if;
end if;
end if;
174,9 → 168,9
port map (
clk => clk,
enable => enable_internal_ram,
write_byte_enable => mem_write_byte_enable,
address => mem_address(31 downto 2),
data_write => mem_data_write,
write_byte_enable => byte_we_next,
address => address_next,
data_write => data_w,
data_read => data_read_ram);
 
u3_uart: uart
186,7 → 180,7
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => data_write_reg(7 downto 0),
data_in => data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
/trunk/vhdl/mlite_cpu.vhd
57,15 → 57,14
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in mem_byte_we Stages
-- ns mem_address mem_data_w mem_data_r 40 44 48 4c 50
-- 3500 0 0 00000040 00000000 00000000 0 0 0
-- 3600 0 0 00000044 00000000 34040041 0 0 1 0
-- 3700 0 0 00000048 00000000 3405FFFF 0 0 2 1 0
-- 3800 0 0 0000004C 00000000 A0A40000 0 0 2 1 0
-- 3900 0 0 0000FFFC 41414141 00000000 1 0 2 1
-- 4000 0 0 00000050 41414141 XXXXXX41 0 0 3 2 0
-- 4100 0 0 00000054 00000000 00000000 0 0 1
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 1 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 0 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
78,15 → 77,18
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
 
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
 
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
 
architecture logic of mlite_cpu is
150,7 → 152,6
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
mem_address(1 downto 0) <= "00";
 
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
205,11 → 206,14
data_read => c_memory,
pause_out => pause_ctrl,
mem_address => mem_address(31 downto 2),
mem_data_w => mem_data_w,
mem_data_r => mem_data_r,
mem_byte_we => mem_byte_we);
address_next => address_next,
byte_we_next => byte_we_next,
 
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r);
 
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,

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