URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 268 to Rev 269
- ↔ Reverse comparison
Rev 268 → Rev 269
/open8_urisc/trunk/VHDL/Open8_pkg.vhd
42,6 → 42,9
-- memory protection schemes. |
-- Seth Henry 04/16/20 Added the OPEN8_BUS_TYPE record to simplify |
-- peripheral connections. |
-- Seth Henry 10/21/20 Modified the write data path to use separate |
-- enumerated states rather than reuse the .reg field |
-- to improve performance. |
|
library ieee; |
use ieee.std_logic_1164.all; |
235,7 → 238,8
end record; |
|
type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM, |
DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC ); |
DATA_WR_REG, DATA_WR_FLAG, |
DATA_WR_PC_L, DATA_WR_PC_H ); |
|
type DATA_CTRL_TYPE is record |
Src : DP_MODES; |
242,9 → 246,6
Reg : SUBOP_TYPE; |
end record; |
|
constant PC_LSB : SUBOP_TYPE := "000"; |
constant PC_MSB : SUBOP_TYPE := "001"; |
|
type INT_CTRL_TYPE is record |
Mask_Set : std_logic; |
Soft_Ints : INTERRUPT_BUNDLE; |
/open8_urisc/trunk/VHDL/o8_cpu.vhd
258,6 → 258,9
-- Seth Henry 07/10/20 Fixed a bug in the LDO/LDX logic where the register |
-- pair wasn't being incremented properly due to a |
-- missing UPP2 signal to the ALU. |
-- Seth Henry 10/21/20 Modified the write data path to use separate |
-- enumerated states rather than reuse the .reg field |
-- to improve performance. |
|
library ieee; |
use ieee.std_logic_1164.all; |
629,10 → 632,9
ALU_Ctrl.Oper <= ALU_GMSK; |
|
when SOP_JSR => |
CPU_Next_State <= JSR_C1; |
CPU_Next_State <= JSR_C1; |
Cache_Ctrl <= CACHE_OPER1; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= PC_MSB; |
DP_Ctrl.Src <= DATA_WR_PC_H; |
|
when others => null; |
end case; |
979,8 → 981,7
ALU_Ctrl.Oper <= ALU_STP; |
ALU_Ctrl.Reg <= conv_std_logic_vector(PSR_I,3); |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= PC_MSB; |
DP_Ctrl.Src <= DATA_WR_PC_H; |
Ack_D <= '1'; |
|
when JSR_C1 => |
987,8 → 988,7
CPU_Next_State <= JSR_C2; |
Cache_Ctrl <= CACHE_OPER2; |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= PC_LSB; |
DP_Ctrl.Src <= DATA_WR_PC_L; |
|
when JSR_C2 => |
CPU_Next_State <= IPF_C0; |
1198,12 → 1198,13
Open8_Bus.Wr_En <= '1'; |
Open8_Bus.Wr_Data <= Flags; |
|
when DATA_WR_PC => |
when DATA_WR_PC_L => |
Open8_Bus.Wr_En <= '1'; |
Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0); |
|
when DATA_WR_PC_H => |
Open8_Bus.Wr_En <= '1'; |
Open8_Bus.Wr_Data <= Program_Ctr(15 downto 8); |
if( DP_Ctrl.Reg = PC_LSB )then |
Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0); |
end if; |
|
when others => |
null; |