URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 269 to Rev 270
- ↔ Reverse comparison
Rev 269 → Rev 270
/trunk/or1ksim/cpu/common/abstract.c
268,9 → 268,11
|
slp_checkaccess(memaddr, SLP_MEMREAD); |
memaddr = simulate_dc_mmu_load(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
temp = evalsim_mem32(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
return temp; |
} |
|
308,10 → 310,12
{ |
unsigned short temp; |
memaddr = simulate_dc_mmu_load(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
|
temp = evalsim_mem16(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
return temp; |
} |
|
348,10 → 352,12
{ |
unsigned char temp; |
memaddr = simulate_dc_mmu_load(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
|
temp = evalsim_mem8(memaddr); |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
return temp; |
} |
|
385,8 → 391,10
slp_checkaccess(memaddr, SLP_MEMWRITE); |
memaddr = simulate_dc_mmu_store(memaddr); |
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
if (DEBUG_ENABLED) { |
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
} |
|
setsim_mem32(memaddr, value); |
|
427,8 → 435,10
{ |
memaddr = simulate_dc_mmu_store(memaddr); |
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
if (DEBUG_ENABLED) { |
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
} |
|
setsim_mem16(memaddr, value); |
|
465,8 → 475,10
{ |
memaddr = simulate_dc_mmu_store(memaddr); |
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
if (DEBUG_ENABLED) { |
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ |
*breakpoint += CheckDebugUnit(DebugStoreData,value); |
} |
|
setsim_mem8(memaddr, value); |
|
/trunk/or1ksim/cpu/common/parse.c
125,9 → 125,6
|
debug("addprogram 1\n"); |
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,vaddr); /* 22/06/01 MM*/ |
*breakpoint += CheckDebugUnit(DebugStoreData,insn); |
|
setsim_mem32 (vaddr, insn); |
|
if(config.filename) |