OpenCores

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trunk/documentation/RISCMCU_Thesis.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/vhdl/license.txt =================================================================== --- trunk/vhdl/license.txt (revision 27) +++ trunk/vhdl/license.txt (nonexistent) @@ -1,144 +0,0 @@ -GNU LESSER GENERAL PUBLIC LICENSE -Version 2.1, February 1999 - - -Copyright (C) 1991, 1999 Free Software Foundation, Inc. -59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -Everyone is permitted to copy and distribute verbatim copies -of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. It also counts - as the successor of the GNU Library Public License, version 2, hence - the version number 2.1.] - -Preamble -The licenses for most software are designed to take away your freedom to share and change it. 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See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_rom is - port( pc : in std_logic_vector(8 downto 0); - instruction : out std_logic_vector(15 downto 0)); -end v_rom; - -architecture rom of v_rom is - - component LPM_ROM - generic ( - LPM_WIDTH: integer := 16; - LPM_WIDTHAD: integer := 9; - LPM_NUMWORDS: integer := 512; - LPM_FILE: string := "program.mif"; - LPM_ADDRESS_CONTROL: string := "UNREGISTERED"; - LPM_OUTDATA: string := "UNREGISTERED" - ); - port ( - ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); - inclock: IN STD_LOGIC := '0'; - outclock: IN STD_LOGIC := '0'; - memenab: IN STD_LOGIC := '1'; - Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0) - ); - end component; - -signal gnd, vcc : std_logic; - -begin - -vcc <= '1'; -gnd <= '0'; - - v1 : LPM_ROM - port map (address => pc, memenab => vcc, q => instruction); - -end rom; Index: trunk/vhdl/v_iodecoder.vhd =================================================================== --- trunk/vhdl/v_iodecoder.vhd (revision 27) +++ trunk/vhdl/v_iodecoder.vhd (nonexistent) @@ -1,144 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_iodecoder is - port( ioaddr : in integer range 0 to 16#3f#; - rd_io, wr_io : in std_logic; - rd_sreg, wr_sreg : out std_logic; - rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; - rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; - rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; - rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; - rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic - ); -end v_iodecoder; - -architecture iodecoder of v_iodecoder is -begin - -process(rd_io, ioaddr) -begin - - rd_sreg <= '0'; - rd_gimsk <= '0'; - rd_timsk <= '0'; - rd_tifr <= '0'; - rd_mcucr <= '0'; - rd_tccr0 <= '0'; - rd_tcnt0 <= '0'; - - rd_portb <= '0'; - rd_ddrb <= '0'; - rd_pinb <= '0'; - rd_portc <= '0'; - rd_ddrc <= '0'; - rd_pinc <= '0'; - rd_portd <= '0'; - rd_ddrd <= '0'; - rd_pind <= '0'; - - if rd_io = '1' then - case ioaddr is - when 16#3f# => rd_sreg <= '1'; - when 16#3b# => rd_gimsk <= '1'; - when 16#39# => rd_timsk <= '1'; - when 16#38# => rd_tifr <= '1'; - when 16#35# => rd_mcucr <= '1'; - when 16#33# => rd_tccr0 <= '1'; - when 16#32# => rd_tcnt0 <= '1'; - - when 16#18# => rd_portb <= '1'; - when 16#17# => rd_ddrb <= '1'; - when 16#16# => rd_pinb <= '1'; - when 16#15# => rd_portc <= '1'; - when 16#14# => rd_ddrc <= '1'; - when 16#13# => rd_pinc <= '1'; - when 16#12# => rd_portd <= '1'; - when 16#11# => rd_ddrd <= '1'; - when 16#10# => rd_pind <= '1'; - when others => - end case; - end if; -end process; - -process(wr_io, ioaddr) -begin - - wr_sreg <= '0'; - wr_gimsk <= '0'; - wr_timsk <= '0'; - wr_tifr <= '0'; - wr_mcucr <= '0'; - wr_tccr0 <= '0'; - wr_tcnt0 <= '0'; - - wr_portb <= '0'; - wr_ddrb <= '0'; - wr_portc <= '0'; - wr_ddrc <= '0'; - wr_portd <= '0'; - wr_ddrd <= '0'; - - if wr_io = '1' then - case ioaddr is - when 16#3f# => wr_sreg <= '1'; - when 16#3b# => wr_gimsk <= '1'; - when 16#39# => wr_timsk <= '1'; - when 16#38# => wr_tifr <= '1'; - when 16#35# => wr_mcucr <= '1'; - when 16#33# => wr_tccr0 <= '1'; - when 16#32# => wr_tcnt0 <= '1'; - - when 16#18# => wr_portb <= '1'; - when 16#17# => wr_ddrb <= '1'; - when 16#15# => wr_portc <= '1'; - when 16#14# => wr_ddrc <= '1'; - when 16#12# => wr_portd <= '1'; - when 16#11# => wr_ddrd <= '1'; - when others => - end case; - end if; -end process; - -end iodecoder; Index: trunk/vhdl/v_freqdiv.vhd =================================================================== --- trunk/vhdl/v_freqdiv.vhd (revision 27) +++ trunk/vhdl/v_freqdiv.vhd (nonexistent) @@ -1,67 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_freqdiv is - port( clock : in std_logic; - div2, div4, div8, div16 : buffer std_logic); -end v_freqdiv; - -architecture myfreqdiv of v_freqdiv is -begin -process(clock) -begin - if clock'event and clock = '1' then - div2 <= not div2; - if div2 = '1' then - div4 <= not div4; - if div4 = '1' then - div8 <= not div8; - if div8 = '1' then - div16 <= not div16; - end if; - end if; - end if; - end if; -end process; -end myfreqdiv; Index: trunk/vhdl/v_pc.vhd =================================================================== --- trunk/vhdl/v_pc.vhd (revision 27) +++ trunk/vhdl/v_pc.vhd (nonexistent) @@ -1,101 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity v_pc is - port( offset : in std_logic_vector(8 downto 0); - en, addoffset, push, pull, vec2, vec4 : in std_logic; - clk, clrn : in std_logic; - pc : buffer std_logic_vector(8 downto 0) - ); -end v_pc; - -architecture pc of v_pc is -constant vector2 : std_logic_vector(8 downto 0) := "000000001"; -constant vector4 : std_logic_vector(8 downto 0) := "000000010"; -signal pcb, stack0, stack1, stack2, stack3 : std_logic_vector(8 downto 0); -begin - -process(clk, clrn) -begin - if clrn = '0' then - pc <= "000000000"; - pcb <= "000000000"; - stack0 <= "000000000"; - stack1 <= "000000000"; - stack2 <= "000000000"; - stack3 <= "000000000"; - elsif clk'event and clk = '1' then - if en = '1' then - pcb <= pc; - if addoffset = '1' then - pc <= pcb + offset; - elsif pull = '1' then - pc <= stack0; - elsif vec2 = '1' then - pc <= vector2; - elsif vec4 = '1' then - pc <= vector4; - else - pc <= pc + 1; - end if; - - if push = '1' then - if addoffset = '1' then - stack0 <= pcb; - else - stack0 <= pcb - 1; - end if; - stack1 <= stack0; - stack2 <= stack1; - stack3 <= stack2; - elsif pull = '1' then - stack0 <= stack1; - stack1 <= stack2; - stack2 <= stack3; - end if; - end if; - end if; -end process; -end pc; Index: trunk/vhdl/v_riscmcu.vhd =================================================================== --- trunk/vhdl/v_riscmcu.vhd (revision 27) +++ trunk/vhdl/v_riscmcu.vhd (nonexistent) @@ -1,340 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_riscmcu is - port ( - clock : in STD_LOGIC; - reset : in STD_LOGIC; - pinb : inout STD_LOGIC_VECTOR(7 downto 0); - pinc : inout STD_LOGIC_VECTOR(7 downto 0); - pind : inout STD_LOGIC_VECTOR(7 downto 0) - ); -end v_riscmcu; - -architecture riscmcu of v_riscmcu is - -signal ext_irq_pin, ext_timer_clk_pin : std_logic; - -signal clk, clrn, div2, div4, div8, div16 : std_logic; -signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0); - -signal pc, offset : std_logic_vector(8 downto 0); -signal instruction, ir : std_logic_vector(15 downto 0); - -signal skip, en, wr_reg : std_logic; -signal sren : std_logic_vector (6 downto 0); -signal c2a, c2b, add, subcp, logic, right, dir, pass_a : std_logic; -signal wcarry : std_logic; -signal logicsel : integer range 0 to 3; -signal rightsel : integer range 0 to 2; -signal dirsel : integer range 0 to 1; -signal addoffset, push, pull, cpse, skiptest : std_logic; -signal bclr,bset, bld, cbisbi : std_logic; -signal dest, rr, rd : integer range 0 to 15; -signal srsel : integer range 0 to 7; -signal imm_value : std_logic_vector(7 downto 0); - -signal tosr : std_logic_vector (6 downto 0); - -signal vec2, vec4, clr_i, set_i, clr_tov0, clr_intf, timerirq, extirq : std_logic; - -signal rd_sreg,wr_sreg,rd_gimsk,wr_gimsk,rd_timsk, wr_timsk, rd_tifr,wr_tifr : std_logic; -signal rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : std_logic; -signal rd_portb,wr_portb,rd_ddrb,wr_ddrb,rd_pinb : std_logic; -signal rd_portc,wr_portc,rd_ddrc,wr_ddrc,rd_pinc : std_logic; -signal rd_portd,wr_portd,rd_ddrd,wr_ddrd,rd_pind : std_logic; - -signal t_flag, c_flag : std_logic; - -signal vcc, gnd : std_logic; - -signal rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp :std_logic; - -signal bitsel : integer range 0 to 7; -signal set : std_logic; - -signal asel : integer range 0 to 1; -signal bsel : integer range 0 to 3; - - -- Frequency Divider - Divide clock by 2(div2), 4(div4), 8(div8) and 16(div16) - component v_freqdiv - port ( clock : in std_logic; - div2, div4, div8, div16 : buffer std_logic - ); - end component; - - -- Program Counter (9 bit wide) - component v_pc - port ( offset : in std_logic_vector(8 downto 0); - en, addoffset, push, pull, vec2, vec4 : in std_logic; - clk, clrn : in std_logic; - pc : buffer std_logic_vector(8 downto 0) - ); - end component; - - -- Program ROM (512 words) - component v_rom - port ( pc : in std_logic_vector(8 downto 0); - instruction : out std_logic_vector(15 downto 0) - ); - end component; - - -- Instruction Register (16 bit wide) - component v_ir - port ( instruction : in std_logic_vector(15 downto 0); - en, clk, clrn : in std_logic; - ir : buffer std_logic_vector(15 downto 0); - imm_value : out std_logic_vector(7 downto 0); - rd, rr : out integer range 0 to 15 - ); - end component; - - -- Control Unit (with IO address decoder module inside) - component v_controlunit - port ( ir : in std_logic_vector(15 downto 0); - sr : in std_logic_vector(7 downto 0); - clk, clrn : in std_logic; - skip, extirq, timerirq : in std_logic; - - en : buffer std_logic; - wr_reg : buffer std_logic; - rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; - sren : out std_logic_vector (6 downto 0); - - c2a,c2b : out std_logic; - asel : out integer range 0 to 1; - bsel : out integer range 0 to 3; - bitsel : out integer range 0 to 7; - set : out std_logic; - - add, subcp, logic, right, dir, pass_a : out std_logic; - - wcarry : out std_logic; - logicsel : out integer range 0 to 3; - rightsel : out integer range 0 to 2; - dirsel : out integer range 0 to 1; - - addoffset : out std_logic; - push, pull : out std_logic; - - cpse, skiptest : out std_logic; - - bclr,bset : out std_logic; - bld : out std_logic; - - cbisbi : out std_logic; - - vec2, vec4 : buffer std_logic; - - dest : out integer range 0 to 15; - srsel : out integer range 0 to 7; - offset : out std_logic_vector(8 downto 0); - - clr_i, set_i, clr_intf, clr_tov0 : out std_logic; - - rd_sreg, wr_sreg : out std_logic; - rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; - rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; - rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; - rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; - rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic - ); - end component; - - -- General Purpose Register (16 x 8bit) - component v_gpr - port ( c : in std_logic_vector(7 downto 0); - wr_reg, inc_zp, dec_zp : in std_logic; - rd, rr, dest : in integer range 0 to 15; - clk, clrn : in std_logic; - reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) - ); - end component; - - -- ALU - component v_alu - port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); - c2a, c2b : in std_logic; - asel : in integer range 0 to 1; - bsel : in integer range 0 to 3; - - bitsel : in integer range 0 to 7; - set : in std_logic; - c_flag, t_flag : in std_logic; - - add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; - cpse, skiptest : in std_logic; - - wcarry : in std_logic; - logicsel : in integer range 0 to 3; - rightsel : in integer range 0 to 2; - dirsel : in integer range 0 to 1; - - clk, clrn : in std_logic; - - c : buffer std_logic_vector(7 downto 0); - tosr : buffer std_logic_vector (6 downto 0); - skip : out std_logic - ); - end component; - - -- Status Register (8 bit wide, flags are ITHSVNZC) - component v_sr - port ( clk,clrn: in std_logic; - sren,tosr : in std_logic_vector(6 downto 0); - srsel : in integer range 0 to 7; - clr_i,set_i,bset,bclr : in std_logic; - rd_sreg, wr_sreg : in std_logic; - c : inout std_logic_vector(7 downto 0); - sr : inout std_logic_vector(7 downto 0) - ); - end component; - - -- Data RAM (128 bytes) - component v_ram - port ( addrbus : in std_logic_vector(7 downto 0); - rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0) - ); - end component; - - -- Standard 8-bit I/O Port module (all ports share this same module) - component v_port - port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0); - pin : inout std_logic_vector(7 downto 0) - ); - end component; - - -- 8-bit Timer with overflow interrupt request, can drive by external clock source - component v_timer - port ( extpin, clr_tov0 : in std_logic; - rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; - rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0); - timerirq : out std_logic - ); - end component; - - -- External Interrupt - component v_extint - port ( clk, clrn, extpin, clr_intf : in std_logic; - rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; - extirq : out std_logic; - c : inout std_logic_vector(7 downto 0) - ); - end component; - -begin - --U_v_freqdiv: v_freqdiv - -- port map (clock, div2, div4, div8, div16); - - U_v_pc: v_pc - port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc); - - U_v_rom: v_rom - port map (pc, instruction); - - U_v_ir: v_ir - port map (instruction, en, clk, clrn, ir, imm_value, rd, rr); - - U_v_controlunit: v_controlunit - port map (ir, sr, clk, clrn, skip, extirq, timerirq, en, wr_reg, rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp, sren, c2a, c2b, asel, bsel, bitsel, set, add, subcp, logic, right, dir, pass_a, wcarry, logicsel, rightsel, dirsel, addoffset, push, pull, cpse, skiptest, bclr, bset, bld, cbisbi, vec2, vec4, dest, srsel, offset, clr_i, set_i, clr_intf, clr_tov0, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); - - U_v_gpr: v_gpr - port map (c, wr_reg, inc_zp, dec_zp, rd, rr, dest, clk, clrn, reg_rd, reg_rr, addrbus); - - U_v_alu: v_alu - port map (reg_rd, reg_rr, imm_value, c2a, c2b, asel, bsel, bitsel, set, c_flag, t_flag, add, subcp, logic, right, dir, bld, cbisbi, pass_a, cpse, skiptest, wcarry, logicsel, rightsel, dirsel, clk, clrn, c, tosr, skip); - - U_v_sr: v_sr - port map (clk, clrn, sren, tosr, srsel, clr_i, set_i, bset, bclr, rd_sreg, wr_sreg, c, sr); - - U_v_ram: v_ram - port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c); - - U_v_timer: v_timer - port map (ext_timer_clk_pin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq); - - U_v_extint: v_extint - port map (clk, clrn, ext_irq_pin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c); - - -- The same module v_port is used by 3 I/O ports, just the signals are different - U_v_portB: v_port - port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb); - - U_v_portC: v_port - port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc); - - U_v_portD: v_port - port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind); - - -- Global reset, it resets ALL flip-flops and registers to the initial state (normally gnd) - clrn <= reset; - - vcc <= '1'; - gnd <= '0'; - t_flag <= sr(6); - c_flag <= sr(0); - - -- These are the external interrupt request pin and external timer clock source pin - -- They share pins with the I/O ports - -- TIPS: You can use any of the 24 I/O pins, I use pind(7) for my applications - ext_irq_pin <= pind(2); - ext_timer_clk_pin <= pind(4); - - -- When I use the UP1 board, the on-board 25 MHz clock is too fast and - -- I need to divide it by 4 so that the MCU can run - -- For waveform simulation, it does not require division (clk <= clock) - -- TIPS: To have division, uncomment v_freqdiv module instantation on top of the page and - -- assign clk with div2, div4, div8 or div16 - clk <= clock; - - -end riscmcu; - - Index: trunk/vhdl/v_ir.vhd =================================================================== --- trunk/vhdl/v_ir.vhd (revision 27) +++ trunk/vhdl/v_ir.vhd (nonexistent) @@ -1,74 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity v_ir is - port( instruction : in std_logic_vector(15 downto 0); - en, clk, clrn : in std_logic; - ir : buffer std_logic_vector(15 downto 0); - imm_value : out std_logic_vector(7 downto 0); - rd, rr : out integer range 0 to 15 -); -end v_ir; - -architecture ir of v_ir is -begin - -process(clk,clrn) -begin - if clrn = '0' then - ir <= "0000000000000000"; - elsif clk'event and clk = '1' then - if en = '1' then - ir <= instruction; - end if; - end if; -end process; - -imm_value <= ir(11 downto 8) & ir(3 downto 0); -rd <= conv_integer(ir(7 downto 4)); -rr <= conv_integer(ir(3 downto 0)); - -end ir; Index: trunk/vhdl/v_extint.vhd =================================================================== --- trunk/vhdl/v_extint.vhd (revision 27) +++ trunk/vhdl/v_extint.vhd (nonexistent) @@ -1,104 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity v_extint is - port( clk, clrn, extpin, clr_intf : in std_logic; - rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; - extirq : out std_logic; - c : inout std_logic_vector(7 downto 0)); -end v_extint; - -architecture extint of v_extint is - -signal int0, flag, currentstate, laststate : std_logic; -signal isc0 : integer range 0 to 3; - -begin - -c <= "000000" & conv_std_logic_vector(isc0,2) when rd_mcucr = '1' else - '0' & int0 & "000000" when rd_gimsk = '1' else - "ZZZZZZZZ"; - -extirq <= int0 and not extpin when isc0 = 0 else - int0 and flag; - -process(clk, clrn) -begin - if clrn = '0' then - int0 <= '0'; - isc0 <= 0; - currentstate <= '0'; - laststate <= '0'; - elsif clk'event and clk = '1' then - if wr_gimsk = '1' then - int0 <= c(6); - end if; - if wr_mcucr = '1' then - isc0 <= conv_integer(c(1 downto 0)); - end if; - currentstate <= extpin; - laststate <= currentstate; - end if; -end process; - -process(clrn, clr_intf, clk, isc0, currentstate) -begin - if clrn = '0' or clr_intf = '1' then - flag <= '0'; - elsif clk'event and clk = '1' then - if isc0 = 2 then - if currentstate = '0' and laststate = '1' then - flag <= '1'; - end if; - elsif isc0 = 3 then - if currentstate = '1' and laststate = '0' then - flag <= '1'; - end if; - end if; - end if; -end process; - -end extint; Index: trunk/vhdl/program.mif =================================================================== --- trunk/vhdl/program.mif (revision 27) +++ trunk/vhdl/program.mif (nonexistent) @@ -1,45 +0,0 @@ --- Refer to counter.asm and counter.lst in the asm directory - -width = 16; -depth = 512; - -address_radix = hex; -data_radix = hex; - -content begin -[0..1ff]: 0; - -000000:c002; -000001:9508; -000002:9508; -000003:2733; -000004:9530; -000005:bb37; -000006:bb34; -000007:bb31; -000008:e003; -000009:bb08; -00000a:950a; -00000b:3000; -00000c:f7e1; -00000d:2733; -00000e:9513; -00000f:9513; -000010:9513; -000011:bb15; -000012:5011; -000013:1313; -000014:cffc; -000015:2722; -000016:5f2d; -000017:bb22; -000018:952a; -000019:b73f; -00001a:ff31; -00001b:cffb; -00001c:cfff; -00001d:9478; -00001e:9468; - - -end; \ No newline at end of file Index: trunk/vhdl/v_ram.vhd =================================================================== --- trunk/vhdl/v_ram.vhd (revision 27) +++ trunk/vhdl/v_ram.vhd (nonexistent) @@ -1,99 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity v_ram is - port( addrbus : in std_logic_vector(7 downto 0); - rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0) - ); -end entity; - -architecture ram of v_ram is - -component lpm_ram_dq - generic( lpm_width: positive := 8; - lpm_widthad: positive := 8; - lpm_numwords: natural := 256; - lpm_file: string := "ram.mif"; - lpm_indata: string := "unregistered"; - lpm_address_control: string := "unregistered"; - lpm_outdata: string := "unregistered" - ); - port( data: in std_logic_vector(lpm_width-1 downto 0); - address: in std_logic_vector(lpm_widthad-1 downto 0); - we: in std_logic; - inclock: in std_logic := '0'; - outclock: in std_logic := '0'; - q: out std_logic_vector(lpm_width-1 downto 0) - ); -end component; - -signal mar, mbr, ram_out : std_logic_vector(7 downto 0); - -begin - -sram: lpm_ram_dq - port map(data => mbr, address => mar, we => wr_ram, q => ram_out); - -c <= ram_out when rd_ram = '1' else - "ZZZZZZZZ"; - -process(clk,clrn) -begin - if clrn = '0' then - mar <= "00000000"; - mbr <= "00000000"; - elsif clk'event and clk = '1' then - if ld_mbr = '1' then - mbr <= c; - end if; - if ld_mar = '1' then - mar <= addrbus; - end if; - end if; -end process; - -end ram; Index: trunk/vhdl/v_timer.vhd =================================================================== --- trunk/vhdl/v_timer.vhd (revision 27) +++ trunk/vhdl/v_timer.vhd (nonexistent) @@ -1,177 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity v_timer is - port( extpin, clr_tov0 : in std_logic; - rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; - rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0); - timerirq : out std_logic - ); -end v_timer; - -architecture timer of v_timer is - -signal toie0, tov0 : std_logic; -signal cs : integer range 0 to 7; -signal tcnt0 : std_logic_vector(7 downto 0); -signal div1, div2, div4, div8, div16, div32, div64, div128, div256, div512, div1024 : std_logic; -signal timerclk, inc_tcnt0, currentstate, laststate : std_logic; - -begin - --- Timer Interrupt Request -timerirq <= toie0 and tov0; - --- Read 4 Registers -c <= "000000" & toie0 & "0" when rd_timsk = '1' else - "000000" & tov0 & "0" when rd_tifr = '1' else - conv_std_logic_vector(cs,8) when rd_tccr0 = '1' else - tcnt0 when rd_tcnt0 = '1' else - "ZZZZZZZZ"; - --- Select Clock Source -with cs select - timerclk <= '0' when 0, - clk when 1, - div8 when 2, - div64 when 3, - div256 when 4, - div1024 when 5, - not extpin when 6, - extpin when 7; - --- Timer : clear/write 4 registers, increment timer, set overflow flag, sample clock source -process(clrn, clr_tov0, wr_tifr, c, clk) -begin - if clrn = '0' then - toie0 <= '0'; - cs <= 0; - tcnt0 <= "00000000"; - tov0 <= '0'; - currentstate <= '0'; - laststate <= '0'; - - elsif clr_tov0 = '1' or (wr_tifr = '1' and c(1) = '1') then - tov0 <= '0'; - - elsif clk'event and clk = '1' then - - if wr_tcnt0 = '1' then - tcnt0 <= c; - elsif inc_tcnt0 = '1' then - tcnt0 <= tcnt0 + 1; - if tcnt0 = "11111111" then - tov0 <= '1'; - end if; - end if; - - if wr_timsk = '1' then - toie0 <= c(1); - end if; - if wr_tccr0 = '1' then - cs <= conv_integer(c(2 downto 0)); - end if; - - currentstate <= timerclk; - laststate <= currentstate; - - end if; -end process; - --- Detect rising edge -inc_tcnt0 <= '1' when (laststate ='0' and currentstate = '1') or cs = 1 else - '0'; - --- 10 bit prescaler -process(clk, clrn) -begin - if clrn = '0' then - div2 <= '0'; - div4 <= '0'; - div8 <= '0'; - div16 <= '0'; - div32 <= '0'; - div64 <= '0'; - div128 <= '0'; - div256 <= '0'; - div512 <= '0'; - div1024 <= '0'; - - elsif clk'event and clk = '1' then - div2 <= not div2; - if div2 = '1' then - div4 <= not div4; - if div4 = '1' then - div8 <= not div8; - if div8 = '1' then - div16 <= not div16; - if div16 = '1' then - div32 <= not div32; - if div32 = '1' then - div64 <= not div64; - if div64 = '1' then - div128 <= not div128; - if div128 = '1' then - div256 <= not div256; - if div256 = '1' then - div512 <= not div512; - if div512 = '1' then - div1024 <= not div1024; - end if; - end if; - end if; - end if; - end if; - end if; - end if; - end if; - end if; - end if; -end process; - -end timer; Index: trunk/vhdl/v_controlunit.vhd =================================================================== --- trunk/vhdl/v_controlunit.vhd (revision 27) +++ trunk/vhdl/v_controlunit.vhd (nonexistent) @@ -1,533 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity v_controlunit is - port( ir : in std_logic_vector(15 downto 0); - sr : in std_logic_vector(7 downto 0); - clk, clrn : in std_logic; - skip, extirq, timerirq : in std_logic; - - en : buffer std_logic; - wr_reg : buffer std_logic; - rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; - sren : out std_logic_vector (6 downto 0); - - c2a,c2b : out std_logic; - asel : out integer range 0 to 1; - bsel : out integer range 0 to 3; - bitsel : out integer range 0 to 7; - set : out std_logic; - - add, subcp, logic, right, dir, pass_a : out std_logic; - - wcarry : out std_logic; - logicsel : out integer range 0 to 3; - rightsel : out integer range 0 to 2; - dirsel : out integer range 0 to 1; - - addoffset : out std_logic; - push, pull : out std_logic; - - cpse, skiptest : out std_logic; - - bclr,bset : out std_logic; - bld : out std_logic; - - cbisbi : out std_logic; - - vec2, vec4 : buffer std_logic; - - dest : out integer range 0 to 15; - srsel : out integer range 0 to 7; - offset : out std_logic_vector(8 downto 0); - - clr_i, set_i, clr_intf, clr_tov0 : out std_logic; - - rd_sreg, wr_sreg : out std_logic; - rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; - rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; - rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; - rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; - rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic - -); -end v_controlunit; - -architecture controlunit of v_controlunit is - -type statetype is (exes, nop2s, nop1s, lds, sts, cbisbis, sbicss, sleeps); - -signal ibr : std_logic_vector(11 downto 0); -signal state : statetype; -signal one, neg, imm : std_logic; - -signal -cpcm, sbcm, addm, cpsem, cpm, subm, adcm, andm, eorm, orm, movm, -cpim, sbcim, subim, orim, andim, ldm, stm, comm, negm, swapm, incm, -asrm, lsrm, rorm, decm, bsetm, bclrm, retm, retim, sleepm, -cbisbim, sbicsm, inm, outm, rjmpm, rcallm, ldim, -brbcsm, bldm, bstm, sbrcsm, -ld_incm, ld_decm, st_incm, st_decm : std_logic; - -signal ioaddr : integer range 0 to 16#3f#; -signal rd_io, wr_io, break, irq, get_io, wr_ram_fast, branchtest, branch, jmp : std_logic; - - component v_iodecoder - port( ioaddr : in integer range 0 to 16#3f#; - rd_io, wr_io : in std_logic; - rd_sreg, wr_sreg : out std_logic; - rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; - rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; - rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; - rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; - rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic - ); - end component; - -begin - --- Instruction Decoder --- Decode 51 instructions generate 46 'm signals --- Combine brbcs+brbs (brbcs) cbi+sbi (cbisbi) sbrc+sbrs (sbrcs) sbic+sbis (sbics) - -process(ir, wr_reg, get_io, ibr) -begin - -cpcm <= '0'; sbcm <= '0'; addm <= '0'; -cpsem <= '0'; cpm <= '0'; subm <= '0'; adcm <= '0'; -andm <= '0'; eorm <= '0'; orm <= '0'; movm <= '0'; -cpim <= '0'; sbcim <= '0'; subim <= '0'; orim <= '0'; andim <= '0'; -ldm <= '0'; stm <= '0'; comm <= '0'; negm <= '0'; swapm <= '0'; incm <= '0'; -asrm <= '0'; lsrm <= '0'; rorm <= '0'; decm <= '0'; -bsetm <= '0'; bclrm <= '0'; retm <= '0'; retim <= '0'; sleepm <= '0'; -cbisbim <= '0'; sbicsm <= '0'; -inm <= '0'; outm <= '0'; rjmpm <= '0'; rcallm <= '0'; ldim <= '0'; -brbcsm <= '0'; bldm <= '0'; bstm <= '0'; sbrcsm <= '0'; -ld_incm <= '0'; ld_decm <= '0'; st_incm <= '0'; st_decm <= '0'; - -case ir(15 downto 12) is - when "0000" => - if ir(11 downto 10) = "01" then cpcm <= '1'; end if; - if ir(11 downto 10) = "10" then sbcm <= '1'; end if; - if ir(11 downto 10) = "11" then addm <= '1'; end if; - when "0001" => - if ir(11 downto 10) = "00" then cpsem<= '1'; end if; - if ir(11 downto 10) = "01" then cpm <= '1'; end if; - if ir(11 downto 10) = "10" then subm <= '1'; end if; - if ir(11 downto 10) = "11" then adcm <= '1'; end if; - when "0010" => - if ir(11 downto 10) = "00" then andm <= '1'; end if; - if ir(11 downto 10) = "01" then eorm <= '1'; end if; - if ir(11 downto 10) = "10" then orm <= '1'; end if; - if ir(11 downto 10) = "11" then movm <= '1'; end if; - when "0011" => - cpim <= '1'; - when "0100" => - sbcim <= '1'; - when "0101" => - subim <= '1'; - when "0110" => - orim <= '1'; - when "0111" => - andim <= '1'; - when "1000" => - if ir(11 downto 9) = "000" then ldm <= '1'; end if; - if ir(11 downto 9) = "001" then stm <= '1'; end if; - when "1001" => - if ir(11 downto 9) = "000" then - if ir(1 downto 0) = "01" then ld_incm <= '1'; end if; - if ir(1 downto 0) = "10" then ld_decm <= '1'; end if; - end if; - if ir(11 downto 9) = "001" then - if ir(1 downto 0) = "01" then st_incm <= '1'; end if; - if ir(1 downto 0) = "10" then st_decm <= '1'; end if; - end if; - if ir(11 downto 9) = "010" then - case ir(3 downto 0) is - when "0000" => comm <= '1'; - when "0001" => negm <= '1'; - when "0010" => swapm <= '1'; - when "0011" => incm <= '1'; - when "0101" => asrm <= '1'; - when "0110" => lsrm <= '1'; - when "0111" => rorm <= '1'; - when "1010" => decm <= '1'; - when "1000" => - if ir(8 downto 7) = "00" then bsetm <= '1'; end if; - if ir(8 downto 7) = "01" then bclrm <= '1'; end if; - if ir(8 downto 7) & ir(4) = "100" then retm <= '1'; end if; - if ir(8 downto 7) & ir(4) = "101" then retim <= '1'; end if; - if ir(8 downto 7) = "11" then sleepm <= '1'; end if; - when others => - end case; - elsif ir(11 downto 10) = "10" then - if ir(8) = '0' then cbisbim <= '1'; -- cbi, sbi - else sbicsm <= '1'; end if; -- sbic, sbis - end if; - when "1011" => - if ir(11) = '0' then inm <= '1'; - else outm <= '1'; - end if; - when "1100" => - rjmpm <= '1'; - when "1101" => - rcallm <= '1'; - when "1110" => - ldim <= '1'; - when "1111" => - if ir(11) = '0' then brbcsm <= '1'; end if; - if ir(11 downto 9) = "100" then bldm <= '1'; end if; - if ir(11 downto 9) = "101" then bstm <= '1'; end if; - if ir(11 downto 10) = "11" then sbrcsm <= '1'; end if;-- sbrc, sbrs - when others => -end case; - - --- Generate Fetch Stage Signals : C2A and C2B (C2A active also when fetch I/O) -if ((ibr(7 downto 4) = ir(7 downto 4)) and wr_reg = '1') or get_io = '1' then - c2a <= '1'; -else - c2a <= '0'; -end if; - -if (ibr(7 downto 4) = ir(3 downto 0)) and wr_reg = '1' then - c2b <= '1'; -else - c2b <= '0'; -end if; - -end process; - --- Generate wcarry, logicsel, rightsel and dirsel --- Load IBR with IR when EN active -process(clk,clrn) -begin -if clrn = '0' then - ibr <= "000000000000"; - - wcarry <= '0'; - logicsel <= 0; - rightsel <= 0; - dirsel <= 0; - -elsif clk'event and clk = '1' then - if en = '1' then - ibr <= ir(11 downto 0); - end if; - - wcarry <= adcm or sbcm or sbcim or cpcm; - - if orm = '1' or orim = '1' then logicsel <= 1; - elsif eorm = '1' then logicsel <= 2; - elsif comm = '1' then logicsel <= 3; - else logicsel <= 0; - end if; - - if rorm = '1' then rightsel <= 1; - elsif asrm = '1' then rightsel <= 2; - else rightsel <= 0; - end if; - - if swapm = '1' then dirsel <= 1; - else dirsel <= 0; - end if; - -end if; -end process; - - --- Finite State Machine - -irq <= (timerirq or extirq) and sr(7); -break <= branch or skip or irq; - -process(clk, clrn) -begin - -if clrn = '0' then - - state <= exes; - - en <= '1'; get_io <= '0'; - pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; - rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; - ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; - add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; - jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; - bclr <= '0'; bset <= '0'; bld <= '0'; - cpse <= '0'; skiptest <= '0'; - cbisbi <= '0'; - vec2 <= '0'; vec4 <= '0'; set_i <= '0'; - -elsif clk'event and clk = '1' then - - en <= '1'; get_io <= '0'; - pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; - rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; - ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; - add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; - jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; - bclr <= '0'; bset <= '0'; bld <= '0'; - cpse <= '0'; skiptest <= '0'; - cbisbi <= '0'; - vec2 <= '0'; vec4 <= '0'; set_i <= '0'; - - case state is - - when exes => - - if break = '1' then - - if branch = '1' then - state <= nop1s; - - elsif skip = '1' then - - elsif irq = '1' then - state <= nop2s; - push <= '1'; - if extirq = '1' then - vec2 <= '1'; - else - vec4 <= '1'; - end if; - end if; - - else - - if rjmpm = '1' or rcallm = '1' or retm = '1' or retim = '1' then - state <= nop2s; - elsif cbisbim = '1' then - state <= cbisbis; - elsif sbicsm = '1' then - state <= sbicss; - elsif ldm = '1' or ld_incm = '1' or ld_decm = '1' then - state <= lds; - elsif stm = '1' or st_incm = '1' or st_decm = '1' then - state <= sts; - elsif sleepm = '1' then - state <= sleeps; - end if; - - -- PC signals - jmp <= rjmpm or rcallm; -- encoded - push <= rcallm; - pull <= retm or retim; - - -- PC and IR signals - en <= not (cbisbim or sbicsm - or stm or st_incm or st_decm or - ldm or ld_incm or ld_decm); - - -- General Purpose Register File signals - wr_reg <= addm or adcm or incm - or subm or subim or sbcm or sbcim or decm or negm - or andm or andim or orm or orim or eorm or comm - or lsrm or rorm or asrm - or ldim or movm or swapm - or inm; - inc_zp <= ld_incm or st_incm; - dec_zp <= ld_decm or st_decm; - - -- ALU signals - add <= addm or adcm or incm; - subcp <= subm or subim or sbcm or sbcim or decm or negm - or cpm or cpim or cpcm; - logic <= andm or andim or orm or orim or eorm or comm; - right <= lsrm or rorm or asrm; - dir <= ldim or movm or swapm; - bld <= bldm; - pass_a <= outm or stm or st_incm or st_decm; - cpse <= cpsem; - skiptest <= sbrcsm; - - - - -- SR signals - bclr <= bclrm; - bset <= bsetm; - set_i <= retim; - - sren(0) <= addm or adcm - or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm - or comm - or lsrm or rorm or asrm; - - for i in 1 to 4 loop - sren(i) <= addm or adcm or incm - or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or decm or negm - or andm or andim or orm or orim or eorm or comm - or lsrm or rorm or asrm; - end loop; - - sren(5) <= addm or adcm - or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm; - - sren(6) <= bstm; - - -- Data RAM signals - ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm; - ld_mbr <= stm or st_incm or st_decm; - - -- I/O decoder signals - wr_io <= outm; - rd_io <= inm or sbicsm or cbisbim; - if inm = '1' or outm = '1' then - ioaddr <= conv_integer(ir(10 downto 9) & ir(3 downto 0)); - else - ioaddr <= conv_integer('0' & ir(7 downto 3)); - end if; - - - -- Branch Evaluation Unit signal - branchtest <= brbcsm; - - - -- Fetch I/O, generate C2A - get_io <= cbisbim or sbicsm; - - end if; - - when nop2s => - state <= nop1s; - - when nop1s => - state <= exes; - - when cbisbis => - state <= exes; - cbisbi <= '1'; - wr_io <= '1'; - - when sbicss => - state <= exes; - skiptest <= '1'; - - when lds => - state <= exes; - wr_reg <= '1'; - rd_ram <= '1'; - - when sts => - state <= exes; - wr_ram_fast <= '1'; - - when sleeps => - en <= '0'; - if irq = '1' then - en <= '1'; - state <= nop2s; - push <= '1'; - if extirq = '1' then - vec2 <= '1'; - else - vec4 <= '1'; - end if; - end if; - - end case; - -end if; -end process; - --- Generate Delayed WR_RAM signal to avoid writing to wrong address -process(state, wr_ram_fast) -begin - if state = exes then - wr_ram <= wr_ram_fast; - else - wr_ram <= '0'; - end if; -end process; - - --- Branch Evaluation Unit -process(branchtest, sr, ibr) -begin - if branchtest = '1' and (sr(conv_integer(ibr(2 downto 0))) = not ibr(10)) then - branch <= '1'; - else - branch <= '0'; - end if; -end process; - - --- IO address decoder -iodec : v_iodecoder - port map (ioaddr, rd_io, wr_io, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); - - --- Intruction Buffer Register (IBR) to signals ------------------ -dest <= conv_integer(ibr(7 downto 4)); -srsel <= conv_integer(ibr(6 downto 4)); -set <= ibr(9); -bitsel <= conv_integer(ibr(2 downto 0)); -offset <= ibr(8 downto 0) when jmp = '1' else - ibr(9) & ibr(9) & ibr(9 downto 3); - - --- Generate Fetch Stage Signals : ASEL and SEL -imm <= subim or sbcim or cpim or andim or orim or ldim; -one <= incm or decm; -neg <= negm; - -asel <= 1 when neg = '1' and get_io = '0' else - 0; -bsel <= 1 when neg = '1' else - 2 when imm = '1' else - 3 when one = '1' else - 0; - - --- Decode Control Signal -addoffset <= branch or jmp; -- PC -clr_i <= vec2 or vec4; -- PC -clr_intf <= vec2; -- External Interrupt -clr_tov0 <= vec4; -- Timer - -end controlunit; - - Index: trunk/vhdl/v_alu.vhd =================================================================== --- trunk/vhdl/v_alu.vhd (revision 27) +++ trunk/vhdl/v_alu.vhd (nonexistent) @@ -1,295 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -library lpm; -use lpm.lpm_components.all; - -entity v_alu is - port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); - c2a, c2b : in std_logic; - asel : in integer range 0 to 1; - bsel : in integer range 0 to 3; - - bitsel : in integer range 0 to 7; - set : in std_logic; - c_flag, t_flag : in std_logic; - - add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; - cpse, skiptest : in std_logic; - - wcarry : in std_logic; - logicsel : in integer range 0 to 3; - rightsel : in integer range 0 to 2; - dirsel : in integer range 0 to 1; - - clk, clrn : in std_logic; - - c : buffer std_logic_vector(7 downto 0); - tosr : buffer std_logic_vector (6 downto 0); - skip : out std_logic - ); - -end v_alu; - -architecture alu of v_alu is - -signal a, b : std_logic_vector(7 downto 0); - -signal sr : std_logic_vector(6 downto 0); - -signal cin, overflow, cout : std_logic; - -signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0); - -begin - --- Operand Fetch Unit -- - -process(clrn, clk) -begin - if clrn = '0' then - a <= "00000000"; - b <= "00000000"; - elsif clk'event and clk = '1' then - case asel is - when 0 => - if c2a = '1' then - a <= c; - else - a <= reg_rd; - end if; - when 1 => - a <= "00000000"; - end case; - - case bsel is - when 0 => - if c2b = '1' then - b <= c; - else - b <= reg_rr; - end if; - when 1 => - b <= reg_rd; - when 2 => - b <= imm_value; - when 3 => - b <= "00000001"; - end case; - end if; -end process; - - --- Execution Unit -- - -cin <= c_flag when add = '1' and wcarry = '1' else - '0' when add = '1' and wcarry = '0' else - not c_flag when wcarry = '1' else - '1'; - - --- Adder-Subtracter -adder1 : lpm_add_sub - generic map(lpm_width => 8) - port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow); - --- Logic Unit -with logicsel select - logic_out <= a and b when 0, -- and, andi - a or b when 1, -- or, ori - a xor b when 2, -- eor - not a when 3; -- com - --- Shifter -right_out(6 downto 0) <= a(7 downto 1); -with rightsel select - right_out(7) <= '0' when 0, -- lsr - c_flag when 1, -- ror - a(7) when 2; -- asr - --- Direct Unit -with dirsel select - dir_out <= b when 0, -- ldi, mov - (a(3 downto 0) & a(7 downto 4)) when 1; -- swap - --- Bit Loader -process(bld, bitsel, a, t_flag, set) -begin - for i in 0 to 7 loop - if i /= bitsel then - bldcbi_out(i) <= a(i); - elsif bld = '1' then - bldcbi_out(i) <= t_flag; - else - bldcbi_out(i) <= set; - end if; - end loop; -end process; - --- Results to Data Bus -process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a) -begin - - c <= "ZZZZZZZZ"; - - -- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg - if add = '1' or subcp = '1' then - c <= sum; - end if; - - -- and, andi, or, ori, eor, com - if logic = '1' then - c <= logic_out; - end if; - - -- lsr, lsr, asr - if right = '1' then - c <= right_out; - end if; - - -- ldi, mov, swap - if dir = '1' then - c <= dir_out; - end if; - - -- bld, cbisbi - if bld = '1' or cbisbi = '1' then - c <= bldcbi_out; - end if; - - -- out, st z, st z+, st -z - if pass_a = '1' then - c <= a; - end if; - -end process; - - --- Skip Evaluation Unit -- -process(cpse, skiptest, a, b, set, bitsel, c) -begin - - skip <= '0'; - - -- cpse - if cpse = '1' then - if a = b then - skip <= '1'; - end if; - - -- sbrc, sbrs - elsif skiptest = '1' then - if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then - skip <= '1'; - end if; - - end if; -end process; - --- Flags Evaluation Unit -- -process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel) -begin - --- C sr(0) - if add = '1' then - sr(0) <= cout; - elsif right = '1' then - sr(0) <= a(0); - elsif logic = '1' then -- com - sr(0) <= '1'; - else -- subcp - sr(0) <= not cout; - --sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7)); - end if; - --- Z sr(1) - if (add = '1' or subcp = '1') and sum = "00000000" then - sr(1) <= '1'; - elsif logic = '1' and logic_out = "00000000" then - sr(1) <= '1'; - elsif right = '1' and right_out = "00000000" then - sr(1) <= '1'; - else - sr(1) <= '0'; - end if; - --- N sr(2) - if (add = '1' or subcp = '1') and sum(7) = '1' then - sr(2) <= '1'; - elsif logic = '1' and logic_out(7) = '1' then - sr(2) <= '1'; - elsif right = '1' and right_out(7) = '1' then - sr(2) <= '1'; - else - sr(2) <= '0'; - end if; - --- V sr(3) - if right = '1' then - sr(3) <= right_out(7) xor a(0); - elsif logic = '1' then - sr(3) <= '0'; - else - sr(3) <= overflow; - end if; - --- S sr(4) - sr(4) <= sr(2) xor sr(3); - --- H sr(5) - if add = '1' then - sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3)); - else -- subcp - sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3)); - end if; - --- T sr(6) - sr(6) <= a(bitsel); - -end process; - -tosr <= sr; - -end alu; Index: trunk/vhdl/v_port_bit.vhd =================================================================== --- trunk/vhdl/v_port_bit.vhd (revision 27) +++ trunk/vhdl/v_port_bit.vhd (nonexistent) @@ -1,83 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_port_bit is - port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; - clk,clrn : in std_logic; - c : inout std_logic; - pin : inout std_logic - ); -end v_port_bit; - -architecture port_bit of v_port_bit is - -signal datareg, ddr : std_logic; - -begin - -c <= datareg when rd_port = '1' else - ddr when rd_ddr = '1' else - pin when rd_pin = '1' else - 'Z'; - -pin <= datareg when ddr = '1' else - 'Z'; - -process(clrn, clk) -begin - if clrn = '0' then - datareg <= '0'; - ddr <= '0'; - elsif clk'event and clk = '1' then - if wr_port = '1' then - datareg <= c; - end if; - if wr_ddr = '1' then - ddr <= c; - end if; - end if; -end process; - -end port_bit; - Index: trunk/vhdl/v_sr.vhd =================================================================== --- trunk/vhdl/v_sr.vhd (revision 27) +++ trunk/vhdl/v_sr.vhd (nonexistent) @@ -1,86 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_sr is - port( clk,clrn: in std_logic; - sren,tosr : in std_logic_vector(6 downto 0); - srsel : in integer range 0 to 7; - clr_i,set_i,bset,bclr : in std_logic; - rd_sreg, wr_sreg : in std_logic; - c : inout std_logic_vector(7 downto 0); - sr : inout std_logic_vector(7 downto 0) - ); -end v_sr; - -architecture sr of v_sr is -begin - -c <= sr when rd_sreg = '1' else - "ZZZZZZZZ"; - -process(clk,clrn,rd_sreg,sr) -begin - if clrn = '0' then - sr <= "00000000"; - elsif clk'event and clk = '1' then - if wr_sreg = '1' then - sr <= c; - elsif bset = '1' or bclr = '1' then - sr(srsel) <= bset; - elsif clr_i = '1' or set_i = '1' then - sr(7) <= set_i; - else - for i in 0 to 6 loop - if sren(i) = '1' then - sr(i) <= tosr(i); - end if; - end loop; - end if; - end if; - -end process; - -end sr; - - Index: trunk/vhdl/ram.mif =================================================================== --- trunk/vhdl/ram.mif (revision 27) +++ trunk/vhdl/ram.mif (nonexistent) @@ -1,10 +0,0 @@ -width = 8; -depth = 256; - -address_radix = hex; -data_radix = hex; - -content begin -[0..ff]: 0; - -end; \ No newline at end of file Index: trunk/vhdl/v_port.vhd =================================================================== --- trunk/vhdl/v_port.vhd (revision 27) +++ trunk/vhdl/v_port.vhd (nonexistent) @@ -1,71 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity v_port is - port( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; - clk, clrn : in std_logic; - c : inout std_logic_vector(7 downto 0); - pin : inout std_logic_vector(7 downto 0) - ); -end v_port; - -architecture ioport of v_port is - -component v_port_bit - port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; - clk,clrn : in std_logic; - c : inout std_logic; - pin : inout std_logic - ); -end component; - -begin - - g1: - for i in 0 to 7 generate - u1 : v_port_bit - port map (rd_port, wr_port, rd_ddr, wr_ddr, rd_pin, clk, clrn, c(i), pin(i)); - end generate; - -end ioport; Index: trunk/vhdl/v_gpr.vhd =================================================================== --- trunk/vhdl/v_gpr.vhd (revision 27) +++ trunk/vhdl/v_gpr.vhd (nonexistent) @@ -1,87 +0,0 @@ ----------------------------------------------------------------------------- ----- ---- ----- WISHBONE RISCMCU IP Core ---- ----- ---- ----- This file is part of the RISCMCU project ---- ----- http://www.opencores.org/projects/riscmcu/ ---- ----- ---- ----- Description ---- ----- Implementation of a RISC Microcontroller based on Atmel AVR ---- ----- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- ----- ---- ----- Author(s): ---- ----- - Yap Zi He, yapzihe@hotmail.com ---- ----- ---- ----------------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity v_gpr is - port( c : in std_logic_vector(7 downto 0); - wr_reg, inc_zp, dec_zp : in std_logic; - rd, rr, dest : in integer range 0 to 15; - clk, clrn : in std_logic; - reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) - ); -end v_gpr; - -architecture gpr of v_gpr is - -type regfiletype is array (0 to 15) of std_logic_vector(7 downto 0); - -signal reg : regfiletype; - -begin - -addrbus <= reg(14) - 16#61# when dec_zp = '1' else - reg(14) - 16#60#; - -reg_rd <= reg(rd); -reg_rr <= reg(rr); - -process(clk, clrn) -begin - if clrn = '0' then - for i in 0 to 15 loop - reg(i) <= "00000000"; - end loop; - elsif clk'event and clk = '1' then - if wr_reg = '1' then - reg(dest) <= c; - end if; - if inc_zp = '1' then - reg(14) <= reg(14) + 1; - elsif dec_zp = '1' then - reg(14) <= reg(14) - 1; - end if; - end if; -end process; - -end gpr; Index: trunk/asm/memory_game.asm =================================================================== --- trunk/asm/memory_game.asm (revision 27) +++ trunk/asm/memory_game.asm (nonexistent) @@ -1,237 +0,0 @@ -.include "riscmcu.inc" - -.def temp = r16 -.def times = r17 -.def num = r18 -.def stack = r19 -.def counter = r20 -.def life = r22 -.def level = r23 -.def temp2 = r24 - -.cseg - rjmp reset - reti - reti - -reset: - ldi counter,5 - - ser temp - out ddrb,temp ; Port B direction as OUTPUT - out ddrd,temp ; Port D direction as OUTPUT - out portc,temp - out portd,temp - - ldi temp,1 - out tccr0,temp ; set clock as timer clock source - ldi temp,$0F - out ddrc,temp ; PinC[3..0] output, [7..4] input - -start: - ldi life,3 - ldi level,1 - clt ; T = 0, start with correct - - rcall getinput ; hit any key to start the game - rcall showlife - out portB,level ; output level to display - rcall holding ; release? - -nextlevel: - rcall delay ; wait a while before the game is started - rcall showled ; show the LEDs and save it in buffer -nlife: rcall check ; get input and check - brts wrong - rcall greenled - inc level ; when win, level <- level + 1 - out portB,level ; output level to display - rjmp nextlevel -wrong: rcall redled - rcall delay - dec life - rcall showlife - out portb,level - rcall delay - cpi life,0 - breq start - rcall playback - clt - rjmp nlife - - -;******************************************* -; show life -showlife: - mov temp,life - sbr temp,$f0 - out portb,temp - rcall delay - rcall delay - ret - -;******************************************* -; on red leds - -redled: - clr temp - out portc,temp - rcall delay - ser temp - out portc,temp - ret - -;******************************************* -; on green led - -greenled: - cbi portd,7 - rcall delay - sbi portd,7 - ret - - -;******************************************* -; play back the last sequence when wrong - -playback: - rcall init -w10: ld temp,Z+ - out portC,temp - rcall delay - ser temp ; OFF - out portC,temp - ldi counter,1 - rcall delay - dec times - brne w10 - ret - -;******************************************* -; Show sequence of LEDs (base on times), save in buffer - -showled: - rcall init -snext: rcall random ; return in NUM - st Z+,num - out portC,num ; display the LED - rcall delay - ser temp ; OFF - out portC,temp - ldi counter,1 - rcall delay - dec times - brne snext - ret - - -;******************************************* -; wait for input and check -; return T = 0 when corrert, T = 1 when wrong - -check: - rcall init -nextkey: - rcall holding - sei - rcall getinput ; return in NUM - cli - ld temp,Z+ - cpse num,temp - set ; Set T flag if one key is wrong - rcall holding - rcall sdelay - dec times - brne nextkey - ret - -;******************************************* -; still holding the key ? - -holding: - in temp,pinc - cbr temp,$0F - cpi temp,$F0 - brne holding - ret - -;******************************************* -; getinput - -getinput: -g15: in num,pinc - cbr num,$0F ; clear lower nibble - cpi num,$F0 - breq g15 - rcall sdelay - in temp,pinc - cbr temp,$0F - cp temp,num - brne g15 - swap num - ret - -;******************************************* -; 1. Load level to times -; 2. ZP point to start of buffer - -init: mov times,level ; times <- level - ldi ZP,buffer ; ZP <- buffer - ret - -;******************************************* -; Generate Random Num, return in NUM - -random: - in num,tcnt0 -ran: cpi num,4 - brlo rnext - subi num,4 - rjmp ran -rnext: cpi num,0 - brne r10 - ldi num,0b1110 - rjmp rend -r10: cpi num,1 - brne r20 - ldi num,0b1101 - rjmp rend -r20: cpi num,2 - brne r30 - ldi num,0b1011 - rjmp rend -r30: ldi num,0b0111 -rend: in temp,tcnt0 - ror temp - ror temp - out tcnt0,temp - ret - -;******************************************* -delay: - mov stack,ZP -del: ldi ZP,count - ld temp,Z - dec temp - st Z,temp - brne del - ldi ZP,count+1 - ld temp,Z - dec temp - st Z,temp - brne del - dec counter - brne del - ldi counter,5 - mov ZP,stack - ret - -sdelay: - clr temp -sd5: dec temp - brne sd5 - ret -;******************************************* -.dseg -count: .byte 2 -buffer: .byte 20 \ No newline at end of file Index: trunk/asm/counter.lst =================================================================== --- trunk/asm/counter.lst (revision 27) +++ trunk/asm/counter.lst (nonexistent) @@ -1,114 +0,0 @@ - -AVRASM ver. 1.30 COUNTER.ASM Sun Jul 07 15:58:37 2002 - - - ; This program is for simulation purpose - ; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D) - ; There are 3 approaches used in accomplishing the above task - - .include "riscmcu.inc" - - ;***** I/O Register Definitions - - .equ SREG =$3f - .equ GIMSK =$3b - .equ TIMSK =$39 - .equ TIFR =$38 - .equ MCUCR =$35 - .equ TCCR0 =$33 - .equ TCNT0 =$32 - - .equ PORTB =$18 - .equ DDRB =$17 - .equ PINB =$16 - .equ PORTC =$15 - .equ DDRC =$14 - .equ PINC =$13 - .equ PORTD =$12 - .equ DDRD =$11 - .equ PIND =$10 - - - ;***** Bit Definitions - - .equ INT0 =6 - - .equ TOIE0 =1 - - .equ TOV0 =1 - - .equ ISC01 =1 - .equ ISC00 =0 - - .equ CS02 =2 - .equ CS01 =1 - .equ CS00 =0 - - .def ZP =r30 - - - .def B = r16 - .def C = r17 - .def D = r18 - .def TEMP = r19 - - - -000000 c002 rjmp reset ; reset vector -000001 9508 ret ; external interrupt vertor(not use) -000002 9508 ret ; timer overflow interrupt vertor (not use) - - - reset: -000003 2733 clr TEMP ; r19 = 00 -000004 9530 com TEMP ; r19 = FF -000005 bb37 out DDRB,TEMP ; set all Port B pins as output -000006 bb34 out DDRC,TEMP ; set all Port C pins as output -000007 bb31 out DDRD,TEMP ; set all Port D pins as output - - - - ; Approach 1, output to Port B - -000008 e003 ldi B,3 ; r16 = 03 -000009 bb08 again1: out PORTB,B ; Port B now output 03 -00000a 950a dec B ; r16 = r16 - 1 -00000b 3000 cpi B,0 ; if r16 = 0, -00000c f7e1 brne again1 ; branch to again1 - - - - ; Approach 2, output to Port C - -00000d 2733 clr TEMP ; r19 = 00 -00000e 9513 inc C ; r17 = 01 -00000f 9513 inc C ; r17 = 02 -000010 9513 inc C ; r17 = 03 -000011 bb15 again2: out PORTC,C ; Port C now output 03 -000012 5011 subi C,1 ; r17 = r17 - 1 -000013 1313 cpse C,TEMP ; if r17 != r19 (means if r17 != 0), -000014 cffc rjmp again2 ; branch to again2 - - - - ; Approach 3, output to Port D - -000015 2722 clr D ; r18 = 00 -000016 5f2d subi D,-3 ; r18 = r18 - (-3) = 03 -000017 bb22 again3: out PORTD,D ; Port D now output 03 -000018 952a dec D ; r18 = r18 -1 -000019 b73f in TEMP,SREG ; transfer the value of SR to R19 -00001a ff31 sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction -00001b cffb rjmp again3 ; else branch to again3 - - - -00001c cfff end: rjmp end ; Branch Forever -00001d 9478 sei ; (Set I-Bit in SR) This 2 instructions won't execute -00001e 9468 set ; (Set T-Bit in SR) even they are fetched to the IR - - - - - -Assembly complete with no errors. Index: trunk/asm/simple_calculator.asm =================================================================== --- trunk/asm/simple_calculator.asm (revision 27) +++ trunk/asm/simple_calculator.asm (nonexistent) @@ -1,289 +0,0 @@ -.include "riscmcu.inc" - -.def key = r16 -.def temp = r17 -.def B = r18 -.def C = r19 -.def addsub = r24 -.def counter = r25 -.def tcount = r26 -.def led = r27 - -.cseg - rjmp reset - rjmp extint - rjmp timer - -extint: - clr B - clr C - clr addsub - out portb,c - reti - -timer: - in temp,sreg - inc tcount - cpi tcount,24 - brne tback - clr tcount - cpi led,0b10000 - brne t4 - ldi led,0b0001 -t4: com led - out portc,led - com led - lsl led - out sreg,temp -tback: reti - - -reset: - - clr B - clr C - clr addsub - ldi counter,3 - ldi led,0b0001 - - ldi temp,0b11110000 - out ddrd,temp - ser temp - out ddrb,temp ; PORT B as output - out ddrc,temp ; PORT C as output - out portc,temp ; PORT C leds OFF - out portd,temp ; PORT D output HI - out gimsk,temp ; Enable external interrupt - out timsk,temp ; Enable Timer interrupt - ldi temp,5 - out tccr0,temp ; timer clock source = divide by 1024 - - rcall ldtable - sei - -;************************************************* -; Detect Keys - -rescan: rcall sdelay - - sbi portd,6 - cbi portd,4 - ldi zp,table - in key,pind - cbr key,$F0 - cpi key,$0F - brne press - - sbi portd,4 - cbi portd,5 - ldi zp,table+1 - in key,pind - cbr key,$F0 - cpi key,$0F - brne press - - sbi portd,5 - cbi portd,6 - ldi zp,table+2 - in key,pind - cbr key,$F0 - cpi key,$0F - brne press - - rjmp rescan - -press: - rcall sdelay - in temp,pind - cbr temp,$F0 - cpse key,temp - rjmp rescan - sbrs key,1 - subi zp,-3 - sbrs key,2 - subi zp,-6 - sbrs key,3 - subi zp,-9 - ld key,Z - -;************************************************* -; Operation - - cpi key,$A - breq addkey - cpi key,$B - breq subkey - - swap B - cbr B,$0f - add B,key - out portb,B - - rjmp holding - -addkey: - cbr addsub,$01 - rjmp arith - -subkey: - sbr addsub,$01 - -arith: - swap addsub - sbrc addsub,0 - rjmp subf - rcall BCDadd - out portb,C - rcall overflow - clr B - rjmp holding - -subf: - rcall BCDsub - out portb,C - rcall overflow - clr B - rjmp holding - -;************************************************* -; Key press released ? - -holding: - rcall sdelay - in key,pind - cbr key,$F0 - ldi temp,$0F - cpse key,temp - rjmp holding - rjmp rescan - -;************************************************* -; overflow ? - -overflow: - sbrs b,0 - ret - cli - sbi ddrd,7 - cbi portd,7 - rcall delay - sbi portd,7 - cbi ddrd,7 - sei - ret - -;************************************************* -; Short Delay - -sdelay: - clr temp -s10: dec temp - brne s10 - ret - -;************************************************* -; Load Table - -ldtable: - ldi ZP,table - ldi temp,1 - st Z+,temp - ldi temp,2 - st Z+,temp - ldi temp,3 - st Z+,temp - ldi temp,4 - st Z+,temp - ldi temp,5 - st Z+,temp - ldi temp,6 - st Z+,temp - ldi temp,7 - st Z+,temp - ldi temp,8 - st Z+,temp - ldi temp,9 - st Z+,temp - ldi temp,$B - st Z+,temp - ldi temp,0 - st Z+,temp - ldi temp,$A - st Z+,temp - ret - -;******************************************* -delay: -del: ldi ZP,count - ld temp,Z - dec temp - st Z,temp - brne del - ldi ZP,count+1 - ld temp,Z - dec temp - st Z,temp - brne del - dec counter - brne del - ldi counter,3 - ret - -;***** Subroutine Register Variables - -.def BCD1 =r19 ;BCD input value #1 -.def BCD2 =r18 ;BCD input value #2 -.def tmpadd =r16 ;temporary register - -;***** Code - -BCDadd: - ldi tmpadd,6 ;value to be added later - add BCD1,BCD2 ;add the numbers binary - clr BCD2 ;clear BCD carry - brcc add_0 ;if carry not clear - ldi BCD2,1 ; set BCD carry -add_0: brhs add_1 ;if half carry not set - add BCD1,tmpadd ; add 6 to LSD - brhs add_2 ; if half carry not set (LSD <= 9) - subi BCD1,6 ; restore value - rjmp add_2 ;else -add_1: add BCD1,tmpadd ; add 6 to LSD -add_2: swap tmpadd - add BCD1,tmpadd ;add 6 to MSD - brcs add_4 ;if carry not set (MSD <= 9) - sbrs BCD2,0 ; if previous carry not set - subi BCD1,$60 ; restore value -add_3: ret ;else -add_4: ldi BCD2,1 ; set BCD carry - ret - - -;***** Subroutine Register Variables - -.def BCDa =r19 ;BCD input value #1 -.def BCDb =r18 ;BCD input value #2 - -;***** Code - -BCDsub: - sub BCDa,BCDb ;subtract the numbers binary - clr BCDb - brcc sub_0 ;if carry not clear - ldi BCDb,1 ; store carry in BCDB1, bit 0 -sub_0: brhc sub_1 ;if half carry not clear - subi BCDa,$06 ; LSD = LSD - 6 -sub_1: sbrs BCDb,0 ;if previous carry not set - ret ; return - subi BCDa,$60 ;subtract 6 from MSD - ldi BCDb,1 ;set underflow carry - brcc sub_2 ;if carry not clear - ldi BCDb,1 ; clear underflow carry -sub_2: ret - - - - -.dseg -table: .byte 12 -count: .byte 2 \ No newline at end of file Index: trunk/asm/readme.txt =================================================================== --- trunk/asm/readme.txt (revision 27) +++ trunk/asm/readme.txt (nonexistent) @@ -1,61 +0,0 @@ ------ -FILES ------ - -readme.txt This file -simple_calculator.asm A simple calculator program which I use to test RISCMCU -memory_game.asm A simple memory game which I use to test RISCMCU -riscmcu.inc AVR Assembler include file for this RISCMCU -riscmcu.aio AVR Studio I/O View setting file for RISCMCU -counter.asm Simulation DEMO program for RISCMCU, which is - the program contains in program.mif in the vhdl directory - and the program the MCU run in the simulation waveform (simulation directory) -counter.lst List file for counter.asm - - - ------------------ -AVR Assember 1.30 ------------------ - -Click on 'Options...' Menu -1. Select 'Generic Format' under the Output file format (MUST for HEX2MIF to work!) -2. Check the 'Save before assemble' box. - -riscmcu.inc Include File for *.ASM (I/O register and bit definition for this design) - -With an ASM file and the riscmcu.inc file, AVR Assembler generates - -*.hex Hex file : used by HEX2MIF -*.lst Listing file -*.obj Object file : used by AVR Studio for simulation - - --------------- -AVR Studio 3.0 --------------- - -Open the OBJ file, set - -Prog.Memory 512 -Data Memory 256* -EEPROM 0 -I/O Size 64 -Hardware Stack check -Levels 4 -Map I/O in Data Area check -Frequency any - -You can go to Simulator Options (under Options menu) to set this anytime. - -Then press -ALT-0 Registers View -ALT-4 New Memory View -ALT-5 New I/O View, choose riscmcu.aio - -* The design only have 128 bytes of data RAM, but the simulator can not display the 128 locations when I put 128. 256 works, just ignored anything after the valid 128 byes. - - - - - Index: trunk/asm/riscmcu.aio =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/asm/riscmcu.aio =================================================================== --- trunk/asm/riscmcu.aio (revision 27) +++ trunk/asm/riscmcu.aio (nonexistent)

trunk/asm/riscmcu.aio Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/asm/riscmcu.inc =================================================================== --- trunk/asm/riscmcu.inc (revision 27) +++ trunk/asm/riscmcu.inc (nonexistent) @@ -1,39 +0,0 @@ - -;***** I/O Register Definitions - -.equ SREG =$3f -.equ GIMSK =$3b -.equ TIMSK =$39 -.equ TIFR =$38 -.equ MCUCR =$35 -.equ TCCR0 =$33 -.equ TCNT0 =$32 - -.equ PORTB =$18 -.equ DDRB =$17 -.equ PINB =$16 -.equ PORTC =$15 -.equ DDRC =$14 -.equ PINC =$13 -.equ PORTD =$12 -.equ DDRD =$11 -.equ PIND =$10 - - -;***** Bit Definitions - -.equ INT0 =6 - -.equ TOIE0 =1 - -.equ TOV0 =1 - -.equ ISC01 =1 -.equ ISC00 =0 - -.equ CS02 =2 -.equ CS01 =1 -.equ CS00 =0 - -.def ZP =r30 - Index: trunk/asm/counter.asm =================================================================== --- trunk/asm/counter.asm (revision 27) +++ trunk/asm/counter.asm (nonexistent) @@ -1,69 +0,0 @@ -; This program is for simulation purpose -; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D) -; There are 3 approaches used in accomplishing the above task - -.include "riscmcu.inc" - -.def B = r16 -.def C = r17 -.def D = r18 -.def TEMP = r19 - - - - rjmp reset ; reset vector - ret ; external interrupt vertor(not use) - ret ; timer overflow interrupt vertor (not use) - - -reset: - clr TEMP ; r19 = 00 - com TEMP ; r19 = FF - out DDRB,TEMP ; set all Port B pins as output - out DDRC,TEMP ; set all Port C pins as output - out DDRD,TEMP ; set all Port D pins as output - - - -; Approach 1, output to Port B - - ldi B,3 ; r16 = 03 -again1: out PORTB,B ; Port B now output 03 - dec B ; r16 = r16 - 1 - cpi B,0 ; if r16 = 0, - brne again1 ; branch to again1 - - - -; Approach 2, output to Port C - - clr TEMP ; r19 = 00 - inc C ; r17 = 01 - inc C ; r17 = 02 - inc C ; r17 = 03 -again2: out PORTC,C ; Port C now output 03 - subi C,1 ; r17 = r17 - 1 - cpse C,TEMP ; if r17 != r19 (means if r17 != 0), - rjmp again2 ; branch to again2 - - - -; Approach 3, output to Port D - - clr D ; r18 = 00 - subi D,-3 ; r18 = r18 - (-3) = 03 -again3: out PORTD,D ; Port D now output 03 - dec D ; r18 = r18 -1 - in TEMP,SREG ; transfer the value of SR to R19 - sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction - rjmp again3 ; else branch to again3 - - - -end: rjmp end ; Branch Forever - sei ; (Set I-Bit in SR) This 2 instructions won't execute - set ; (Set T-Bit in SR) even they are fetched to the IR - - - - Index: trunk/hex2mif/readme.txt =================================================================== --- trunk/hex2mif/readme.txt (revision 27) +++ trunk/hex2mif/readme.txt (nonexistent) @@ -1,14 +0,0 @@ -hex2mif.exe Program itself -hex2mif.c C source code - ------ -Usage ------ - -hex2mif [filename] - -input: -HEX file from AVR Assember (Generic Format) - -output: -MIF file named 'progam.mif' for MAX+plus II Index: trunk/hex2mif/hex2mif.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/hex2mif/hex2mif.exe =================================================================== --- trunk/hex2mif/hex2mif.exe (revision 27) +++ trunk/hex2mif/hex2mif.exe (nonexistent)

trunk/hex2mif/hex2mif.exe Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/hex2mif/hex2mif.c =================================================================== --- trunk/hex2mif/hex2mif.c (revision 27) +++ trunk/hex2mif/hex2mif.c (nonexistent) @@ -1,49 +0,0 @@ -#include -#include - -void process(FILE *, FILE *); -void prn_info(); - -int main(int argc, char **argv) -{ - FILE *ifp, *ofp; - - if (argc != 2) { - prn_info(); - exit(1); - } - - ifp = fopen(argv[1], "r"); - ofp = fopen("program.mif", "w"); - process(ifp, ofp); - fclose(ifp); - fclose(ofp); - return 0; -} - -void process(FILE *ifp, FILE *ofp) -{ - int c; - - fprintf(ofp, "width = 16;\ndepth = 512;\n\n" - "address_radix = hex;\ndata_radix = hex;\n\n" - "content begin\n[0..1ff]: 0;\n\n"); - - while((c = getc(ifp)) != EOF) { - if (c != '\n') - putc(c, ofp); - else { - putc(';', ofp); - putc(c, ofp); - } - } - - fprintf(ofp, "\n\nend;"); - - printf("Mission Accomplished"); -} - -void prn_info() -{ - printf("Mission Failed"); -} Index: RISCMCU/trunk/asm/readme.txt =================================================================== --- RISCMCU/trunk/asm/readme.txt (nonexistent) +++ RISCMCU/trunk/asm/readme.txt (revision 28) @@ -0,0 +1,61 @@ +----- +FILES +----- + +readme.txt This file +simple_calculator.asm A simple calculator program which I use to test RISCMCU +memory_game.asm A simple memory game which I use to test RISCMCU +riscmcu.inc AVR Assembler include file for this RISCMCU +riscmcu.aio AVR Studio I/O View setting file for RISCMCU +counter.asm Simulation DEMO program for RISCMCU, which is + the program contains in program.mif in the vhdl directory + and the program the MCU run in the simulation waveform (simulation directory) +counter.lst List file for counter.asm + + + +----------------- +AVR Assember 1.30 +----------------- + +Click on 'Options...' Menu +1. Select 'Generic Format' under the Output file format (MUST for HEX2MIF to work!) +2. Check the 'Save before assemble' box. + +riscmcu.inc Include File for *.ASM (I/O register and bit definition for this design) + +With an ASM file and the riscmcu.inc file, AVR Assembler generates + +*.hex Hex file : used by HEX2MIF +*.lst Listing file +*.obj Object file : used by AVR Studio for simulation + + +-------------- +AVR Studio 3.0 +-------------- + +Open the OBJ file, set + +Prog.Memory 512 +Data Memory 256* +EEPROM 0 +I/O Size 64 +Hardware Stack check +Levels 4 +Map I/O in Data Area check +Frequency any + +You can go to Simulator Options (under Options menu) to set this anytime. + +Then press +ALT-0 Registers View +ALT-4 New Memory View +ALT-5 New I/O View, choose riscmcu.aio + +* The design only have 128 bytes of data RAM, but the simulator can not display the 128 locations when I put 128. 256 works, just ignored anything after the valid 128 byes. + + + + + Index: RISCMCU/trunk/asm/counter.lst =================================================================== --- RISCMCU/trunk/asm/counter.lst (nonexistent) +++ RISCMCU/trunk/asm/counter.lst (revision 28) @@ -0,0 +1,114 @@ + +AVRASM ver. 1.30 COUNTER.ASM Sun Jul 07 15:58:37 2002 + + + ; This program is for simulation purpose + ; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D) + ; There are 3 approaches used in accomplishing the above task + + .include "riscmcu.inc" + + ;***** I/O Register Definitions + + .equ SREG =$3f + .equ GIMSK =$3b + .equ TIMSK =$39 + .equ TIFR =$38 + .equ MCUCR =$35 + .equ TCCR0 =$33 + .equ TCNT0 =$32 + + .equ PORTB =$18 + .equ DDRB =$17 + .equ PINB =$16 + .equ PORTC =$15 + .equ DDRC =$14 + .equ PINC =$13 + .equ PORTD =$12 + .equ DDRD =$11 + .equ PIND =$10 + + + ;***** Bit Definitions + + .equ INT0 =6 + + .equ TOIE0 =1 + + .equ TOV0 =1 + + .equ ISC01 =1 + .equ ISC00 =0 + + .equ CS02 =2 + .equ CS01 =1 + .equ CS00 =0 + + .def ZP =r30 + + + .def B = r16 + .def C = r17 + .def D = r18 + .def TEMP = r19 + + + +000000 c002 rjmp reset ; reset vector +000001 9508 ret ; external interrupt vertor(not use) +000002 9508 ret ; timer overflow interrupt vertor (not use) + + + reset: +000003 2733 clr TEMP ; r19 = 00 +000004 9530 com TEMP ; r19 = FF +000005 bb37 out DDRB,TEMP ; set all Port B pins as output +000006 bb34 out DDRC,TEMP ; set all Port C pins as output +000007 bb31 out DDRD,TEMP ; set all Port D pins as output + + + + ; Approach 1, output to Port B + +000008 e003 ldi B,3 ; r16 = 03 +000009 bb08 again1: out PORTB,B ; Port B now output 03 +00000a 950a dec B ; r16 = r16 - 1 +00000b 3000 cpi B,0 ; if r16 = 0, +00000c f7e1 brne again1 ; branch to again1 + + + + ; Approach 2, output to Port C + +00000d 2733 clr TEMP ; r19 = 00 +00000e 9513 inc C ; r17 = 01 +00000f 9513 inc C ; r17 = 02 +000010 9513 inc C ; r17 = 03 +000011 bb15 again2: out PORTC,C ; Port C now output 03 +000012 5011 subi C,1 ; r17 = r17 - 1 +000013 1313 cpse C,TEMP ; if r17 != r19 (means if r17 != 0), +000014 cffc rjmp again2 ; branch to again2 + + + + ; Approach 3, output to Port D + +000015 2722 clr D ; r18 = 00 +000016 5f2d subi D,-3 ; r18 = r18 - (-3) = 03 +000017 bb22 again3: out PORTD,D ; Port D now output 03 +000018 952a dec D ; r18 = r18 -1 +000019 b73f in TEMP,SREG ; transfer the value of SR to R19 +00001a ff31 sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction +00001b cffb rjmp again3 ; else branch to again3 + + + +00001c cfff end: rjmp end ; Branch Forever +00001d 9478 sei ; (Set I-Bit in SR) This 2 instructions won't execute +00001e 9468 set ; (Set T-Bit in SR) even they are fetched to the IR + + + + + +Assembly complete with no errors. Index: RISCMCU/trunk/asm/counter.asm =================================================================== --- RISCMCU/trunk/asm/counter.asm (nonexistent) +++ RISCMCU/trunk/asm/counter.asm (revision 28) @@ -0,0 +1,69 @@ +; This program is for simulation purpose +; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D) +; There are 3 approaches used in accomplishing the above task + +.include "riscmcu.inc" + +.def B = r16 +.def C = r17 +.def D = r18 +.def TEMP = r19 + + + + rjmp reset ; reset vector + ret ; external interrupt vertor(not use) + ret ; timer overflow interrupt vertor (not use) + + +reset: + clr TEMP ; r19 = 00 + com TEMP ; r19 = FF + out DDRB,TEMP ; set all Port B pins as output + out DDRC,TEMP ; set all Port C pins as output + out DDRD,TEMP ; set all Port D pins as output + + + +; Approach 1, output to Port B + + ldi B,3 ; r16 = 03 +again1: out PORTB,B ; Port B now output 03 + dec B ; r16 = r16 - 1 + cpi B,0 ; if r16 = 0, + brne again1 ; branch to again1 + + + +; Approach 2, output to Port C + + clr TEMP ; r19 = 00 + inc C ; r17 = 01 + inc C ; r17 = 02 + inc C ; r17 = 03 +again2: out PORTC,C ; Port C now output 03 + subi C,1 ; r17 = r17 - 1 + cpse C,TEMP ; if r17 != r19 (means if r17 != 0), + rjmp again2 ; branch to again2 + + + +; Approach 3, output to Port D + + clr D ; r18 = 00 + subi D,-3 ; r18 = r18 - (-3) = 03 +again3: out PORTD,D ; Port D now output 03 + dec D ; r18 = r18 -1 + in TEMP,SREG ; transfer the value of SR to R19 + sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction + rjmp again3 ; else branch to again3 + + + +end: rjmp end ; Branch Forever + sei ; (Set I-Bit in SR) This 2 instructions won't execute + set ; (Set T-Bit in SR) even they are fetched to the IR + + + + Index: RISCMCU/trunk/asm/riscmcu.aio =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: RISCMCU/trunk/asm/riscmcu.aio =================================================================== --- RISCMCU/trunk/asm/riscmcu.aio (nonexistent) +++ RISCMCU/trunk/asm/riscmcu.aio (revision 28)

RISCMCU/trunk/asm/riscmcu.aio Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: RISCMCU/trunk/asm/riscmcu.inc =================================================================== --- RISCMCU/trunk/asm/riscmcu.inc (nonexistent) +++ RISCMCU/trunk/asm/riscmcu.inc (revision 28) @@ -0,0 +1,39 @@ + +;***** I/O Register Definitions + +.equ SREG =$3f +.equ GIMSK =$3b +.equ TIMSK =$39 +.equ TIFR =$38 +.equ MCUCR =$35 +.equ TCCR0 =$33 +.equ TCNT0 =$32 + +.equ PORTB =$18 +.equ DDRB =$17 +.equ PINB =$16 +.equ PORTC =$15 +.equ DDRC =$14 +.equ PINC =$13 +.equ PORTD =$12 +.equ DDRD =$11 +.equ PIND =$10 + + +;***** Bit Definitions + +.equ INT0 =6 + +.equ TOIE0 =1 + +.equ TOV0 =1 + +.equ ISC01 =1 +.equ ISC00 =0 + +.equ CS02 =2 +.equ CS01 =1 +.equ CS00 =0 + +.def ZP =r30 + Index: RISCMCU/trunk/asm/memory_game.asm =================================================================== --- RISCMCU/trunk/asm/memory_game.asm (nonexistent) +++ RISCMCU/trunk/asm/memory_game.asm (revision 28) @@ -0,0 +1,237 @@ +.include "riscmcu.inc" + +.def temp = r16 +.def times = r17 +.def num = r18 +.def stack = r19 +.def counter = r20 +.def life = r22 +.def level = r23 +.def temp2 = r24 + +.cseg + rjmp reset + reti + reti + +reset: + ldi counter,5 + + ser temp + out ddrb,temp ; Port B direction as OUTPUT + out ddrd,temp ; Port D direction as OUTPUT + out portc,temp + out portd,temp + + ldi temp,1 + out tccr0,temp ; set clock as timer clock source + ldi temp,$0F + out ddrc,temp ; PinC[3..0] output, [7..4] input + +start: + ldi life,3 + ldi level,1 + clt ; T = 0, start with correct + + rcall getinput ; hit any key to start the game + rcall showlife + out portB,level ; output level to display + rcall holding ; release? + +nextlevel: + rcall delay ; wait a while before the game is started + rcall showled ; show the LEDs and save it in buffer +nlife: rcall check ; get input and check + brts wrong + rcall greenled + inc level ; when win, level <- level + 1 + out portB,level ; output level to display + rjmp nextlevel +wrong: rcall redled + rcall delay + dec life + rcall showlife + out portb,level + rcall delay + cpi life,0 + breq start + rcall playback + clt + rjmp nlife + + +;******************************************* +; show life +showlife: + mov temp,life + sbr temp,$f0 + out portb,temp + rcall delay + rcall delay + ret + +;******************************************* +; on red leds + +redled: + clr temp + out portc,temp + rcall delay + ser temp + out portc,temp + ret + +;******************************************* +; on green led + +greenled: + cbi portd,7 + rcall delay + sbi portd,7 + ret + + +;******************************************* +; play back the last sequence when wrong + +playback: + rcall init +w10: ld temp,Z+ + out portC,temp + rcall delay + ser temp ; OFF + out portC,temp + ldi counter,1 + rcall delay + dec times + brne w10 + ret + +;******************************************* +; Show sequence of LEDs (base on times), save in buffer + +showled: + rcall init +snext: rcall random ; return in NUM + st Z+,num + out portC,num ; display the LED + rcall delay + ser temp ; OFF + out portC,temp + ldi counter,1 + rcall delay + dec times + brne snext + ret + + +;******************************************* +; wait for input and check +; return T = 0 when corrert, T = 1 when wrong + +check: + rcall init +nextkey: + rcall holding + sei + rcall getinput ; return in NUM + cli + ld temp,Z+ + cpse num,temp + set ; Set T flag if one key is wrong + rcall holding + rcall sdelay + dec times + brne nextkey + ret + +;******************************************* +; still holding the key ? + +holding: + in temp,pinc + cbr temp,$0F + cpi temp,$F0 + brne holding + ret + +;******************************************* +; getinput + +getinput: +g15: in num,pinc + cbr num,$0F ; clear lower nibble + cpi num,$F0 + breq g15 + rcall sdelay + in temp,pinc + cbr temp,$0F + cp temp,num + brne g15 + swap num + ret + +;******************************************* +; 1. Load level to times +; 2. ZP point to start of buffer + +init: mov times,level ; times <- level + ldi ZP,buffer ; ZP <- buffer + ret + +;******************************************* +; Generate Random Num, return in NUM + +random: + in num,tcnt0 +ran: cpi num,4 + brlo rnext + subi num,4 + rjmp ran +rnext: cpi num,0 + brne r10 + ldi num,0b1110 + rjmp rend +r10: cpi num,1 + brne r20 + ldi num,0b1101 + rjmp rend +r20: cpi num,2 + brne r30 + ldi num,0b1011 + rjmp rend +r30: ldi num,0b0111 +rend: in temp,tcnt0 + ror temp + ror temp + out tcnt0,temp + ret + +;******************************************* +delay: + mov stack,ZP +del: ldi ZP,count + ld temp,Z + dec temp + st Z,temp + brne del + ldi ZP,count+1 + ld temp,Z + dec temp + st Z,temp + brne del + dec counter + brne del + ldi counter,5 + mov ZP,stack + ret + +sdelay: + clr temp +sd5: dec temp + brne sd5 + ret +;******************************************* +.dseg +count: .byte 2 +buffer: .byte 20 \ No newline at end of file Index: RISCMCU/trunk/asm/simple_calculator.asm =================================================================== --- RISCMCU/trunk/asm/simple_calculator.asm (nonexistent) +++ RISCMCU/trunk/asm/simple_calculator.asm (revision 28) @@ -0,0 +1,289 @@ +.include "riscmcu.inc" + +.def key = r16 +.def temp = r17 +.def B = r18 +.def C = r19 +.def addsub = r24 +.def counter = r25 +.def tcount = r26 +.def led = r27 + +.cseg + rjmp reset + rjmp extint + rjmp timer + +extint: + clr B + clr C + clr addsub + out portb,c + reti + +timer: + in temp,sreg + inc tcount + cpi tcount,24 + brne tback + clr tcount + cpi led,0b10000 + brne t4 + ldi led,0b0001 +t4: com led + out portc,led + com led + lsl led + out sreg,temp +tback: reti + + +reset: + + clr B + clr C + clr addsub + ldi counter,3 + ldi led,0b0001 + + ldi temp,0b11110000 + out ddrd,temp + ser temp + out ddrb,temp ; PORT B as output + out ddrc,temp ; PORT C as output + out portc,temp ; PORT C leds OFF + out portd,temp ; PORT D output HI + out gimsk,temp ; Enable external interrupt + out timsk,temp ; Enable Timer interrupt + ldi temp,5 + out tccr0,temp ; timer clock source = divide by 1024 + + rcall ldtable + sei + +;************************************************* +; Detect Keys + +rescan: rcall sdelay + + sbi portd,6 + cbi portd,4 + ldi zp,table + in key,pind + cbr key,$F0 + cpi key,$0F + brne press + + sbi portd,4 + cbi portd,5 + ldi zp,table+1 + in key,pind + cbr key,$F0 + cpi key,$0F + brne press + + sbi portd,5 + cbi portd,6 + ldi zp,table+2 + in key,pind + cbr key,$F0 + cpi key,$0F + brne press + + rjmp rescan + +press: + rcall sdelay + in temp,pind + cbr temp,$F0 + cpse key,temp + rjmp rescan + sbrs key,1 + subi zp,-3 + sbrs key,2 + subi zp,-6 + sbrs key,3 + subi zp,-9 + ld key,Z + +;************************************************* +; Operation + + cpi key,$A + breq addkey + cpi key,$B + breq subkey + + swap B + cbr B,$0f + add B,key + out portb,B + + rjmp holding + +addkey: + cbr addsub,$01 + rjmp arith + +subkey: + sbr addsub,$01 + +arith: + swap addsub + sbrc addsub,0 + rjmp subf + rcall BCDadd + out portb,C + rcall overflow + clr B + rjmp holding + +subf: + rcall BCDsub + out portb,C + rcall overflow + clr B + rjmp holding + +;************************************************* +; Key press released ? + +holding: + rcall sdelay + in key,pind + cbr key,$F0 + ldi temp,$0F + cpse key,temp + rjmp holding + rjmp rescan + +;************************************************* +; overflow ? + +overflow: + sbrs b,0 + ret + cli + sbi ddrd,7 + cbi portd,7 + rcall delay + sbi portd,7 + cbi ddrd,7 + sei + ret + +;************************************************* +; Short Delay + +sdelay: + clr temp +s10: dec temp + brne s10 + ret + +;************************************************* +; Load Table + +ldtable: + ldi ZP,table + ldi temp,1 + st Z+,temp + ldi temp,2 + st Z+,temp + ldi temp,3 + st Z+,temp + ldi temp,4 + st Z+,temp + ldi temp,5 + st Z+,temp + ldi temp,6 + st Z+,temp + ldi temp,7 + st Z+,temp + ldi temp,8 + st Z+,temp + ldi temp,9 + st Z+,temp + ldi temp,$B + st Z+,temp + ldi temp,0 + st Z+,temp + ldi temp,$A + st Z+,temp + ret + +;******************************************* +delay: +del: ldi ZP,count + ld temp,Z + dec temp + st Z,temp + brne del + ldi ZP,count+1 + ld temp,Z + dec temp + st Z,temp + brne del + dec counter + brne del + ldi counter,3 + ret + +;***** Subroutine Register Variables + +.def BCD1 =r19 ;BCD input value #1 +.def BCD2 =r18 ;BCD input value #2 +.def tmpadd =r16 ;temporary register + +;***** Code + +BCDadd: + ldi tmpadd,6 ;value to be added later + add BCD1,BCD2 ;add the numbers binary + clr BCD2 ;clear BCD carry + brcc add_0 ;if carry not clear + ldi BCD2,1 ; set BCD carry +add_0: brhs add_1 ;if half carry not set + add BCD1,tmpadd ; add 6 to LSD + brhs add_2 ; if half carry not set (LSD <= 9) + subi BCD1,6 ; restore value + rjmp add_2 ;else +add_1: add BCD1,tmpadd ; add 6 to LSD +add_2: swap tmpadd + add BCD1,tmpadd ;add 6 to MSD + brcs add_4 ;if carry not set (MSD <= 9) + sbrs BCD2,0 ; if previous carry not set + subi BCD1,$60 ; restore value +add_3: ret ;else +add_4: ldi BCD2,1 ; set BCD carry + ret + + +;***** Subroutine Register Variables + +.def BCDa =r19 ;BCD input value #1 +.def BCDb =r18 ;BCD input value #2 + +;***** Code + +BCDsub: + sub BCDa,BCDb ;subtract the numbers binary + clr BCDb + brcc sub_0 ;if carry not clear + ldi BCDb,1 ; store carry in BCDB1, bit 0 +sub_0: brhc sub_1 ;if half carry not clear + subi BCDa,$06 ; LSD = LSD - 6 +sub_1: sbrs BCDb,0 ;if previous carry not set + ret ; return + subi BCDa,$60 ;subtract 6 from MSD + ldi BCDb,1 ;set underflow carry + brcc sub_2 ;if carry not clear + ldi BCDb,1 ; clear underflow carry +sub_2: ret + + + + +.dseg +table: .byte 12 +count: .byte 2 \ No newline at end of file Index: RISCMCU/trunk/vhdl/program.mif =================================================================== --- RISCMCU/trunk/vhdl/program.mif (nonexistent) +++ RISCMCU/trunk/vhdl/program.mif (revision 28) @@ -0,0 +1,45 @@ +-- Refer to counter.asm and counter.lst in the asm directory + +width = 16; +depth = 512; + +address_radix = hex; +data_radix = hex; + +content begin +[0..1ff]: 0; + +000000:c002; +000001:9508; +000002:9508; +000003:2733; +000004:9530; +000005:bb37; +000006:bb34; +000007:bb31; +000008:e003; +000009:bb08; +00000a:950a; +00000b:3000; +00000c:f7e1; +00000d:2733; +00000e:9513; +00000f:9513; +000010:9513; +000011:bb15; +000012:5011; +000013:1313; +000014:cffc; +000015:2722; +000016:5f2d; +000017:bb22; +000018:952a; +000019:b73f; +00001a:ff31; +00001b:cffb; +00001c:cfff; +00001d:9478; +00001e:9468; + + +end; \ No newline at end of file Index: RISCMCU/trunk/vhdl/v_riscmcu.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_riscmcu.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_riscmcu.vhd (revision 28) @@ -0,0 +1,340 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_riscmcu is + port ( + clock : in STD_LOGIC; + reset : in STD_LOGIC; + pinb : inout STD_LOGIC_VECTOR(7 downto 0); + pinc : inout STD_LOGIC_VECTOR(7 downto 0); + pind : inout STD_LOGIC_VECTOR(7 downto 0) + ); +end v_riscmcu; + +architecture riscmcu of v_riscmcu is + +signal ext_irq_pin, ext_timer_clk_pin : std_logic; + +signal clk, clrn, div2, div4, div8, div16 : std_logic; +signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0); + +signal pc, offset : std_logic_vector(8 downto 0); +signal instruction, ir : std_logic_vector(15 downto 0); + +signal skip, en, wr_reg : std_logic; +signal sren : std_logic_vector (6 downto 0); +signal c2a, c2b, add, subcp, logic, right, dir, pass_a : std_logic; +signal wcarry : std_logic; +signal logicsel : integer range 0 to 3; +signal rightsel : integer range 0 to 2; +signal dirsel : integer range 0 to 1; +signal addoffset, push, pull, cpse, skiptest : std_logic; +signal bclr,bset, bld, cbisbi : std_logic; +signal dest, rr, rd : integer range 0 to 15; +signal srsel : integer range 0 to 7; +signal imm_value : std_logic_vector(7 downto 0); + +signal tosr : std_logic_vector (6 downto 0); + +signal vec2, vec4, clr_i, set_i, clr_tov0, clr_intf, timerirq, extirq : std_logic; + +signal rd_sreg,wr_sreg,rd_gimsk,wr_gimsk,rd_timsk, wr_timsk, rd_tifr,wr_tifr : std_logic; +signal rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : std_logic; +signal rd_portb,wr_portb,rd_ddrb,wr_ddrb,rd_pinb : std_logic; +signal rd_portc,wr_portc,rd_ddrc,wr_ddrc,rd_pinc : std_logic; +signal rd_portd,wr_portd,rd_ddrd,wr_ddrd,rd_pind : std_logic; + +signal t_flag, c_flag : std_logic; + +signal vcc, gnd : std_logic; + +signal rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp :std_logic; + +signal bitsel : integer range 0 to 7; +signal set : std_logic; + +signal asel : integer range 0 to 1; +signal bsel : integer range 0 to 3; + + -- Frequency Divider - Divide clock by 2(div2), 4(div4), 8(div8) and 16(div16) + component v_freqdiv + port ( clock : in std_logic; + div2, div4, div8, div16 : buffer std_logic + ); + end component; + + -- Program Counter (9 bit wide) + component v_pc + port ( offset : in std_logic_vector(8 downto 0); + en, addoffset, push, pull, vec2, vec4 : in std_logic; + clk, clrn : in std_logic; + pc : buffer std_logic_vector(8 downto 0) + ); + end component; + + -- Program ROM (512 words) + component v_rom + port ( pc : in std_logic_vector(8 downto 0); + instruction : out std_logic_vector(15 downto 0) + ); + end component; + + -- Instruction Register (16 bit wide) + component v_ir + port ( instruction : in std_logic_vector(15 downto 0); + en, clk, clrn : in std_logic; + ir : buffer std_logic_vector(15 downto 0); + imm_value : out std_logic_vector(7 downto 0); + rd, rr : out integer range 0 to 15 + ); + end component; + + -- Control Unit (with IO address decoder module inside) + component v_controlunit + port ( ir : in std_logic_vector(15 downto 0); + sr : in std_logic_vector(7 downto 0); + clk, clrn : in std_logic; + skip, extirq, timerirq : in std_logic; + + en : buffer std_logic; + wr_reg : buffer std_logic; + rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; + sren : out std_logic_vector (6 downto 0); + + c2a,c2b : out std_logic; + asel : out integer range 0 to 1; + bsel : out integer range 0 to 3; + bitsel : out integer range 0 to 7; + set : out std_logic; + + add, subcp, logic, right, dir, pass_a : out std_logic; + + wcarry : out std_logic; + logicsel : out integer range 0 to 3; + rightsel : out integer range 0 to 2; + dirsel : out integer range 0 to 1; + + addoffset : out std_logic; + push, pull : out std_logic; + + cpse, skiptest : out std_logic; + + bclr,bset : out std_logic; + bld : out std_logic; + + cbisbi : out std_logic; + + vec2, vec4 : buffer std_logic; + + dest : out integer range 0 to 15; + srsel : out integer range 0 to 7; + offset : out std_logic_vector(8 downto 0); + + clr_i, set_i, clr_intf, clr_tov0 : out std_logic; + + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); + end component; + + -- General Purpose Register (16 x 8bit) + component v_gpr + port ( c : in std_logic_vector(7 downto 0); + wr_reg, inc_zp, dec_zp : in std_logic; + rd, rr, dest : in integer range 0 to 15; + clk, clrn : in std_logic; + reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) + ); + end component; + + -- ALU + component v_alu + port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); + c2a, c2b : in std_logic; + asel : in integer range 0 to 1; + bsel : in integer range 0 to 3; + + bitsel : in integer range 0 to 7; + set : in std_logic; + c_flag, t_flag : in std_logic; + + add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; + cpse, skiptest : in std_logic; + + wcarry : in std_logic; + logicsel : in integer range 0 to 3; + rightsel : in integer range 0 to 2; + dirsel : in integer range 0 to 1; + + clk, clrn : in std_logic; + + c : buffer std_logic_vector(7 downto 0); + tosr : buffer std_logic_vector (6 downto 0); + skip : out std_logic + ); + end component; + + -- Status Register (8 bit wide, flags are ITHSVNZC) + component v_sr + port ( clk,clrn: in std_logic; + sren,tosr : in std_logic_vector(6 downto 0); + srsel : in integer range 0 to 7; + clr_i,set_i,bset,bclr : in std_logic; + rd_sreg, wr_sreg : in std_logic; + c : inout std_logic_vector(7 downto 0); + sr : inout std_logic_vector(7 downto 0) + ); + end component; + + -- Data RAM (128 bytes) + component v_ram + port ( addrbus : in std_logic_vector(7 downto 0); + rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0) + ); + end component; + + -- Standard 8-bit I/O Port module (all ports share this same module) + component v_port + port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + pin : inout std_logic_vector(7 downto 0) + ); + end component; + + -- 8-bit Timer with overflow interrupt request, can drive by external clock source + component v_timer + port ( extpin, clr_tov0 : in std_logic; + rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; + rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + timerirq : out std_logic + ); + end component; + + -- External Interrupt + component v_extint + port ( clk, clrn, extpin, clr_intf : in std_logic; + rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; + extirq : out std_logic; + c : inout std_logic_vector(7 downto 0) + ); + end component; + +begin + --U_v_freqdiv: v_freqdiv + -- port map (clock, div2, div4, div8, div16); + + U_v_pc: v_pc + port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc); + + U_v_rom: v_rom + port map (pc, instruction); + + U_v_ir: v_ir + port map (instruction, en, clk, clrn, ir, imm_value, rd, rr); + + U_v_controlunit: v_controlunit + port map (ir, sr, clk, clrn, skip, extirq, timerirq, en, wr_reg, rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp, sren, c2a, c2b, asel, bsel, bitsel, set, add, subcp, logic, right, dir, pass_a, wcarry, logicsel, rightsel, dirsel, addoffset, push, pull, cpse, skiptest, bclr, bset, bld, cbisbi, vec2, vec4, dest, srsel, offset, clr_i, set_i, clr_intf, clr_tov0, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); + + U_v_gpr: v_gpr + port map (c, wr_reg, inc_zp, dec_zp, rd, rr, dest, clk, clrn, reg_rd, reg_rr, addrbus); + + U_v_alu: v_alu + port map (reg_rd, reg_rr, imm_value, c2a, c2b, asel, bsel, bitsel, set, c_flag, t_flag, add, subcp, logic, right, dir, bld, cbisbi, pass_a, cpse, skiptest, wcarry, logicsel, rightsel, dirsel, clk, clrn, c, tosr, skip); + + U_v_sr: v_sr + port map (clk, clrn, sren, tosr, srsel, clr_i, set_i, bset, bclr, rd_sreg, wr_sreg, c, sr); + + U_v_ram: v_ram + port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c); + + U_v_timer: v_timer + port map (ext_timer_clk_pin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq); + + U_v_extint: v_extint + port map (clk, clrn, ext_irq_pin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c); + + -- The same module v_port is used by 3 I/O ports, just the signals are different + U_v_portB: v_port + port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb); + + U_v_portC: v_port + port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc); + + U_v_portD: v_port + port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind); + + -- Global reset, it resets ALL flip-flops and registers to the initial state (normally gnd) + clrn <= reset; + + vcc <= '1'; + gnd <= '0'; + t_flag <= sr(6); + c_flag <= sr(0); + + -- These are the external interrupt request pin and external timer clock source pin + -- They share pins with the I/O ports + -- TIPS: You can use any of the 24 I/O pins, I use pind(7) for my applications + ext_irq_pin <= pind(2); + ext_timer_clk_pin <= pind(4); + + -- When I use the UP1 board, the on-board 25 MHz clock is too fast and + -- I need to divide it by 4 so that the MCU can run + -- For waveform simulation, it does not require division (clk <= clock) + -- TIPS: To have division, uncomment v_freqdiv module instantation on top of the page and + -- assign clk with div2, div4, div8 or div16 + clk <= clock; + + +end riscmcu; + + Index: RISCMCU/trunk/vhdl/v_ir.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_ir.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_ir.vhd (revision 28) @@ -0,0 +1,74 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_ir is + port( instruction : in std_logic_vector(15 downto 0); + en, clk, clrn : in std_logic; + ir : buffer std_logic_vector(15 downto 0); + imm_value : out std_logic_vector(7 downto 0); + rd, rr : out integer range 0 to 15 +); +end v_ir; + +architecture ir of v_ir is +begin + +process(clk,clrn) +begin + if clrn = '0' then + ir <= "0000000000000000"; + elsif clk'event and clk = '1' then + if en = '1' then + ir <= instruction; + end if; + end if; +end process; + +imm_value <= ir(11 downto 8) & ir(3 downto 0); +rd <= conv_integer(ir(7 downto 4)); +rr <= conv_integer(ir(3 downto 0)); + +end ir; Index: RISCMCU/trunk/vhdl/v_extint.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_extint.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_extint.vhd (revision 28) @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_extint is + port( clk, clrn, extpin, clr_intf : in std_logic; + rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; + extirq : out std_logic; + c : inout std_logic_vector(7 downto 0)); +end v_extint; + +architecture extint of v_extint is + +signal int0, flag, currentstate, laststate : std_logic; +signal isc0 : integer range 0 to 3; + +begin + +c <= "000000" & conv_std_logic_vector(isc0,2) when rd_mcucr = '1' else + '0' & int0 & "000000" when rd_gimsk = '1' else + "ZZZZZZZZ"; + +extirq <= int0 and not extpin when isc0 = 0 else + int0 and flag; + +process(clk, clrn) +begin + if clrn = '0' then + int0 <= '0'; + isc0 <= 0; + currentstate <= '0'; + laststate <= '0'; + elsif clk'event and clk = '1' then + if wr_gimsk = '1' then + int0 <= c(6); + end if; + if wr_mcucr = '1' then + isc0 <= conv_integer(c(1 downto 0)); + end if; + currentstate <= extpin; + laststate <= currentstate; + end if; +end process; + +process(clrn, clr_intf, clk, isc0, currentstate) +begin + if clrn = '0' or clr_intf = '1' then + flag <= '0'; + elsif clk'event and clk = '1' then + if isc0 = 2 then + if currentstate = '0' and laststate = '1' then + flag <= '1'; + end if; + elsif isc0 = 3 then + if currentstate = '1' and laststate = '0' then + flag <= '1'; + end if; + end if; + end if; +end process; + +end extint; Index: RISCMCU/trunk/vhdl/v_ram.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_ram.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_ram.vhd (revision 28) @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_ram is + port( addrbus : in std_logic_vector(7 downto 0); + rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0) + ); +end entity; + +architecture ram of v_ram is + +component lpm_ram_dq + generic( lpm_width: positive := 8; + lpm_widthad: positive := 8; + lpm_numwords: natural := 256; + lpm_file: string := "ram.mif"; + lpm_indata: string := "unregistered"; + lpm_address_control: string := "unregistered"; + lpm_outdata: string := "unregistered" + ); + port( data: in std_logic_vector(lpm_width-1 downto 0); + address: in std_logic_vector(lpm_widthad-1 downto 0); + we: in std_logic; + inclock: in std_logic := '0'; + outclock: in std_logic := '0'; + q: out std_logic_vector(lpm_width-1 downto 0) + ); +end component; + +signal mar, mbr, ram_out : std_logic_vector(7 downto 0); + +begin + +sram: lpm_ram_dq + port map(data => mbr, address => mar, we => wr_ram, q => ram_out); + +c <= ram_out when rd_ram = '1' else + "ZZZZZZZZ"; + +process(clk,clrn) +begin + if clrn = '0' then + mar <= "00000000"; + mbr <= "00000000"; + elsif clk'event and clk = '1' then + if ld_mbr = '1' then + mbr <= c; + end if; + if ld_mar = '1' then + mar <= addrbus; + end if; + end if; +end process; + +end ram; Index: RISCMCU/trunk/vhdl/v_timer.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_timer.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_timer.vhd (revision 28) @@ -0,0 +1,177 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_timer is + port( extpin, clr_tov0 : in std_logic; + rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; + rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + timerirq : out std_logic + ); +end v_timer; + +architecture timer of v_timer is + +signal toie0, tov0 : std_logic; +signal cs : integer range 0 to 7; +signal tcnt0 : std_logic_vector(7 downto 0); +signal div1, div2, div4, div8, div16, div32, div64, div128, div256, div512, div1024 : std_logic; +signal timerclk, inc_tcnt0, currentstate, laststate : std_logic; + +begin + +-- Timer Interrupt Request +timerirq <= toie0 and tov0; + +-- Read 4 Registers +c <= "000000" & toie0 & "0" when rd_timsk = '1' else + "000000" & tov0 & "0" when rd_tifr = '1' else + conv_std_logic_vector(cs,8) when rd_tccr0 = '1' else + tcnt0 when rd_tcnt0 = '1' else + "ZZZZZZZZ"; + +-- Select Clock Source +with cs select + timerclk <= '0' when 0, + clk when 1, + div8 when 2, + div64 when 3, + div256 when 4, + div1024 when 5, + not extpin when 6, + extpin when 7; + +-- Timer : clear/write 4 registers, increment timer, set overflow flag, sample clock source +process(clrn, clr_tov0, wr_tifr, c, clk) +begin + if clrn = '0' then + toie0 <= '0'; + cs <= 0; + tcnt0 <= "00000000"; + tov0 <= '0'; + currentstate <= '0'; + laststate <= '0'; + + elsif clr_tov0 = '1' or (wr_tifr = '1' and c(1) = '1') then + tov0 <= '0'; + + elsif clk'event and clk = '1' then + + if wr_tcnt0 = '1' then + tcnt0 <= c; + elsif inc_tcnt0 = '1' then + tcnt0 <= tcnt0 + 1; + if tcnt0 = "11111111" then + tov0 <= '1'; + end if; + end if; + + if wr_timsk = '1' then + toie0 <= c(1); + end if; + if wr_tccr0 = '1' then + cs <= conv_integer(c(2 downto 0)); + end if; + + currentstate <= timerclk; + laststate <= currentstate; + + end if; +end process; + +-- Detect rising edge +inc_tcnt0 <= '1' when (laststate ='0' and currentstate = '1') or cs = 1 else + '0'; + +-- 10 bit prescaler +process(clk, clrn) +begin + if clrn = '0' then + div2 <= '0'; + div4 <= '0'; + div8 <= '0'; + div16 <= '0'; + div32 <= '0'; + div64 <= '0'; + div128 <= '0'; + div256 <= '0'; + div512 <= '0'; + div1024 <= '0'; + + elsif clk'event and clk = '1' then + div2 <= not div2; + if div2 = '1' then + div4 <= not div4; + if div4 = '1' then + div8 <= not div8; + if div8 = '1' then + div16 <= not div16; + if div16 = '1' then + div32 <= not div32; + if div32 = '1' then + div64 <= not div64; + if div64 = '1' then + div128 <= not div128; + if div128 = '1' then + div256 <= not div256; + if div256 = '1' then + div512 <= not div512; + if div512 = '1' then + div1024 <= not div1024; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; +end process; + +end timer; Index: RISCMCU/trunk/vhdl/v_controlunit.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_controlunit.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_controlunit.vhd (revision 28) @@ -0,0 +1,533 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity v_controlunit is + port( ir : in std_logic_vector(15 downto 0); + sr : in std_logic_vector(7 downto 0); + clk, clrn : in std_logic; + skip, extirq, timerirq : in std_logic; + + en : buffer std_logic; + wr_reg : buffer std_logic; + rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; + sren : out std_logic_vector (6 downto 0); + + c2a,c2b : out std_logic; + asel : out integer range 0 to 1; + bsel : out integer range 0 to 3; + bitsel : out integer range 0 to 7; + set : out std_logic; + + add, subcp, logic, right, dir, pass_a : out std_logic; + + wcarry : out std_logic; + logicsel : out integer range 0 to 3; + rightsel : out integer range 0 to 2; + dirsel : out integer range 0 to 1; + + addoffset : out std_logic; + push, pull : out std_logic; + + cpse, skiptest : out std_logic; + + bclr,bset : out std_logic; + bld : out std_logic; + + cbisbi : out std_logic; + + vec2, vec4 : buffer std_logic; + + dest : out integer range 0 to 15; + srsel : out integer range 0 to 7; + offset : out std_logic_vector(8 downto 0); + + clr_i, set_i, clr_intf, clr_tov0 : out std_logic; + + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + +); +end v_controlunit; + +architecture controlunit of v_controlunit is + +type statetype is (exes, nop2s, nop1s, lds, sts, cbisbis, sbicss, sleeps); + +signal ibr : std_logic_vector(11 downto 0); +signal state : statetype; +signal one, neg, imm : std_logic; + +signal +cpcm, sbcm, addm, cpsem, cpm, subm, adcm, andm, eorm, orm, movm, +cpim, sbcim, subim, orim, andim, ldm, stm, comm, negm, swapm, incm, +asrm, lsrm, rorm, decm, bsetm, bclrm, retm, retim, sleepm, +cbisbim, sbicsm, inm, outm, rjmpm, rcallm, ldim, +brbcsm, bldm, bstm, sbrcsm, +ld_incm, ld_decm, st_incm, st_decm : std_logic; + +signal ioaddr : integer range 0 to 16#3f#; +signal rd_io, wr_io, break, irq, get_io, wr_ram_fast, branchtest, branch, jmp : std_logic; + + component v_iodecoder + port( ioaddr : in integer range 0 to 16#3f#; + rd_io, wr_io : in std_logic; + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); + end component; + +begin + +-- Instruction Decoder +-- Decode 51 instructions generate 46 'm signals +-- Combine brbcs+brbs (brbcs) cbi+sbi (cbisbi) sbrc+sbrs (sbrcs) sbic+sbis (sbics) + +process(ir, wr_reg, get_io, ibr) +begin + +cpcm <= '0'; sbcm <= '0'; addm <= '0'; +cpsem <= '0'; cpm <= '0'; subm <= '0'; adcm <= '0'; +andm <= '0'; eorm <= '0'; orm <= '0'; movm <= '0'; +cpim <= '0'; sbcim <= '0'; subim <= '0'; orim <= '0'; andim <= '0'; +ldm <= '0'; stm <= '0'; comm <= '0'; negm <= '0'; swapm <= '0'; incm <= '0'; +asrm <= '0'; lsrm <= '0'; rorm <= '0'; decm <= '0'; +bsetm <= '0'; bclrm <= '0'; retm <= '0'; retim <= '0'; sleepm <= '0'; +cbisbim <= '0'; sbicsm <= '0'; +inm <= '0'; outm <= '0'; rjmpm <= '0'; rcallm <= '0'; ldim <= '0'; +brbcsm <= '0'; bldm <= '0'; bstm <= '0'; sbrcsm <= '0'; +ld_incm <= '0'; ld_decm <= '0'; st_incm <= '0'; st_decm <= '0'; + +case ir(15 downto 12) is + when "0000" => + if ir(11 downto 10) = "01" then cpcm <= '1'; end if; + if ir(11 downto 10) = "10" then sbcm <= '1'; end if; + if ir(11 downto 10) = "11" then addm <= '1'; end if; + when "0001" => + if ir(11 downto 10) = "00" then cpsem<= '1'; end if; + if ir(11 downto 10) = "01" then cpm <= '1'; end if; + if ir(11 downto 10) = "10" then subm <= '1'; end if; + if ir(11 downto 10) = "11" then adcm <= '1'; end if; + when "0010" => + if ir(11 downto 10) = "00" then andm <= '1'; end if; + if ir(11 downto 10) = "01" then eorm <= '1'; end if; + if ir(11 downto 10) = "10" then orm <= '1'; end if; + if ir(11 downto 10) = "11" then movm <= '1'; end if; + when "0011" => + cpim <= '1'; + when "0100" => + sbcim <= '1'; + when "0101" => + subim <= '1'; + when "0110" => + orim <= '1'; + when "0111" => + andim <= '1'; + when "1000" => + if ir(11 downto 9) = "000" then ldm <= '1'; end if; + if ir(11 downto 9) = "001" then stm <= '1'; end if; + when "1001" => + if ir(11 downto 9) = "000" then + if ir(1 downto 0) = "01" then ld_incm <= '1'; end if; + if ir(1 downto 0) = "10" then ld_decm <= '1'; end if; + end if; + if ir(11 downto 9) = "001" then + if ir(1 downto 0) = "01" then st_incm <= '1'; end if; + if ir(1 downto 0) = "10" then st_decm <= '1'; end if; + end if; + if ir(11 downto 9) = "010" then + case ir(3 downto 0) is + when "0000" => comm <= '1'; + when "0001" => negm <= '1'; + when "0010" => swapm <= '1'; + when "0011" => incm <= '1'; + when "0101" => asrm <= '1'; + when "0110" => lsrm <= '1'; + when "0111" => rorm <= '1'; + when "1010" => decm <= '1'; + when "1000" => + if ir(8 downto 7) = "00" then bsetm <= '1'; end if; + if ir(8 downto 7) = "01" then bclrm <= '1'; end if; + if ir(8 downto 7) & ir(4) = "100" then retm <= '1'; end if; + if ir(8 downto 7) & ir(4) = "101" then retim <= '1'; end if; + if ir(8 downto 7) = "11" then sleepm <= '1'; end if; + when others => + end case; + elsif ir(11 downto 10) = "10" then + if ir(8) = '0' then cbisbim <= '1'; -- cbi, sbi + else sbicsm <= '1'; end if; -- sbic, sbis + end if; + when "1011" => + if ir(11) = '0' then inm <= '1'; + else outm <= '1'; + end if; + when "1100" => + rjmpm <= '1'; + when "1101" => + rcallm <= '1'; + when "1110" => + ldim <= '1'; + when "1111" => + if ir(11) = '0' then brbcsm <= '1'; end if; + if ir(11 downto 9) = "100" then bldm <= '1'; end if; + if ir(11 downto 9) = "101" then bstm <= '1'; end if; + if ir(11 downto 10) = "11" then sbrcsm <= '1'; end if;-- sbrc, sbrs + when others => +end case; + + +-- Generate Fetch Stage Signals : C2A and C2B (C2A active also when fetch I/O) +if ((ibr(7 downto 4) = ir(7 downto 4)) and wr_reg = '1') or get_io = '1' then + c2a <= '1'; +else + c2a <= '0'; +end if; + +if (ibr(7 downto 4) = ir(3 downto 0)) and wr_reg = '1' then + c2b <= '1'; +else + c2b <= '0'; +end if; + +end process; + +-- Generate wcarry, logicsel, rightsel and dirsel +-- Load IBR with IR when EN active +process(clk,clrn) +begin +if clrn = '0' then + ibr <= "000000000000"; + + wcarry <= '0'; + logicsel <= 0; + rightsel <= 0; + dirsel <= 0; + +elsif clk'event and clk = '1' then + if en = '1' then + ibr <= ir(11 downto 0); + end if; + + wcarry <= adcm or sbcm or sbcim or cpcm; + + if orm = '1' or orim = '1' then logicsel <= 1; + elsif eorm = '1' then logicsel <= 2; + elsif comm = '1' then logicsel <= 3; + else logicsel <= 0; + end if; + + if rorm = '1' then rightsel <= 1; + elsif asrm = '1' then rightsel <= 2; + else rightsel <= 0; + end if; + + if swapm = '1' then dirsel <= 1; + else dirsel <= 0; + end if; + +end if; +end process; + + +-- Finite State Machine + +irq <= (timerirq or extirq) and sr(7); +break <= branch or skip or irq; + +process(clk, clrn) +begin + +if clrn = '0' then + + state <= exes; + + en <= '1'; get_io <= '0'; + pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; + rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; + ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; + add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; + jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; + bclr <= '0'; bset <= '0'; bld <= '0'; + cpse <= '0'; skiptest <= '0'; + cbisbi <= '0'; + vec2 <= '0'; vec4 <= '0'; set_i <= '0'; + +elsif clk'event and clk = '1' then + + en <= '1'; get_io <= '0'; + pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; + rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; + ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; + add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; + jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; + bclr <= '0'; bset <= '0'; bld <= '0'; + cpse <= '0'; skiptest <= '0'; + cbisbi <= '0'; + vec2 <= '0'; vec4 <= '0'; set_i <= '0'; + + case state is + + when exes => + + if break = '1' then + + if branch = '1' then + state <= nop1s; + + elsif skip = '1' then + + elsif irq = '1' then + state <= nop2s; + push <= '1'; + if extirq = '1' then + vec2 <= '1'; + else + vec4 <= '1'; + end if; + end if; + + else + + if rjmpm = '1' or rcallm = '1' or retm = '1' or retim = '1' then + state <= nop2s; + elsif cbisbim = '1' then + state <= cbisbis; + elsif sbicsm = '1' then + state <= sbicss; + elsif ldm = '1' or ld_incm = '1' or ld_decm = '1' then + state <= lds; + elsif stm = '1' or st_incm = '1' or st_decm = '1' then + state <= sts; + elsif sleepm = '1' then + state <= sleeps; + end if; + + -- PC signals + jmp <= rjmpm or rcallm; -- encoded + push <= rcallm; + pull <= retm or retim; + + -- PC and IR signals + en <= not (cbisbim or sbicsm + or stm or st_incm or st_decm or + ldm or ld_incm or ld_decm); + + -- General Purpose Register File signals + wr_reg <= addm or adcm or incm + or subm or subim or sbcm or sbcim or decm or negm + or andm or andim or orm or orim or eorm or comm + or lsrm or rorm or asrm + or ldim or movm or swapm + or inm; + inc_zp <= ld_incm or st_incm; + dec_zp <= ld_decm or st_decm; + + -- ALU signals + add <= addm or adcm or incm; + subcp <= subm or subim or sbcm or sbcim or decm or negm + or cpm or cpim or cpcm; + logic <= andm or andim or orm or orim or eorm or comm; + right <= lsrm or rorm or asrm; + dir <= ldim or movm or swapm; + bld <= bldm; + pass_a <= outm or stm or st_incm or st_decm; + cpse <= cpsem; + skiptest <= sbrcsm; + + + + -- SR signals + bclr <= bclrm; + bset <= bsetm; + set_i <= retim; + + sren(0) <= addm or adcm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm + or comm + or lsrm or rorm or asrm; + + for i in 1 to 4 loop + sren(i) <= addm or adcm or incm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or decm or negm + or andm or andim or orm or orim or eorm or comm + or lsrm or rorm or asrm; + end loop; + + sren(5) <= addm or adcm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm; + + sren(6) <= bstm; + + -- Data RAM signals + ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm; + ld_mbr <= stm or st_incm or st_decm; + + -- I/O decoder signals + wr_io <= outm; + rd_io <= inm or sbicsm or cbisbim; + if inm = '1' or outm = '1' then + ioaddr <= conv_integer(ir(10 downto 9) & ir(3 downto 0)); + else + ioaddr <= conv_integer('0' & ir(7 downto 3)); + end if; + + + -- Branch Evaluation Unit signal + branchtest <= brbcsm; + + + -- Fetch I/O, generate C2A + get_io <= cbisbim or sbicsm; + + end if; + + when nop2s => + state <= nop1s; + + when nop1s => + state <= exes; + + when cbisbis => + state <= exes; + cbisbi <= '1'; + wr_io <= '1'; + + when sbicss => + state <= exes; + skiptest <= '1'; + + when lds => + state <= exes; + wr_reg <= '1'; + rd_ram <= '1'; + + when sts => + state <= exes; + wr_ram_fast <= '1'; + + when sleeps => + en <= '0'; + if irq = '1' then + en <= '1'; + state <= nop2s; + push <= '1'; + if extirq = '1' then + vec2 <= '1'; + else + vec4 <= '1'; + end if; + end if; + + end case; + +end if; +end process; + +-- Generate Delayed WR_RAM signal to avoid writing to wrong address +process(state, wr_ram_fast) +begin + if state = exes then + wr_ram <= wr_ram_fast; + else + wr_ram <= '0'; + end if; +end process; + + +-- Branch Evaluation Unit +process(branchtest, sr, ibr) +begin + if branchtest = '1' and (sr(conv_integer(ibr(2 downto 0))) = not ibr(10)) then + branch <= '1'; + else + branch <= '0'; + end if; +end process; + + +-- IO address decoder +iodec : v_iodecoder + port map (ioaddr, rd_io, wr_io, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); + + +-- Intruction Buffer Register (IBR) to signals ------------------ +dest <= conv_integer(ibr(7 downto 4)); +srsel <= conv_integer(ibr(6 downto 4)); +set <= ibr(9); +bitsel <= conv_integer(ibr(2 downto 0)); +offset <= ibr(8 downto 0) when jmp = '1' else + ibr(9) & ibr(9) & ibr(9 downto 3); + + +-- Generate Fetch Stage Signals : ASEL and SEL +imm <= subim or sbcim or cpim or andim or orim or ldim; +one <= incm or decm; +neg <= negm; + +asel <= 1 when neg = '1' and get_io = '0' else + 0; +bsel <= 1 when neg = '1' else + 2 when imm = '1' else + 3 when one = '1' else + 0; + + +-- Decode Control Signal +addoffset <= branch or jmp; -- PC +clr_i <= vec2 or vec4; -- PC +clr_intf <= vec2; -- External Interrupt +clr_tov0 <= vec4; -- Timer + +end controlunit; + + Index: RISCMCU/trunk/vhdl/v_alu.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_alu.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_alu.vhd (revision 28) @@ -0,0 +1,295 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library lpm; +use lpm.lpm_components.all; + +entity v_alu is + port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); + c2a, c2b : in std_logic; + asel : in integer range 0 to 1; + bsel : in integer range 0 to 3; + + bitsel : in integer range 0 to 7; + set : in std_logic; + c_flag, t_flag : in std_logic; + + add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; + cpse, skiptest : in std_logic; + + wcarry : in std_logic; + logicsel : in integer range 0 to 3; + rightsel : in integer range 0 to 2; + dirsel : in integer range 0 to 1; + + clk, clrn : in std_logic; + + c : buffer std_logic_vector(7 downto 0); + tosr : buffer std_logic_vector (6 downto 0); + skip : out std_logic + ); + +end v_alu; + +architecture alu of v_alu is + +signal a, b : std_logic_vector(7 downto 0); + +signal sr : std_logic_vector(6 downto 0); + +signal cin, overflow, cout : std_logic; + +signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0); + +begin + +-- Operand Fetch Unit -- + +process(clrn, clk) +begin + if clrn = '0' then + a <= "00000000"; + b <= "00000000"; + elsif clk'event and clk = '1' then + case asel is + when 0 => + if c2a = '1' then + a <= c; + else + a <= reg_rd; + end if; + when 1 => + a <= "00000000"; + end case; + + case bsel is + when 0 => + if c2b = '1' then + b <= c; + else + b <= reg_rr; + end if; + when 1 => + b <= reg_rd; + when 2 => + b <= imm_value; + when 3 => + b <= "00000001"; + end case; + end if; +end process; + + +-- Execution Unit -- + +cin <= c_flag when add = '1' and wcarry = '1' else + '0' when add = '1' and wcarry = '0' else + not c_flag when wcarry = '1' else + '1'; + + +-- Adder-Subtracter +adder1 : lpm_add_sub + generic map(lpm_width => 8) + port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow); + +-- Logic Unit +with logicsel select + logic_out <= a and b when 0, -- and, andi + a or b when 1, -- or, ori + a xor b when 2, -- eor + not a when 3; -- com + +-- Shifter +right_out(6 downto 0) <= a(7 downto 1); +with rightsel select + right_out(7) <= '0' when 0, -- lsr + c_flag when 1, -- ror + a(7) when 2; -- asr + +-- Direct Unit +with dirsel select + dir_out <= b when 0, -- ldi, mov + (a(3 downto 0) & a(7 downto 4)) when 1; -- swap + +-- Bit Loader +process(bld, bitsel, a, t_flag, set) +begin + for i in 0 to 7 loop + if i /= bitsel then + bldcbi_out(i) <= a(i); + elsif bld = '1' then + bldcbi_out(i) <= t_flag; + else + bldcbi_out(i) <= set; + end if; + end loop; +end process; + +-- Results to Data Bus +process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a) +begin + + c <= "ZZZZZZZZ"; + + -- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg + if add = '1' or subcp = '1' then + c <= sum; + end if; + + -- and, andi, or, ori, eor, com + if logic = '1' then + c <= logic_out; + end if; + + -- lsr, lsr, asr + if right = '1' then + c <= right_out; + end if; + + -- ldi, mov, swap + if dir = '1' then + c <= dir_out; + end if; + + -- bld, cbisbi + if bld = '1' or cbisbi = '1' then + c <= bldcbi_out; + end if; + + -- out, st z, st z+, st -z + if pass_a = '1' then + c <= a; + end if; + +end process; + + +-- Skip Evaluation Unit -- +process(cpse, skiptest, a, b, set, bitsel, c) +begin + + skip <= '0'; + + -- cpse + if cpse = '1' then + if a = b then + skip <= '1'; + end if; + + -- sbrc, sbrs + elsif skiptest = '1' then + if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then + skip <= '1'; + end if; + + end if; +end process; + +-- Flags Evaluation Unit -- +process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel) +begin + +-- C sr(0) + if add = '1' then + sr(0) <= cout; + elsif right = '1' then + sr(0) <= a(0); + elsif logic = '1' then -- com + sr(0) <= '1'; + else -- subcp + sr(0) <= not cout; + --sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7)); + end if; + +-- Z sr(1) + if (add = '1' or subcp = '1') and sum = "00000000" then + sr(1) <= '1'; + elsif logic = '1' and logic_out = "00000000" then + sr(1) <= '1'; + elsif right = '1' and right_out = "00000000" then + sr(1) <= '1'; + else + sr(1) <= '0'; + end if; + +-- N sr(2) + if (add = '1' or subcp = '1') and sum(7) = '1' then + sr(2) <= '1'; + elsif logic = '1' and logic_out(7) = '1' then + sr(2) <= '1'; + elsif right = '1' and right_out(7) = '1' then + sr(2) <= '1'; + else + sr(2) <= '0'; + end if; + +-- V sr(3) + if right = '1' then + sr(3) <= right_out(7) xor a(0); + elsif logic = '1' then + sr(3) <= '0'; + else + sr(3) <= overflow; + end if; + +-- S sr(4) + sr(4) <= sr(2) xor sr(3); + +-- H sr(5) + if add = '1' then + sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3)); + else -- subcp + sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3)); + end if; + +-- T sr(6) + sr(6) <= a(bitsel); + +end process; + +tosr <= sr; + +end alu; Index: RISCMCU/trunk/vhdl/v_port_bit.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_port_bit.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_port_bit.vhd (revision 28) @@ -0,0 +1,83 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_port_bit is + port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; + clk,clrn : in std_logic; + c : inout std_logic; + pin : inout std_logic + ); +end v_port_bit; + +architecture port_bit of v_port_bit is + +signal datareg, ddr : std_logic; + +begin + +c <= datareg when rd_port = '1' else + ddr when rd_ddr = '1' else + pin when rd_pin = '1' else + 'Z'; + +pin <= datareg when ddr = '1' else + 'Z'; + +process(clrn, clk) +begin + if clrn = '0' then + datareg <= '0'; + ddr <= '0'; + elsif clk'event and clk = '1' then + if wr_port = '1' then + datareg <= c; + end if; + if wr_ddr = '1' then + ddr <= c; + end if; + end if; +end process; + +end port_bit; + Index: RISCMCU/trunk/vhdl/v_sr.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_sr.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_sr.vhd (revision 28) @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_sr is + port( clk,clrn: in std_logic; + sren,tosr : in std_logic_vector(6 downto 0); + srsel : in integer range 0 to 7; + clr_i,set_i,bset,bclr : in std_logic; + rd_sreg, wr_sreg : in std_logic; + c : inout std_logic_vector(7 downto 0); + sr : inout std_logic_vector(7 downto 0) + ); +end v_sr; + +architecture sr of v_sr is +begin + +c <= sr when rd_sreg = '1' else + "ZZZZZZZZ"; + +process(clk,clrn,rd_sreg,sr) +begin + if clrn = '0' then + sr <= "00000000"; + elsif clk'event and clk = '1' then + if wr_sreg = '1' then + sr <= c; + elsif bset = '1' or bclr = '1' then + sr(srsel) <= bset; + elsif clr_i = '1' or set_i = '1' then + sr(7) <= set_i; + else + for i in 0 to 6 loop + if sren(i) = '1' then + sr(i) <= tosr(i); + end if; + end loop; + end if; + end if; + +end process; + +end sr; + + Index: RISCMCU/trunk/vhdl/ram.mif =================================================================== --- RISCMCU/trunk/vhdl/ram.mif (nonexistent) +++ RISCMCU/trunk/vhdl/ram.mif (revision 28) @@ -0,0 +1,10 @@ +width = 8; +depth = 256; + +address_radix = hex; +data_radix = hex; + +content begin +[0..ff]: 0; + +end; \ No newline at end of file Index: RISCMCU/trunk/vhdl/v_port.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_port.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_port.vhd (revision 28) @@ -0,0 +1,71 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_port is + port( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + pin : inout std_logic_vector(7 downto 0) + ); +end v_port; + +architecture ioport of v_port is + +component v_port_bit + port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; + clk,clrn : in std_logic; + c : inout std_logic; + pin : inout std_logic + ); +end component; + +begin + + g1: + for i in 0 to 7 generate + u1 : v_port_bit + port map (rd_port, wr_port, rd_ddr, wr_ddr, rd_pin, clk, clrn, c(i), pin(i)); + end generate; + +end ioport; Index: RISCMCU/trunk/vhdl/v_gpr.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_gpr.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_gpr.vhd (revision 28) @@ -0,0 +1,87 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_gpr is + port( c : in std_logic_vector(7 downto 0); + wr_reg, inc_zp, dec_zp : in std_logic; + rd, rr, dest : in integer range 0 to 15; + clk, clrn : in std_logic; + reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) + ); +end v_gpr; + +architecture gpr of v_gpr is + +type regfiletype is array (0 to 15) of std_logic_vector(7 downto 0); + +signal reg : regfiletype; + +begin + +addrbus <= reg(14) - 16#61# when dec_zp = '1' else + reg(14) - 16#60#; + +reg_rd <= reg(rd); +reg_rr <= reg(rr); + +process(clk, clrn) +begin + if clrn = '0' then + for i in 0 to 15 loop + reg(i) <= "00000000"; + end loop; + elsif clk'event and clk = '1' then + if wr_reg = '1' then + reg(dest) <= c; + end if; + if inc_zp = '1' then + reg(14) <= reg(14) + 1; + elsif dec_zp = '1' then + reg(14) <= reg(14) - 1; + end if; + end if; +end process; + +end gpr; Index: RISCMCU/trunk/vhdl/license.txt =================================================================== --- RISCMCU/trunk/vhdl/license.txt (nonexistent) +++ RISCMCU/trunk/vhdl/license.txt (revision 28) @@ -0,0 +1,144 @@ +GNU LESSER GENERAL PUBLIC LICENSE +Version 2.1, February 1999 + + +Copyright (C) 1991, 1999 Free Software Foundation, Inc. +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. + +[This is the first released version of the Lesser GPL. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + + +END OF TERMS AND CONDITIONS \ No newline at end of file Index: RISCMCU/trunk/vhdl/v_iodecoder.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_iodecoder.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_iodecoder.vhd (revision 28) @@ -0,0 +1,144 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_iodecoder is + port( ioaddr : in integer range 0 to 16#3f#; + rd_io, wr_io : in std_logic; + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); +end v_iodecoder; + +architecture iodecoder of v_iodecoder is +begin + +process(rd_io, ioaddr) +begin + + rd_sreg <= '0'; + rd_gimsk <= '0'; + rd_timsk <= '0'; + rd_tifr <= '0'; + rd_mcucr <= '0'; + rd_tccr0 <= '0'; + rd_tcnt0 <= '0'; + + rd_portb <= '0'; + rd_ddrb <= '0'; + rd_pinb <= '0'; + rd_portc <= '0'; + rd_ddrc <= '0'; + rd_pinc <= '0'; + rd_portd <= '0'; + rd_ddrd <= '0'; + rd_pind <= '0'; + + if rd_io = '1' then + case ioaddr is + when 16#3f# => rd_sreg <= '1'; + when 16#3b# => rd_gimsk <= '1'; + when 16#39# => rd_timsk <= '1'; + when 16#38# => rd_tifr <= '1'; + when 16#35# => rd_mcucr <= '1'; + when 16#33# => rd_tccr0 <= '1'; + when 16#32# => rd_tcnt0 <= '1'; + + when 16#18# => rd_portb <= '1'; + when 16#17# => rd_ddrb <= '1'; + when 16#16# => rd_pinb <= '1'; + when 16#15# => rd_portc <= '1'; + when 16#14# => rd_ddrc <= '1'; + when 16#13# => rd_pinc <= '1'; + when 16#12# => rd_portd <= '1'; + when 16#11# => rd_ddrd <= '1'; + when 16#10# => rd_pind <= '1'; + when others => + end case; + end if; +end process; + +process(wr_io, ioaddr) +begin + + wr_sreg <= '0'; + wr_gimsk <= '0'; + wr_timsk <= '0'; + wr_tifr <= '0'; + wr_mcucr <= '0'; + wr_tccr0 <= '0'; + wr_tcnt0 <= '0'; + + wr_portb <= '0'; + wr_ddrb <= '0'; + wr_portc <= '0'; + wr_ddrc <= '0'; + wr_portd <= '0'; + wr_ddrd <= '0'; + + if wr_io = '1' then + case ioaddr is + when 16#3f# => wr_sreg <= '1'; + when 16#3b# => wr_gimsk <= '1'; + when 16#39# => wr_timsk <= '1'; + when 16#38# => wr_tifr <= '1'; + when 16#35# => wr_mcucr <= '1'; + when 16#33# => wr_tccr0 <= '1'; + when 16#32# => wr_tcnt0 <= '1'; + + when 16#18# => wr_portb <= '1'; + when 16#17# => wr_ddrb <= '1'; + when 16#15# => wr_portc <= '1'; + when 16#14# => wr_ddrc <= '1'; + when 16#12# => wr_portd <= '1'; + when 16#11# => wr_ddrd <= '1'; + when others => + end case; + end if; +end process; + +end iodecoder; Index: RISCMCU/trunk/vhdl/v_rom.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_rom.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_rom.vhd (revision 28) @@ -0,0 +1,80 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_rom is + port( pc : in std_logic_vector(8 downto 0); + instruction : out std_logic_vector(15 downto 0)); +end v_rom; + +architecture rom of v_rom is + + component LPM_ROM + generic ( + LPM_WIDTH: integer := 16; + LPM_WIDTHAD: integer := 9; + LPM_NUMWORDS: integer := 512; + LPM_FILE: string := "program.mif"; + LPM_ADDRESS_CONTROL: string := "UNREGISTERED"; + LPM_OUTDATA: string := "UNREGISTERED" + ); + port ( + ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); + inclock: IN STD_LOGIC := '0'; + outclock: IN STD_LOGIC := '0'; + memenab: IN STD_LOGIC := '1'; + Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0) + ); + end component; + +signal gnd, vcc : std_logic; + +begin + +vcc <= '1'; +gnd <= '0'; + + v1 : LPM_ROM + port map (address => pc, memenab => vcc, q => instruction); + +end rom; Index: RISCMCU/trunk/vhdl/v_freqdiv.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_freqdiv.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_freqdiv.vhd (revision 28) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_freqdiv is + port( clock : in std_logic; + div2, div4, div8, div16 : buffer std_logic); +end v_freqdiv; + +architecture myfreqdiv of v_freqdiv is +begin +process(clock) +begin + if clock'event and clock = '1' then + div2 <= not div2; + if div2 = '1' then + div4 <= not div4; + if div4 = '1' then + div8 <= not div8; + if div8 = '1' then + div16 <= not div16; + end if; + end if; + end if; + end if; +end process; +end myfreqdiv; Index: RISCMCU/trunk/vhdl/v_pc.vhd =================================================================== --- RISCMCU/trunk/vhdl/v_pc.vhd (nonexistent) +++ RISCMCU/trunk/vhdl/v_pc.vhd (revision 28) @@ -0,0 +1,101 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_pc is + port( offset : in std_logic_vector(8 downto 0); + en, addoffset, push, pull, vec2, vec4 : in std_logic; + clk, clrn : in std_logic; + pc : buffer std_logic_vector(8 downto 0) + ); +end v_pc; + +architecture pc of v_pc is +constant vector2 : std_logic_vector(8 downto 0) := "000000001"; +constant vector4 : std_logic_vector(8 downto 0) := "000000010"; +signal pcb, stack0, stack1, stack2, stack3 : std_logic_vector(8 downto 0); +begin + +process(clk, clrn) +begin + if clrn = '0' then + pc <= "000000000"; + pcb <= "000000000"; + stack0 <= "000000000"; + stack1 <= "000000000"; + stack2 <= "000000000"; + stack3 <= "000000000"; + elsif clk'event and clk = '1' then + if en = '1' then + pcb <= pc; + if addoffset = '1' then + pc <= pcb + offset; + elsif pull = '1' then + pc <= stack0; + elsif vec2 = '1' then + pc <= vector2; + elsif vec4 = '1' then + pc <= vector4; + else + pc <= pc + 1; + end if; + + if push = '1' then + if addoffset = '1' then + stack0 <= pcb; + else + stack0 <= pcb - 1; + end if; + stack1 <= stack0; + stack2 <= stack1; + stack3 <= stack2; + elsif pull = '1' then + stack0 <= stack1; + stack1 <= stack2; + stack2 <= stack3; + end if; + end if; + end if; +end process; +end pc; Index: RISCMCU/trunk/simulation/v_riscmcu.scf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: RISCMCU/trunk/simulation/v_riscmcu.scf =================================================================== --- RISCMCU/trunk/simulation/v_riscmcu.scf (nonexistent) +++ RISCMCU/trunk/simulation/v_riscmcu.scf (revision 28)

RISCMCU/trunk/simulation/v_riscmcu.scf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: RISCMCU/trunk/hex2mif/readme.txt =================================================================== --- RISCMCU/trunk/hex2mif/readme.txt (nonexistent) +++ RISCMCU/trunk/hex2mif/readme.txt (revision 28) @@ -0,0 +1,14 @@ +hex2mif.exe Program itself +hex2mif.c C source code + +----- +Usage +----- + +hex2mif [filename] + +input: +HEX file from AVR Assember (Generic Format) + +output: +MIF file named 'progam.mif' for MAX+plus II Index: RISCMCU/trunk/hex2mif/hex2mif.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: RISCMCU/trunk/hex2mif/hex2mif.exe =================================================================== --- RISCMCU/trunk/hex2mif/hex2mif.exe (nonexistent) +++ RISCMCU/trunk/hex2mif/hex2mif.exe (revision 28)

RISCMCU/trunk/hex2mif/hex2mif.exe Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: RISCMCU/trunk/hex2mif/hex2mif.c =================================================================== --- RISCMCU/trunk/hex2mif/hex2mif.c (nonexistent) +++ RISCMCU/trunk/hex2mif/hex2mif.c (revision 28) @@ -0,0 +1,49 @@ +#include +#include + +void process(FILE *, FILE *); +void prn_info(); + +int main(int argc, char **argv) +{ + FILE *ifp, *ofp; + + if (argc != 2) { + prn_info(); + exit(1); + } + + ifp = fopen(argv[1], "r"); + ofp = fopen("program.mif", "w"); + process(ifp, ofp); + fclose(ifp); + fclose(ofp); + return 0; +} + +void process(FILE *ifp, FILE *ofp) +{ + int c; + + fprintf(ofp, "width = 16;\ndepth = 512;\n\n" + "address_radix = hex;\ndata_radix = hex;\n\n" + "content begin\n[0..1ff]: 0;\n\n"); + + while((c = getc(ifp)) != EOF) { + if (c != '\n') + putc(c, ofp); + else { + putc(';', ofp); + putc(c, ofp); + } + } + + fprintf(ofp, "\n\nend;"); + + printf("Mission Accomplished"); +} + +void prn_info() +{ + printf("Mission Failed"); +} Index: RISCMCU/trunk/documentation/RISCMCU_Presentation.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: RISCMCU/trunk/documentation/RISCMCU_Presentation.pdf =================================================================== --- RISCMCU/trunk/documentation/RISCMCU_Presentation.pdf (nonexistent) +++ RISCMCU/trunk/documentation/RISCMCU_Presentation.pdf (revision 28)

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RISCMCU/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: RISCMCU/tags/arelease/license.txt =================================================================== --- RISCMCU/tags/arelease/license.txt (nonexistent) +++ RISCMCU/tags/arelease/license.txt (revision 28) @@ -0,0 +1,144 @@ +GNU LESSER GENERAL PUBLIC LICENSE +Version 2.1, February 1999 + + +Copyright (C) 1991, 1999 Free Software Foundation, Inc. +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. + +[This is the first released version of the Lesser GPL. It also counts + as the successor of the GNU Library Public License, version 2, hence + the version number 2.1.] + +Preamble +The licenses for most software are designed to take away your freedom to share and change it. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + + +END OF TERMS AND CONDITIONS \ No newline at end of file Index: RISCMCU/tags/arelease/v_ir.vhd =================================================================== --- RISCMCU/tags/arelease/v_ir.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_ir.vhd (revision 28) @@ -0,0 +1,74 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_ir is + port( instruction : in std_logic_vector(15 downto 0); + en, clk, clrn : in std_logic; + ir : buffer std_logic_vector(15 downto 0); + imm_value : out std_logic_vector(7 downto 0); + rd, rr : out integer range 0 to 15 +); +end v_ir; + +architecture ir of v_ir is +begin + +process(clk,clrn) +begin + if clrn = '0' then + ir <= "0000000000000000"; + elsif clk'event and clk = '1' then + if en = '1' then + ir <= instruction; + end if; + end if; +end process; + +imm_value <= ir(11 downto 8) & ir(3 downto 0); +rd <= conv_integer(ir(7 downto 4)); +rr <= conv_integer(ir(3 downto 0)); + +end ir; Index: RISCMCU/tags/arelease/v_extint.vhd =================================================================== --- RISCMCU/tags/arelease/v_extint.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_extint.vhd (revision 28) @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_extint is + port( clk, clrn, extpin, clr_intf : in std_logic; + rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; + extirq : out std_logic; + c : inout std_logic_vector(7 downto 0)); +end v_extint; + +architecture extint of v_extint is + +signal int0, flag, currentstate, laststate : std_logic; +signal isc0 : integer range 0 to 3; + +begin + +c <= "000000" & conv_std_logic_vector(isc0,2) when rd_mcucr = '1' else + '0' & int0 & "000000" when rd_gimsk = '1' else + "ZZZZZZZZ"; + +extirq <= int0 and not extpin when isc0 = 0 else + int0 and flag; + +process(clk, clrn) +begin + if clrn = '0' then + int0 <= '0'; + isc0 <= 0; + currentstate <= '0'; + laststate <= '0'; + elsif clk'event and clk = '1' then + if wr_gimsk = '1' then + int0 <= c(6); + end if; + if wr_mcucr = '1' then + isc0 <= conv_integer(c(1 downto 0)); + end if; + currentstate <= extpin; + laststate <= currentstate; + end if; +end process; + +process(clrn, clr_intf, clk, isc0, currentstate) +begin + if clrn = '0' or clr_intf = '1' then + flag <= '0'; + elsif clk'event and clk = '1' then + if isc0 = 2 then + if currentstate = '0' and laststate = '1' then + flag <= '1'; + end if; + elsif isc0 = 3 then + if currentstate = '1' and laststate = '0' then + flag <= '1'; + end if; + end if; + end if; +end process; + +end extint; Index: RISCMCU/tags/arelease/program.mif =================================================================== --- RISCMCU/tags/arelease/program.mif (nonexistent) +++ RISCMCU/tags/arelease/program.mif (revision 28) @@ -0,0 +1,165 @@ +width = 16; +depth = 512; + +address_radix = hex; +data_radix = hex; + +content begin +[0..1ff]: 0; + +000000:c002; +000001:9518; +000002:9518; +000003:e045; +000004:ef0f; +000005:bb07; +000006:bb01; +000007:bb05; +000008:bb02; +000009:e001; +00000a:bf03; +00000b:e00f; +00000c:bb04; +00000d:e063; +00000e:e071; +00000f:94e8; +000010:d04f; +000011:d015; +000012:bb78; +000013:d047; +000014:d070; +000015:d02c; +000016:d037; +000017:f026; +000018:d01a; +000019:9573; +00001a:bb78; +00001b:cff8; +00001c:d010; +00001d:d067; +00001e:956a; +00001f:d007; +000020:bb78; +000021:d063; +000022:3060; +000023:f349; +000024:d012; +000025:94e8; +000026:cfef; +000027:2f06; +000028:6f00; +000029:bb08; +00002a:d05a; +00002b:d059; +00002c:9508; +00002d:2700; +00002e:bb05; +00002f:d055; +000030:ef0f; +000031:bb05; +000032:9508; +000033:9897; +000034:d050; +000035:9a97; +000036:9508; +000037:d033; +000038:9101; +000039:bb05; +00003a:d04a; +00003b:ef0f; +00003c:bb05; +00003d:e041; +00003e:d046; +00003f:951a; +000040:f7b9; +000041:9508; +000042:d028; +000043:d02a; +000044:9321; +000045:bb25; +000046:d03e; +000047:ef0f; +000048:bb05; +000049:e041; +00004a:d03a; +00004b:951a; +00004c:f7b1; +00004d:9508; +00004e:d01c; +00004f:d00b; +000050:9478; +000051:d00e; +000052:94f8; +000053:9101; +000054:1320; +000055:9468; +000056:d004; +000057:d03d; +000058:951a; +000059:f7a9; +00005a:9508; +00005b:b303; +00005c:7f00; +00005d:3f00; +00005e:f7e1; +00005f:9508; +000060:b323; +000061:7f20; +000062:3f20; +000063:f3e1; +000064:d030; +000065:b303; +000066:7f00; +000067:1702; +000068:f7b9; +000069:9522; +00006a:9508; +00006b:2f17; +00006c:e6e2; +00006d:9508; +00006e:b722; +00006f:3024; +000070:f010; +000071:5024; +000072:cffc; +000073:3020; +000074:f411; +000075:e02e; +000076:c009; +000077:3021; +000078:f411; +000079:e02d; +00007a:c005; +00007b:3022; +00007c:f411; +00007d:e02b; +00007e:c001; +00007f:e027; +000080:b702; +000081:9507; +000082:9507; +000083:bf02; +000084:9508; +000085:2f3e; +000086:e6e0; +000087:8100; +000088:950a; +000089:8300; +00008a:f7d9; +00008b:e6e1; +00008c:8100; +00008d:950a; +00008e:8300; +00008f:f7b1; +000090:954a; +000091:f7a1; +000092:e045; +000093:2fe3; +000094:9508; +000095:2700; +000096:950a; +000097:f7f1; +000098:9508; + + +end; \ No newline at end of file Index: RISCMCU/tags/arelease/v_ram.vhd =================================================================== --- RISCMCU/tags/arelease/v_ram.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_ram.vhd (revision 28) @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_ram is + port( addrbus : in std_logic_vector(7 downto 0); + rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0) + ); +end entity; + +architecture ram of v_ram is + +component lpm_ram_dq + generic( lpm_width: positive := 8; + lpm_widthad: positive := 8; + lpm_numwords: natural := 256; + lpm_file: string := "ram.mif"; + lpm_indata: string := "unregistered"; + lpm_address_control: string := "unregistered"; + lpm_outdata: string := "unregistered" + ); + port( data: in std_logic_vector(lpm_width-1 downto 0); + address: in std_logic_vector(lpm_widthad-1 downto 0); + we: in std_logic; + inclock: in std_logic := '0'; + outclock: in std_logic := '0'; + q: out std_logic_vector(lpm_width-1 downto 0) + ); +end component; + +signal mar, mbr, ram_out : std_logic_vector(7 downto 0); + +begin + +sram: lpm_ram_dq + port map(data => mbr, address => mar, we => wr_ram, q => ram_out); + +c <= ram_out when rd_ram = '1' else + "ZZZZZZZZ"; + +process(clk,clrn) +begin + if clrn = '0' then + mar <= "00000000"; + mbr <= "00000000"; + elsif clk'event and clk = '1' then + if ld_mbr = '1' then + mbr <= c; + end if; + if ld_mar = '1' then + mar <= addrbus; + end if; + end if; +end process; + +end ram; Index: RISCMCU/tags/arelease/v_timer.vhd =================================================================== --- RISCMCU/tags/arelease/v_timer.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_timer.vhd (revision 28) @@ -0,0 +1,177 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity v_timer is + port( extpin, clr_tov0 : in std_logic; + rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; + rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + timerirq : out std_logic + ); +end v_timer; + +architecture timer of v_timer is + +signal toie0, tov0 : std_logic; +signal cs : integer range 0 to 7; +signal tcnt0 : std_logic_vector(7 downto 0); +signal div1, div2, div4, div8, div16, div32, div64, div128, div256, div512, div1024 : std_logic; +signal timerclk, inc_tcnt0, currentstate, laststate : std_logic; + +begin + +-- Timer Interrupt Request +timerirq <= toie0 and tov0; + +-- Read 4 Registers +c <= "000000" & toie0 & "0" when rd_timsk = '1' else + "000000" & tov0 & "0" when rd_tifr = '1' else + conv_std_logic_vector(cs,8) when rd_tccr0 = '1' else + tcnt0 when rd_tcnt0 = '1' else + "ZZZZZZZZ"; + +-- Select Clock Source +with cs select + timerclk <= '0' when 0, + clk when 1, + div8 when 2, + div64 when 3, + div256 when 4, + div1024 when 5, + not extpin when 6, + extpin when 7; + +-- Timer : clear/write 4 registers, increment timer, set overflow flag, sample clock source +process(clrn, clr_tov0, wr_tifr, c, clk) +begin + if clrn = '0' then + toie0 <= '0'; + cs <= 0; + tcnt0 <= "00000000"; + tov0 <= '0'; + currentstate <= '0'; + laststate <= '0'; + + elsif clr_tov0 = '1' or (wr_tifr = '1' and c(1) = '1') then + tov0 <= '0'; + + elsif clk'event and clk = '1' then + + if wr_tcnt0 = '1' then + tcnt0 <= c; + elsif inc_tcnt0 = '1' then + tcnt0 <= tcnt0 + 1; + if tcnt0 = "11111111" then + tov0 <= '1'; + end if; + end if; + + if wr_timsk = '1' then + toie0 <= c(1); + end if; + if wr_tccr0 = '1' then + cs <= conv_integer(c(2 downto 0)); + end if; + + currentstate <= timerclk; + laststate <= currentstate; + + end if; +end process; + +-- Detect rising edge +inc_tcnt0 <= '1' when (laststate ='0' and currentstate = '1') or cs = 1 else + '0'; + +-- 10 bit prescaler +process(clk, clrn) +begin + if clrn = '0' then + div2 <= '0'; + div4 <= '0'; + div8 <= '0'; + div16 <= '0'; + div32 <= '0'; + div64 <= '0'; + div128 <= '0'; + div256 <= '0'; + div512 <= '0'; + div1024 <= '0'; + + elsif clk'event and clk = '1' then + div2 <= not div2; + if div2 = '1' then + div4 <= not div4; + if div4 = '1' then + div8 <= not div8; + if div8 = '1' then + div16 <= not div16; + if div16 = '1' then + div32 <= not div32; + if div32 = '1' then + div64 <= not div64; + if div64 = '1' then + div128 <= not div128; + if div128 = '1' then + div256 <= not div256; + if div256 = '1' then + div512 <= not div512; + if div512 = '1' then + div1024 <= not div1024; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; +end process; + +end timer; Index: RISCMCU/tags/arelease/v_controlunit.vhd =================================================================== --- RISCMCU/tags/arelease/v_controlunit.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_controlunit.vhd (revision 28) @@ -0,0 +1,548 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity v_controlunit is + port( ir : in std_logic_vector(15 downto 0); + sr : in std_logic_vector(7 downto 0); + clk, clrn : in std_logic; + skip, extirq, timerirq : in std_logic; + + en : buffer std_logic; + wr_reg : buffer std_logic; + rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; + sren : out std_logic_vector (6 downto 0); + + c2a,c2b : out std_logic; + asel : out integer range 0 to 1; + bsel : out integer range 0 to 3; + bitsel : out integer range 0 to 7; + set : out std_logic; + + add, subcp, logic, right, dir, pass_a : out std_logic; + + wcarry : out std_logic; + logicsel : out integer range 0 to 3; + rightsel : out integer range 0 to 2; + dirsel : out integer range 0 to 1; + + addoffset : out std_logic; + push, pull : out std_logic; + + cpse, skiptest : out std_logic; + + bclr,bset : out std_logic; + bld : out std_logic; + + cbisbi : out std_logic; + + vec2, vec4 : buffer std_logic; + + dest : out integer range 0 to 15; + srsel : out integer range 0 to 7; + offset : out std_logic_vector(8 downto 0); + + clr_i, set_i, clr_intf, clr_tov0 : out std_logic; + + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + +); +end v_controlunit; + +architecture controlunit of v_controlunit is + +type statetype is (exes, nop2s, nop1s, lds, sts, cbisbis, sbicss, sleeps); + +signal ibr : std_logic_vector(11 downto 0); +signal state : statetype; + +signal one, neg, imm : std_logic; + +signal +cpcm, sbcm, addm, cpsem, cpm, subm, adcm, andm, eorm, orm, movm, +cpim, sbcim, subim, orim, andim, ldm, stm, comm, negm, swapm, incm, +asrm, lsrm, rorm, decm, bsetm, bclrm, retm, retim, sleepm, +cbisbim, sbicsm, inm, outm, rjmpm, rcallm, ldim, +brbcsm, bldm, bstm, sbrcsm, +ld_incm, ld_decm, st_incm, st_decm : std_logic; + +signal ioaddr : integer range 0 to 16#3f#; +signal rd_io, wr_io, break, irq, get_io, wr_ram_fast, branchtest, branch, jmp : std_logic; + + component v_iodecoder + port( ioaddr : in integer range 0 to 16#3f#; + rd_io, wr_io : in std_logic; + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); + end component; + +begin + +-- Decoder Begin ------------------------------------------------ +-- +-- Decode 46 instructions (48 - NOP - WDR) +-- +-- Combine cbi,sbi (cbisbi) sbrc,sbrs (sbrcs) sbic,sbis (sbic,sbis) +-- +-- Generate C2A and C2B +-- + + +process(ir, wr_reg, get_io, ibr) +begin +-- 43 signal +cpcm <= '0'; sbcm <= '0'; addm <= '0'; +cpsem <= '0'; cpm <= '0'; subm <= '0'; adcm <= '0'; +andm <= '0'; eorm <= '0'; orm <= '0'; movm <= '0'; +cpim <= '0'; sbcim <= '0'; subim <= '0'; orim <= '0'; andim <= '0'; +ldm <= '0'; stm <= '0'; comm <= '0'; negm <= '0'; swapm <= '0'; incm <= '0'; +asrm <= '0'; lsrm <= '0'; rorm <= '0'; decm <= '0'; +bsetm <= '0'; bclrm <= '0'; retm <= '0'; retim <= '0'; sleepm <= '0'; +cbisbim <= '0'; sbicsm <= '0'; +inm <= '0'; outm <= '0'; rjmpm <= '0'; rcallm <= '0'; ldim <= '0'; +brbcsm <= '0'; bldm <= '0'; bstm <= '0'; sbrcsm <= '0'; +ld_incm <= '0'; ld_decm <= '0'; st_incm <= '0'; st_decm <= '0'; + +case ir(15 downto 12) is + when "0000" => + if ir(11 downto 10) = "01" then cpcm <= '1'; end if; + if ir(11 downto 10) = "10" then sbcm <= '1'; end if; + if ir(11 downto 10) = "11" then addm <= '1'; end if; + when "0001" => + if ir(11 downto 10) = "00" then cpsem<= '1'; end if; + if ir(11 downto 10) = "01" then cpm <= '1'; end if; + if ir(11 downto 10) = "10" then subm <= '1'; end if; + if ir(11 downto 10) = "11" then adcm <= '1'; end if; + when "0010" => + if ir(11 downto 10) = "00" then andm <= '1'; end if; + if ir(11 downto 10) = "01" then eorm <= '1'; end if; + if ir(11 downto 10) = "10" then orm <= '1'; end if; + if ir(11 downto 10) = "11" then movm <= '1'; end if; + when "0011" => + cpim <= '1'; + when "0100" => + sbcim <= '1'; + when "0101" => + subim <= '1'; + when "0110" => + orim <= '1'; + when "0111" => + andim <= '1'; + when "1000" => + if ir(11 downto 9) = "000" then ldm <= '1'; end if; + if ir(11 downto 9) = "001" then stm <= '1'; end if; + when "1001" => + if ir(11 downto 9) = "000" then + if ir(1 downto 0) = "01" then ld_incm <= '1'; end if; + if ir(1 downto 0) = "10" then ld_decm <= '1'; end if; + end if; + if ir(11 downto 9) = "001" then + if ir(1 downto 0) = "01" then st_incm <= '1'; end if; + if ir(1 downto 0) = "10" then st_decm <= '1'; end if; + end if; + if ir(11 downto 9) = "010" then + case ir(3 downto 0) is + when "0000" => comm <= '1'; + when "0001" => negm <= '1'; + when "0010" => swapm <= '1'; + when "0011" => incm <= '1'; + when "0101" => asrm <= '1'; + when "0110" => lsrm <= '1'; + when "0111" => rorm <= '1'; + when "1010" => decm <= '1'; + when "1000" => + if ir(8 downto 7) = "00" then bsetm <= '1'; end if; + if ir(8 downto 7) = "01" then bclrm <= '1'; end if; + if ir(8 downto 7) & ir(4) = "100" then retm <= '1'; end if; + if ir(8 downto 7) & ir(4) = "101" then retim <= '1'; end if; + if ir(8 downto 7) = "11" then sleepm <= '1'; end if; + when others => + end case; + elsif ir(11 downto 10) = "10" then + if ir(8) = '0' then cbisbim <= '1'; -- cbi, sbi + else sbicsm <= '1'; end if; -- sbic, sbis + end if; + when "1011" => + if ir(11) = '0' then inm <= '1'; + else outm <= '1'; + end if; + when "1100" => + rjmpm <= '1'; + when "1101" => + rcallm <= '1'; + when "1110" => + ldim <= '1'; + when "1111" => + if ir(11) = '0' then brbcsm <= '1'; end if; + if ir(11 downto 9) = "100" then bldm <= '1'; end if; + if ir(11 downto 9) = "101" then bstm <= '1'; end if; + if ir(11 downto 10) = "11" then sbrcsm <= '1'; end if;-- sbrc, sbrs + when others => +end case; + +if ((ibr(7 downto 4) = ir(7 downto 4)) and wr_reg = '1') or get_io = '1' then + c2a <= '1'; +else + c2a <= '0'; +end if; + +if (ibr(7 downto 4) = ir(3 downto 0)) and wr_reg = '1' then + c2b <= '1'; +else + c2b <= '0'; +end if; + +end process; + +-- Decoder End ------------------------------------------------------------ + + + +-- Helper Signal Begin --------------------------------------------------- +-- +-- 8 : ibr, imm, wcarry, one, neg, logicsel, rightsel, dirsel +-- +process(clk,clrn) +begin +if clrn = '0' then + ibr <= "000000000000"; + + wcarry <= '0'; + logicsel <= 0; + rightsel <= 0; + dirsel <= 0; + +elsif clk'event and clk = '1' then + if en = '1' then + ibr <= ir(11 downto 0); + end if; + + wcarry <= adcm or sbcm or sbcim or cpcm; + + if orm = '1' or orim = '1' then logicsel <= 1; + elsif eorm = '1' then logicsel <= 2; + elsif comm = '1' then logicsel <= 3; + else logicsel <= 0; + end if; + + if rorm = '1' then rightsel <= 1; + elsif asrm = '1' then rightsel <= 2; + else rightsel <= 0; + end if; + + if swapm = '1' then dirsel <= 1; + else dirsel <= 0; + end if; + +end if; +end process; +-- Helper Signal End ----------------------------------------------------- + + +-- Control Unit Begin ---------------------------------------------------- +-- +-- Main Signal : 17 +-- wr_reg, pass_a, sren, rd_io, wr_io +-- add, subcp, logic, right, dir +-- rjmp, rcall, ret, brbc, brbs +-- bclr, bset +-- + +irq <= (timerirq or extirq) and sr(7); +break <= branch or skip or irq; + +process(clk, clrn) +begin + +if clrn = '0' then + + state <= exes; + + + en <= '1'; get_io <= '0'; + pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; + rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; + ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; + add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; + jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; + bclr <= '0'; bset <= '0'; bld <= '0'; + cpse <= '0'; skiptest <= '0'; + cbisbi <= '0'; + + vec2 <= '0'; vec4 <= '0'; set_i <= '0'; + +elsif clk'event and clk = '1' then + + en <= '1'; get_io <= '0'; + pass_a <= '0'; wr_reg <= '0'; sren <= "0000000"; + rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0'; + ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0'; + add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0'; + jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0'; + bclr <= '0'; bset <= '0'; bld <= '0'; + cpse <= '0'; skiptest <= '0'; + cbisbi <= '0'; + + vec2 <= '0'; vec4 <= '0'; set_i <= '0'; + + case state is + + when exes => + + if break = '1' then + + if branch = '1' then + state <= nop1s; + + elsif skip = '1' then + + elsif irq = '1' then + state <= nop2s; + push <= '1'; + if extirq = '1' then + vec2 <= '1'; + else + vec4 <= '1'; + end if; + end if; + + else + + if rjmpm = '1' or rcallm = '1' or retm = '1' or retim = '1' then + state <= nop2s; + elsif cbisbim = '1' then + state <= cbisbis; + elsif sbicsm = '1' then + state <= sbicss; + elsif ldm = '1' or ld_incm = '1' or ld_decm = '1' then + state <= lds; + elsif stm = '1' or st_incm = '1' or st_decm = '1' then + state <= sts; + elsif sleepm = '1' then + state <= sleeps; + end if; + + en <= not (cbisbim or sbicsm + or stm or st_incm or st_decm or + ldm or ld_incm or ld_decm); + + wr_reg <= addm or adcm or incm + or subm or subim or sbcm or sbcim or decm or negm + or andm or andim or orm or orim or eorm or comm + or lsrm or rorm or asrm + or ldim or movm or swapm + or inm; + + pass_a <= outm or stm or st_incm or st_decm; + + wr_io <= outm; + rd_io <= inm or sbicsm or cbisbim; + + ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm; + ld_mbr <= stm or st_incm or st_decm; + + inc_zp <= ld_incm or st_incm; + dec_zp <= ld_decm or st_decm; + + add <= addm or adcm or incm; + subcp <= subm or subim or sbcm or sbcim or decm or negm + or cpm or cpim or cpcm; + logic <= andm or andim or orm or orim or eorm or comm; + right <= lsrm or rorm or asrm; + dir <= ldim or movm or swapm; + + bclr <= bclrm; + bset <= bsetm; + + bld <= bldm; + + cpse <= cpsem; + skiptest <= sbrcsm or cpsem; + + branchtest <= brbcsm; + + jmp <= rjmpm or rcallm; + push <= rcallm; + pull <= retm or retim; + + set_i <= retim; + + get_io <= cbisbim or sbicsm; + + sren(0) <= addm or adcm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm + or comm + or lsrm or rorm or asrm; + + for i in 1 to 4 loop + sren(i) <= addm or adcm or incm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or decm or negm + or andm or andim or orm or orim or eorm or comm + or lsrm or rorm or asrm; + end loop; + + sren(5) <= addm or adcm + or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm; + + sren(6) <= bstm; + + if inm = '1' or outm = '1' then + ioaddr <= conv_integer(ir(10 downto 9) & ir(3 downto 0)); + else + ioaddr <= conv_integer('0' & ir(7 downto 3)); + end if; + + end if; + + when nop2s => + state <= nop1s; + + when nop1s => + state <= exes; + + when cbisbis => + state <= exes; + cbisbi <= '1'; + wr_io <= '1'; + + when sbicss => + state <= exes; + skiptest <= '1'; + + when lds => + state <= exes; + wr_reg <= '1'; + rd_ram <= '1'; + + when sts => + state <= exes; + wr_ram_fast <= '1'; + + when sleeps => + en <= '0'; + if irq = '1' then + en <= '1'; + state <= nop2s; + push <= '1'; + if extirq = '1' then + vec2 <= '1'; + else + vec4 <= '1'; + end if; + end if; + + end case; + +end if; +end process; + +process(state, wr_ram_fast) +begin + if state = exes then + wr_ram <= wr_ram_fast; + else + wr_ram <= '0'; + end if; +end process; + + +-- branch evaluation -------------------------------------------- +process(branchtest, sr, ibr) +begin + if branchtest = '1' and (sr(conv_integer(ibr(2 downto 0))) = not ibr(10)) then + branch <= '1'; + else + branch <= '0'; + end if; +end process; + +------------------------------------------------- + +-- IO address decoder -------------------------- +iodec : v_iodecoder + port map (ioaddr, rd_io, wr_io, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); +---------------------------------------------------- + +-- Intruction Buffer Register (IBR) to signals ------------------ +dest <= conv_integer(ibr(7 downto 4)); + +srsel <= conv_integer(ibr(6 downto 4)); +set <= ibr(9); +bitsel <= conv_integer(ibr(2 downto 0)); + +imm <= subim or sbcim or cpim or andim or orim or ldim; +one <= incm or decm; +neg <= negm; + +asel <= 1 when neg = '1' and get_io = '0' else + 0; + +bsel <= 1 when neg = '1' else + 2 when imm = '1' else + 3 when one = '1' else + 0; + +offset <= ibr(8 downto 0) when jmp = '1' else + ibr(9) & ibr(9) & ibr(9 downto 3); + +addoffset <= branch or jmp; + +clr_i <= vec2 or vec4; +clr_intf <= vec2; +clr_tov0 <= vec4; + +end controlunit; + + Index: RISCMCU/tags/arelease/v_alu.vhd =================================================================== --- RISCMCU/tags/arelease/v_alu.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_alu.vhd (revision 28) @@ -0,0 +1,298 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library lpm; +use lpm.lpm_components.all; + +entity v_alu is + port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); + c2a, c2b : in std_logic; + asel : in integer range 0 to 1; + bsel : in integer range 0 to 3; + + bitsel : in integer range 0 to 7; + set : in std_logic; + c_flag, t_flag : in std_logic; + + add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; + cpse, skiptest : in std_logic; + + wcarry : in std_logic; + logicsel : in integer range 0 to 3; + rightsel : in integer range 0 to 2; + dirsel : in integer range 0 to 1; + + clk, clrn : in std_logic; + + c : buffer std_logic_vector(7 downto 0); + tosr : buffer std_logic_vector (6 downto 0); + skip : out std_logic + ); + +end v_alu; + +architecture alu of v_alu is + +signal a, b : std_logic_vector(7 downto 0); + +signal sr : std_logic_vector(6 downto 0); + +signal cin, overflow, cout : std_logic; + +signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0); + +begin + +-- Fetch Operand To Buffer ------------------------------------------ +process(clrn, clk) +begin + if clrn = '0' then + a <= "00000000"; + b <= "00000000"; + elsif clk'event and clk = '1' then + case asel is + when 0 => + if c2a = '1' then + a <= c; + else + a <= reg_rd; + end if; + when 1 => + a <= "00000000"; + end case; + + case bsel is + when 0 => + if c2b = '1' then + b <= c; + else + b <= reg_rr; + end if; + when 1 => + b <= reg_rd; + when 2 => + b <= imm_value; + when 3 => + b <= "00000001"; + end case; + end if; +end process; + + +-- ALU START------------------------------------------------------------ + + +cin <= c_flag when add = '1' and wcarry = '1' else + '0' when add = '1' and wcarry = '0' else + not c_flag when wcarry = '1' else + '1'; + +-- Adder, Logic, Shift Right, Direct, Bld, Cbisbi --------------------------- + +adder1 : lpm_add_sub + generic map(lpm_width => 8) + port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow); + +with logicsel select + logic_out <= a and b when 0, -- and, andi + a or b when 1, -- or, ori + a xor b when 2, -- eor + not a when 3; -- com + +right_out(6 downto 0) <= a(7 downto 1); +with rightsel select + right_out(7) <= '0' when 0, -- lsr + c_flag when 1, -- ror + a(7) when 2; -- asr + +with dirsel select + dir_out <= b when 0, -- ldi, mov + (a(3 downto 0) & a(7 downto 4)) when 1; -- swap + +process(bld, bitsel, a, t_flag, set) +begin + for i in 0 to 7 loop + if i /= bitsel then + bldcbi_out(i) <= a(i); + elsif bld = '1' then + bldcbi_out(i) <= t_flag; + else + bldcbi_out(i) <= set; + end if; + end loop; +end process; + + +-- Output correct result to Data Bus (C Bus) ------------------------ + +process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a) +begin + + c <= "ZZZZZZZZ"; + + -- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg + if add = '1' or subcp = '1' then + c <= sum; + end if; + + -- and, andi, or, ori, eor, com + if logic = '1' then + c <= logic_out; + end if; + + -- lsr, lsr, asr + if right = '1' then + c <= right_out; + end if; + + -- ldi, mov, swap + if dir = '1' then + c <= dir_out; + end if; + + -- bld, cbisbi + if bld = '1' or cbisbi = '1' then + c <= bldcbi_out; + end if; + + -- out + if pass_a = '1' then + c <= a; + end if; + +end process; +--------------------------------------------------------------------------------- + +-- Perform Skip Test ---------------------------------------------------------- + +process(cpse, skiptest, a, b, set, bitsel, c) +begin + + skip <= '0'; + + -- cpse + if cpse = '1' then + if a = b then + skip <= '1'; + end if; + + -- sbrc, sbrs + elsif skiptest = '1' then + if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then + skip <= '1'; + end if; + + end if; +end process; +-------------------------------------------------------------------------- + +-- Calculate Status Register's Flags ------------------------------------- + +process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel) +begin + +-- C sr(0) + if add = '1' then + sr(0) <= cout; + elsif right = '1' then + sr(0) <= a(0); + elsif logic = '1' then -- com + sr(0) <= '1'; + else -- subcp + sr(0) <= not cout; + --sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7)); + end if; + +-- Z sr(1) + if (add = '1' or subcp = '1') and sum = "00000000" then + sr(1) <= '1'; + elsif logic = '1' and logic_out = "00000000" then + sr(1) <= '1'; + elsif right = '1' and right_out = "00000000" then + sr(1) <= '1'; + else + sr(1) <= '0'; + end if; + +-- N sr(2) + if (add = '1' or subcp = '1') and sum(7) = '1' then + sr(2) <= '1'; + elsif logic = '1' and logic_out(7) = '1' then + sr(2) <= '1'; + elsif right = '1' and right_out(7) = '1' then + sr(2) <= '1'; + else + sr(2) <= '0'; + end if; + +-- V sr(3) + if right = '1' then + sr(3) <= right_out(7) xor a(0); + elsif logic = '1' then + sr(3) <= '0'; + else + sr(3) <= overflow; + end if; + +-- S sr(4) + sr(4) <= sr(2) xor sr(3); + +-- H sr(5) + if add = '1' then + sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3)); + else -- subcp + sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3)); + end if; + +-- T sr(6) + sr(6) <= a(bitsel); + +end process; + +tosr <= sr; + +------------------------------------------------------------------------ + +end alu; Index: RISCMCU/tags/arelease/v_port_bit.vhd =================================================================== --- RISCMCU/tags/arelease/v_port_bit.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_port_bit.vhd (revision 28) @@ -0,0 +1,83 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_port_bit is + port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; + clk,clrn : in std_logic; + c : inout std_logic; + pin : inout std_logic + ); +end v_port_bit; + +architecture port_bit of v_port_bit is + +signal datareg, ddr : std_logic; + +begin + +c <= datareg when rd_port = '1' else + ddr when rd_ddr = '1' else + pin when rd_pin = '1' else + 'Z'; + +pin <= datareg when ddr = '1' else + 'Z'; + +process(clrn, clk) +begin + if clrn = '0' then + datareg <= '0'; + ddr <= '0'; + elsif clk'event and clk = '1' then + if wr_port = '1' then + datareg <= c; + end if; + if wr_ddr = '1' then + ddr <= c; + end if; + end if; +end process; + +end port_bit; + Index: RISCMCU/tags/arelease/ram.mif =================================================================== --- RISCMCU/tags/arelease/ram.mif (nonexistent) +++ RISCMCU/tags/arelease/ram.mif (revision 28) @@ -0,0 +1,10 @@ +width = 8; +depth = 256; + +address_radix = hex; +data_radix = hex; + +content begin +[0..ff]: 0; + +end; \ No newline at end of file Index: RISCMCU/tags/arelease/v_port.vhd =================================================================== --- RISCMCU/tags/arelease/v_port.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_port.vhd (revision 28) @@ -0,0 +1,71 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_port is + port( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + pin : inout std_logic_vector(7 downto 0) + ); +end v_port; + +architecture ioport of v_port is + +component v_port_bit + port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic; + clk,clrn : in std_logic; + c : inout std_logic; + pin : inout std_logic + ); +end component; + +begin + + g1: + for i in 0 to 7 generate + u1 : v_port_bit + port map (rd_port, wr_port, rd_ddr, wr_ddr, rd_pin, clk, clrn, c(i), pin(i)); + end generate; + +end ioport; Index: RISCMCU/tags/arelease/v_sr.vhd =================================================================== --- RISCMCU/tags/arelease/v_sr.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_sr.vhd (revision 28) @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_sr is + port( clk,clrn: in std_logic; + sren,tosr : in std_logic_vector(6 downto 0); + srsel : in integer range 0 to 7; + clr_i,set_i,bset,bclr : in std_logic; + rd_sreg, wr_sreg : in std_logic; + c : inout std_logic_vector(7 downto 0); + sr : inout std_logic_vector(7 downto 0) + ); +end v_sr; + +architecture sr of v_sr is +begin + +c <= sr when rd_sreg = '1' else + "ZZZZZZZZ"; + +process(clk,clrn,rd_sreg,sr) +begin + if clrn = '0' then + sr <= "00000000"; + elsif clk'event and clk = '1' then + if wr_sreg = '1' then + sr <= c; + elsif bset = '1' or bclr = '1' then + sr(srsel) <= bset; + elsif clr_i = '1' or set_i = '1' then + sr(7) <= set_i; + else + for i in 0 to 6 loop + if sren(i) = '1' then + sr(i) <= tosr(i); + end if; + end loop; + end if; + end if; + +end process; + +end sr; + + Index: RISCMCU/tags/arelease/v_gpr.vhd =================================================================== --- RISCMCU/tags/arelease/v_gpr.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_gpr.vhd (revision 28) @@ -0,0 +1,87 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_gpr is + port( c : in std_logic_vector(7 downto 0); + wr_reg, inc_zp, dec_zp : in std_logic; + rd, rr, dest : in integer range 0 to 15; + clk, clrn : in std_logic; + reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) + ); +end v_gpr; + +architecture gpr of v_gpr is + +type regfiletype is array (0 to 15) of std_logic_vector(7 downto 0); + +signal reg : regfiletype; + +begin + +addrbus <= reg(14) - 16#61# when dec_zp = '1' else + reg(14) - 16#60#; + +reg_rd <= reg(rd); +reg_rr <= reg(rr); + +process(clk, clrn) +begin + if clrn = '0' then + for i in 0 to 15 loop + reg(i) <= "00000000"; + end loop; + elsif clk'event and clk = '1' then + if wr_reg = '1' then + reg(dest) <= c; + end if; + if inc_zp = '1' then + reg(14) <= reg(14) + 1; + elsif dec_zp = '1' then + reg(14) <= reg(14) - 1; + end if; + end if; +end process; + +end gpr; Index: RISCMCU/tags/arelease/v_iodecoder.vhd =================================================================== --- RISCMCU/tags/arelease/v_iodecoder.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_iodecoder.vhd (revision 28) @@ -0,0 +1,144 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_iodecoder is + port( ioaddr : in integer range 0 to 16#3f#; + rd_io, wr_io : in std_logic; + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); +end v_iodecoder; + +architecture iodecoder of v_iodecoder is +begin + +process(rd_io, ioaddr) +begin + + rd_sreg <= '0'; + rd_gimsk <= '0'; + rd_timsk <= '0'; + rd_tifr <= '0'; + rd_mcucr <= '0'; + rd_tccr0 <= '0'; + rd_tcnt0 <= '0'; + + rd_portb <= '0'; + rd_ddrb <= '0'; + rd_pinb <= '0'; + rd_portc <= '0'; + rd_ddrc <= '0'; + rd_pinc <= '0'; + rd_portd <= '0'; + rd_ddrd <= '0'; + rd_pind <= '0'; + + if rd_io = '1' then + case ioaddr is + when 16#3f# => rd_sreg <= '1'; + when 16#3b# => rd_gimsk <= '1'; + when 16#39# => rd_timsk <= '1'; + when 16#38# => rd_tifr <= '1'; + when 16#35# => rd_mcucr <= '1'; + when 16#33# => rd_tccr0 <= '1'; + when 16#32# => rd_tcnt0 <= '1'; + + when 16#18# => rd_portb <= '1'; + when 16#17# => rd_ddrb <= '1'; + when 16#16# => rd_pinb <= '1'; + when 16#15# => rd_portc <= '1'; + when 16#14# => rd_ddrc <= '1'; + when 16#13# => rd_pinc <= '1'; + when 16#12# => rd_portd <= '1'; + when 16#11# => rd_ddrd <= '1'; + when 16#10# => rd_pind <= '1'; + when others => + end case; + end if; +end process; + +process(wr_io, ioaddr) +begin + + wr_sreg <= '0'; + wr_gimsk <= '0'; + wr_timsk <= '0'; + wr_tifr <= '0'; + wr_mcucr <= '0'; + wr_tccr0 <= '0'; + wr_tcnt0 <= '0'; + + wr_portb <= '0'; + wr_ddrb <= '0'; + wr_portc <= '0'; + wr_ddrc <= '0'; + wr_portd <= '0'; + wr_ddrd <= '0'; + + if wr_io = '1' then + case ioaddr is + when 16#3f# => wr_sreg <= '1'; + when 16#3b# => wr_gimsk <= '1'; + when 16#39# => wr_timsk <= '1'; + when 16#38# => wr_tifr <= '1'; + when 16#35# => wr_mcucr <= '1'; + when 16#33# => wr_tccr0 <= '1'; + when 16#32# => wr_tcnt0 <= '1'; + + when 16#18# => wr_portb <= '1'; + when 16#17# => wr_ddrb <= '1'; + when 16#15# => wr_portc <= '1'; + when 16#14# => wr_ddrc <= '1'; + when 16#12# => wr_portd <= '1'; + when 16#11# => wr_ddrd <= '1'; + when others => + end case; + end if; +end process; + +end iodecoder; Index: RISCMCU/tags/arelease/v_rom.vhd =================================================================== --- RISCMCU/tags/arelease/v_rom.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_rom.vhd (revision 28) @@ -0,0 +1,80 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_rom is + port( pc : in std_logic_vector(8 downto 0); + instruction : out std_logic_vector(15 downto 0)); +end v_rom; + +architecture rom of v_rom is + + component LPM_ROM + generic ( + LPM_WIDTH: integer := 16; + LPM_WIDTHAD: integer := 9; + LPM_NUMWORDS: integer := 512; + LPM_FILE: string := "program.mif"; + LPM_ADDRESS_CONTROL: string := "UNREGISTERED"; + LPM_OUTDATA: string := "UNREGISTERED" + ); + port ( + ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); + inclock: IN STD_LOGIC := '0'; + outclock: IN STD_LOGIC := '0'; + memenab: IN STD_LOGIC := '1'; + Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0) + ); + end component; + +signal gnd, vcc : std_logic; + +begin + +vcc <= '1'; +gnd <= '0'; + + v1 : LPM_ROM + port map (address => pc, memenab => vcc, q => instruction); + +end rom; Index: RISCMCU/tags/arelease/v_freqdiv.vhd =================================================================== --- RISCMCU/tags/arelease/v_freqdiv.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_freqdiv.vhd (revision 28) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_freqdiv is + port( clock : in std_logic; + div2, div4, div8, div16 : buffer std_logic); +end v_freqdiv; + +architecture myfreqdiv of v_freqdiv is +begin +process(clock) +begin + if clock'event and clock = '1' then + div2 <= not div2; + if div2 = '1' then + div4 <= not div4; + if div4 = '1' then + div8 <= not div8; + if div8 = '1' then + div16 <= not div16; + end if; + end if; + end if; + end if; +end process; +end myfreqdiv; Index: RISCMCU/tags/arelease/v_pc.vhd =================================================================== --- RISCMCU/tags/arelease/v_pc.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_pc.vhd (revision 28) @@ -0,0 +1,98 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity v_pc is + port( offset : in std_logic_vector(8 downto 0); + en, addoffset, push, pull, vec2, vec4 : in std_logic; + clk, clrn : in std_logic; + pc : buffer std_logic_vector(8 downto 0) + ); +end v_pc; + +architecture pc of v_pc is +constant vector2 : std_logic_vector(8 downto 0) := "000000001"; +constant vector4 : std_logic_vector(8 downto 0) := "000000010"; +signal pcb, stack0, stack1, stack2 : std_logic_vector(8 downto 0); +begin + +process(clk, clrn) +begin + if clrn = '0' then + pc <= "000000000"; + pcb <= "000000000"; + stack0 <= "000000000"; + stack1 <= "000000000"; + stack2 <= "000000000"; + elsif clk'event and clk = '1' then + if en = '1' then + pcb <= pc; + if addoffset = '1' then + pc <= pcb + offset; + elsif pull = '1' then + pc <= stack0; + elsif vec2 = '1' then + pc <= vector2; + elsif vec4 = '1' then + pc <= vector4; + else + pc <= pc + 1; + end if; + + if push = '1' then + if addoffset = '1' then + stack0 <= pcb; + else + stack0 <= pcb - 1; + end if; + stack1 <= stack0; + stack2 <= stack1; + elsif pull = '1' then + stack0 <= stack1; + stack1 <= stack2; + end if; + end if; + end if; +end process; +end pc; Index: RISCMCU/tags/arelease/v_riscmcu.vhd =================================================================== --- RISCMCU/tags/arelease/v_riscmcu.vhd (nonexistent) +++ RISCMCU/tags/arelease/v_riscmcu.vhd (revision 28) @@ -0,0 +1,315 @@ +---------------------------------------------------------------------------- +---- ---- +---- WISHBONE RISCMCU IP Core ---- +---- ---- +---- This file is part of the RISCMCU project ---- +---- http://www.opencores.org/projects/riscmcu/ ---- +---- ---- +---- Description ---- +---- Implementation of a RISC Microcontroller based on Atmel AVR ---- +---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ---- +---- ---- +---- Author(s): ---- +---- - Yap Zi He, yapzihe@hotmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity v_riscmcu is + port ( + clock : in STD_LOGIC; + reset : in STD_LOGIC; + pinb : inout STD_LOGIC_VECTOR(7 downto 0); + pinc : inout STD_LOGIC_VECTOR(7 downto 0); + pind : inout STD_LOGIC_VECTOR(7 downto 0) + ); +end v_riscmcu; + +architecture riscmcu of v_riscmcu is + +signal extpin : std_logic; + +signal clk, clrn, div2, div4, div8, div16 : std_logic; +signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0); + +signal pc, offset : std_logic_vector(8 downto 0); +signal instruction, ir : std_logic_vector(15 downto 0); + +signal skip, en, wr_reg : std_logic; +signal sren : std_logic_vector (6 downto 0); +signal c2a, c2b, add, subcp, logic, right, dir, pass_a : std_logic; +signal wcarry : std_logic; +signal logicsel : integer range 0 to 3; +signal rightsel : integer range 0 to 2; +signal dirsel : integer range 0 to 1; +signal addoffset, push, pull, cpse, skiptest : std_logic; +signal bclr,bset, bld, cbisbi : std_logic; +signal dest, rr, rd : integer range 0 to 15; +signal srsel : integer range 0 to 7; +signal imm_value : std_logic_vector(7 downto 0); + +signal tosr : std_logic_vector (6 downto 0); + +signal vec2, vec4, clr_i, set_i, clr_tov0, clr_intf, timerirq, extirq : std_logic; + +signal rd_sreg,wr_sreg,rd_gimsk,wr_gimsk,rd_timsk, wr_timsk, rd_tifr,wr_tifr : std_logic; +signal rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : std_logic; +signal rd_portb,wr_portb,rd_ddrb,wr_ddrb,rd_pinb : std_logic; +signal rd_portc,wr_portc,rd_ddrc,wr_ddrc,rd_pinc : std_logic; +signal rd_portd,wr_portd,rd_ddrd,wr_ddrd,rd_pind : std_logic; + +signal t_flag, c_flag : std_logic; + +signal vcc, gnd : std_logic; + +signal rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp :std_logic; + +signal bitsel : integer range 0 to 7; +signal set : std_logic; + +signal asel : integer range 0 to 1; +signal bsel : integer range 0 to 3; + + component v_freqdiv + port ( clock : in std_logic; + div2, div4, div8, div16 : buffer std_logic + ); + end component; + + component v_pc + port ( offset : in std_logic_vector(8 downto 0); + en, addoffset, push, pull, vec2, vec4 : in std_logic; + clk, clrn : in std_logic; + pc : buffer std_logic_vector(8 downto 0) + ); + end component; + + component v_rom + port ( pc : in std_logic_vector(8 downto 0); + instruction : out std_logic_vector(15 downto 0) + ); + end component; + + component v_ir + port ( instruction : in std_logic_vector(15 downto 0); + en, clk, clrn : in std_logic; + ir : buffer std_logic_vector(15 downto 0); + imm_value : out std_logic_vector(7 downto 0); + rd, rr : out integer range 0 to 15 + ); + end component; + + component v_controlunit + port ( ir : in std_logic_vector(15 downto 0); + sr : in std_logic_vector(7 downto 0); + clk, clrn : in std_logic; + skip, extirq, timerirq : in std_logic; + + en : buffer std_logic; + wr_reg : buffer std_logic; + rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic; + sren : out std_logic_vector (6 downto 0); + + c2a,c2b : out std_logic; + asel : out integer range 0 to 1; + bsel : out integer range 0 to 3; + bitsel : out integer range 0 to 7; + set : out std_logic; + + add, subcp, logic, right, dir, pass_a : out std_logic; + + wcarry : out std_logic; + logicsel : out integer range 0 to 3; + rightsel : out integer range 0 to 2; + dirsel : out integer range 0 to 1; + + addoffset : out std_logic; + push, pull : out std_logic; + + cpse, skiptest : out std_logic; + + bclr,bset : out std_logic; + bld : out std_logic; + + cbisbi : out std_logic; + + vec2, vec4 : buffer std_logic; + + dest : out integer range 0 to 15; + srsel : out integer range 0 to 7; + offset : out std_logic_vector(8 downto 0); + + clr_i, set_i, clr_intf, clr_tov0 : out std_logic; + + rd_sreg, wr_sreg : out std_logic; + rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic; + rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic; + rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic; + rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic; + rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic + ); + end component; + + component v_gpr + port ( c : in std_logic_vector(7 downto 0); + wr_reg, inc_zp, dec_zp : in std_logic; + rd, rr, dest : in integer range 0 to 15; + clk, clrn : in std_logic; + reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0) + ); + end component; + + component v_alu + port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0); + c2a, c2b : in std_logic; + asel : in integer range 0 to 1; + bsel : in integer range 0 to 3; + + bitsel : in integer range 0 to 7; + set : in std_logic; + c_flag, t_flag : in std_logic; + + add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic; + cpse, skiptest : in std_logic; + + wcarry : in std_logic; + logicsel : in integer range 0 to 3; + rightsel : in integer range 0 to 2; + dirsel : in integer range 0 to 1; + + clk, clrn : in std_logic; + + c : buffer std_logic_vector(7 downto 0); + tosr : buffer std_logic_vector (6 downto 0); + skip : out std_logic + ); + end component; + + component v_sr + port ( clk,clrn: in std_logic; + sren,tosr : in std_logic_vector(6 downto 0); + srsel : in integer range 0 to 7; + clr_i,set_i,bset,bclr : in std_logic; + rd_sreg, wr_sreg : in std_logic; + c : inout std_logic_vector(7 downto 0); + sr : inout std_logic_vector(7 downto 0) + ); + end component; + + component v_ram + port ( addrbus : in std_logic_vector(7 downto 0); + rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0) + ); + end component; + + component v_port + port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + pin : inout std_logic_vector(7 downto 0) + ); + end component; + + component v_timer + port ( extpin, clr_tov0 : in std_logic; + rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic; + rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic; + clk, clrn : in std_logic; + c : inout std_logic_vector(7 downto 0); + timerirq : out std_logic + ); + end component; + + component v_extint + port ( clk, clrn, extpin, clr_intf : in std_logic; + rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic; + extirq : out std_logic; + c : inout std_logic_vector(7 downto 0) + ); + end component; + +begin + + U_v_freqdiv: v_freqdiv + port map (clock, div2, div4, div8, div16); + + U_v_pc: v_pc + port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc); + + U_v_rom: v_rom + port map (pc, instruction); + + U_v_ir: v_ir + port map (instruction, en, clk, clrn, ir, imm_value, rd, rr); + + U_v_controlunit: v_controlunit + port map (ir, sr, clk, clrn, skip, extirq, timerirq, en, wr_reg, rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp, sren, c2a, c2b, asel, bsel, bitsel, set, add, subcp, logic, right, dir, pass_a, wcarry, logicsel, rightsel, dirsel, addoffset, push, pull, cpse, skiptest, bclr, bset, bld, cbisbi, vec2, vec4, dest, srsel, offset, clr_i, set_i, clr_intf, clr_tov0, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind); + + U_v_gpr: v_gpr + port map (c, wr_reg, inc_zp, dec_zp, rd, rr, dest, clk, clrn, reg_rd, reg_rr, addrbus); + + U_v_alu: v_alu + port map (reg_rd, reg_rr, imm_value, c2a, c2b, asel, bsel, bitsel, set, c_flag, t_flag, add, subcp, logic, right, dir, bld, cbisbi, pass_a, cpse, skiptest, wcarry, logicsel, rightsel, dirsel, clk, clrn, c, tosr, skip); + + U_v_sr: v_sr + port map (clk, clrn, sren, tosr, srsel, clr_i, set_i, bset, bclr, rd_sreg, wr_sreg, c, sr); + + U_v_ram: v_ram + port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c); + + U_v_timer: v_timer + port map (extpin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq); + + U_v_extint: v_extint + port map (clk, clrn, extpin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c); + + + U_v_portB: v_port + port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb); + + U_v_portC: v_port + port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc); + + U_v_portD: v_port + port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind); + + extpin <= pind(7); + clrn <= reset; + clk <= div4; + vcc <= '1'; + gnd <= '0'; + t_flag <= sr(6); + c_flag <= sr(0); + +end riscmcu; + + Index: RISCMCU/tags =================================================================== --- RISCMCU/tags (nonexistent) +++ RISCMCU/tags (revision 28)

RISCMCU/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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