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Rev 27 → Rev 28

/raytrac/trunk/uf.vhd
41,7 → 41,7
 
entity uf is
generic (
use_std_logic_signed : string := "YES"
use_std_logic_signed : string := "NO"
);
port (
 
57,13 → 57,13
 
 
 
 
--Stage 1 signals
 
 
 
 
-- Some support signals
 
143,9 → 143,9
if use_std_logic_signed="YES" generate
-- Adder Instantiation (sTaGe 1)
stage1adderProc:
process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stage1opcode)
process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stageSRopcode)
begin
case (stage1opcode) is
case (stageSRopcode) is
when '1' => -- Cross Product
stage1a0 <= stage1p0-stage1p1;
stage1a2 <= stage1p4-stage1p5;
166,12 → 166,12
a0low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stage1opcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stage1opcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
186,12 → 186,12
a2low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stage1opcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stage1opcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
-- Adder Instantiation (Stage 2)
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
248,14 → 248,14
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
--! Este proceso describe la manera en que se organizan las etapas de pipe.
 
 
uf_seq: process (clk,rst)
begin
if rst=rstMasterValue then
stage0opcode <= '0';
stage1opcode <= '0';
stageMopcode <= '0';
stageSRopcode <= '0';
stage2a2 <= (others => '0');
stage2p3 <= (others => '0');
270,8 → 270,8
stage2a0 <= stage1a0;
-- Opcode control sequence
stage0opcode <= opcode;
stage1opcode <= stage0opcode;
stageMopcode <= opcode;
stageSRopcode <= stageMopcode;
end if;
end process uf_seq;

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